Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T32,T33
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T6
1	0	1	Covered	T2,T27,T28
1	1	0	Covered	T2,T4,T31
1	1	1	Covered	T2,T4,T31

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T31
0	1	Covered	T2,T4,T31
1	0	Covered	T21,T17,T34

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T31
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T21,T17,T34

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T31
1	0	Covered	T33
1	1	Covered	T2,T4,T31

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T2,T3,T29

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T31,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T35,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T29,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T3,T6

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T2,T4,T31

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T2,T4,T31
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T2,T34,T36
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T6,T34,T36
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T31,T34,T37
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T20,T38,T34
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T4,T21
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T4,T21
TimeoutSt->Phase0St	172	Covered	T2,T4,T31

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T31
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T31
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T31
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T34,T36
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T34,T36
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T34,T37
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T38,T34
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1208	0	0
CheckAccumTrig0_A	2147483647	2237	0	0
CheckAccumTrig1_A	2147483647	81	0	0
CheckClr_A	2147483647	1019	0	0
CheckEn_A	2147483647	1096134519	0	0
CheckPhase0_A	2147483647	2526	0	0
CheckPhase1_A	2147483647	2474	0	0
CheckPhase2_A	2147483647	2420	0	0
CheckPhase3_A	2147483647	2370	0	0
CheckTimeout0_A	2147483647	5176	0	0
CheckTimeoutSt1_A	2147483647	457586	0	0
CheckTimeoutSt2_A	2147483647	4836	0	0
CheckTimeoutStTrig_A	2147483647	252	0	0
ErrorStAllEscAsserted_A	2147483647	6557	0	0
ErrorStIsTerminal_A	2147483647	5477	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1208	0	0
T13	374652	234	0	0
T14	0	303	0	0
T15	0	257	0	0
T39	0	134	0	0
T40	0	280	0	0
T41	11656	0	0	0
T42	88864	0	0	0
T43	3650492	0	0	0
T44	4760	0	0	0
T45	440648	0	0	0
T46	1255788	0	0	0
T47	1020448	0	0	0
T48	105576	0	0	0
T49	186508	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2237	0	0
T1	3889	1	0	0
T2	777708	15	0	0
T3	149880	1	0	0
T4	733652	6	0	0
T6	151508	2	0	0
T7	0	1	0	0
T8	0	3	0	0
T9	0	7	0	0
T10	0	8	0	0
T16	0	7	0	0
T17	0	2	0	0
T21	0	10	0	0
T23	0	1	0	0
T24	0	5	0	0
T25	0	1	0	0
T27	22340	0	0	0
T28	15500	0	0	0
T29	1457316	2	0	0
T30	18400	1	0	0
T31	103252	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T50	11757	1	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	81	0	0
T8	629245	0	0	0
T9	375100	0	0	0
T10	416514	0	0	0
T16	923178	0	0	0
T17	0	1	0	0
T21	131244	1	0	0
T22	41045	0	0	0
T23	563487	0	0	0
T24	34564	0	0	0
T25	2248	0	0	0
T34	0	3	0	0
T36	228682	0	0	0
T37	0	1	0	0
T47	0	1	0	0
T52	202135	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	290302	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	2730	0	0	0
T69	10231	0	0	0
T70	50384	0	0	0
T71	1533	0	0	0
T72	52760	0	0	0
T73	31711	0	0	0
T74	931604	0	0	0
T75	123667	0	0	0
T76	21427	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1019	0	0
T2	388854	4	0	0
T3	74940	0	0	0
T4	366826	1	0	0
T6	75754	1	0	0
T9	0	2	0	0
T10	833028	3	0	0
T16	0	6	0	0
T17	700706	2	0	0
T18	1952646	0	0	0
T19	164078	0	0	0
T20	111017	2	0	0
T21	0	9	0	0
T24	34564	1	0	0
T26	1630706	0	0	0
T27	11170	0	0	0
T28	7750	0	0	0
T29	728658	0	0	0
T30	9200	0	0	0
T31	51626	1	0	0
T34	0	15	0	0
T38	0	3	0	0
T50	7838	0	0	0
T68	5460	0	0	0
T77	21671	1	0	0
T78	0	1	0	0
T79	0	4	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	31228	0	0	0
T86	6371	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1096134519	0	0
T1	15556	12513	0	0
T2	777708	625004	0	0
T3	149880	113868	0	0
T4	733652	325917	0	0
T6	151508	75669	0	0
T27	22340	19300	0	0
T28	15500	8723	0	0
T29	1457316	746765	0	0
T30	18400	12865	0	0
T31	103252	79934	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2526	0	0
T1	3889	1	0	0
T2	777708	17	0	0
T3	149880	1	0	0
T4	733652	7	0	0
T6	151508	2	0	0
T7	0	1	0	0
T8	0	3	0	0
T9	0	8	0	0
T10	0	8	0	0
T16	0	7	0	0
T17	0	3	0	0
T21	0	19	0	0
T23	0	1	0	0
T24	0	5	0	0
T27	22340	0	0	0
T28	15500	0	0	0
T29	1457316	2	0	0
T30	18400	1	0	0
T31	103252	2	0	0
T35	0	1	0	0
T38	0	2	0	0
T50	11757	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2474	0	0
T1	3889	1	0	0
T2	777708	17	0	0
T3	149880	1	0	0
T4	733652	7	0	0
T6	151508	1	0	0
T7	0	1	0	0
T8	0	3	0	0
T9	0	8	0	0
T10	0	7	0	0
T16	0	7	0	0
T17	0	3	0	0
T21	0	19	0	0
T23	0	1	0	0
T24	0	5	0	0
T27	22340	0	0	0
T28	15500	0	0	0
T29	1457316	2	0	0
T30	18400	1	0	0
T31	103252	2	0	0
T35	0	1	0	0
T38	0	2	0	0
T50	11757	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2420	0	0
T1	3889	1	0	0
T2	777708	17	0	0
T3	149880	1	0	0
T4	733652	7	0	0
T6	151508	1	0	0
T7	0	1	0	0
T8	0	3	0	0
T9	0	8	0	0
T10	0	7	0	0
T16	0	7	0	0
T17	0	3	0	0
T21	0	19	0	0
T23	0	1	0	0
T24	0	5	0	0
T27	22340	0	0	0
T28	15500	0	0	0
T29	1457316	2	0	0
T30	18400	1	0	0
T31	103252	1	0	0
T35	0	1	0	0
T38	0	2	0	0
T50	11757	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2370	0	0
T1	3889	1	0	0
T2	777708	17	0	0
T3	149880	1	0	0
T4	733652	7	0	0
T6	151508	1	0	0
T7	0	1	0	0
T8	0	3	0	0
T9	0	8	0	0
T10	0	6	0	0
T16	0	7	0	0
T17	0	3	0	0
T21	0	19	0	0
T23	0	1	0	0
T24	0	5	0	0
T27	22340	0	0	0
T28	15500	0	0	0
T29	1457316	2	0	0
T30	18400	1	0	0
T31	103252	1	0	0
T35	0	1	0	0
T38	0	2	0	0
T50	11757	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5176	0	0
T2	777708	35	0	0
T3	149880	0	0	0
T4	733652	10	0	0
T6	151508	0	0	0
T9	0	58	0	0
T17	0	11	0	0
T21	0	11	0	0
T22	0	1	0	0
T24	0	1	0	0
T26	0	82	0	0
T27	22340	0	0	0
T28	15500	0	0	0
T29	1457316	0	0	0
T30	18400	0	0	0
T31	103252	2	0	0
T34	0	37	0	0
T37	0	90	0	0
T50	15676	0	0	0
T51	0	3	0	0
T52	0	2	0	0
T86	0	3	0	0
T87	0	10	0	0
T88	0	9	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	457586	0	0
T2	777708	2237	0	0
T3	149880	0	0	0
T4	733652	1540	0	0
T6	151508	0	0	0
T9	0	7794	0	0
T17	0	806	0	0
T21	0	412	0	0
T22	0	177	0	0
T24	0	161	0	0
T26	0	4683	0	0
T27	22340	0	0	0
T28	15500	0	0	0
T29	1457316	0	0	0
T30	18400	0	0	0
T31	103252	78	0	0
T34	0	3787	0	0
T37	0	7523	0	0
T50	15676	0	0	0
T51	0	131	0	0
T52	0	133	0	0
T70	0	319	0	0
T86	0	184	0	0
T87	0	707	0	0
T88	0	1635	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4836	0	0
T2	777708	32	0	0
T3	149880	0	0	0
T4	733652	9	0	0
T6	151508	0	0	0
T9	0	57	0	0
T17	0	9	0	0
T21	0	2	0	0
T22	0	1	0	0
T24	0	1	0	0
T26	0	82	0	0
T27	22340	0	0	0
T28	15500	0	0	0
T29	1457316	0	0	0
T30	18400	0	0	0
T31	103252	0	0	0
T34	0	36	0	0
T36	0	1	0	0
T37	0	398	0	0
T50	15676	0	0	0
T51	0	3	0	0
T52	0	1	0	0
T70	0	2	0	0
T73	0	1	0	0
T86	0	3	0	0
T87	0	10	0	0
T88	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	252	0	0
T2	583281	3	0	0
T3	112410	0	0	0
T4	550239	1	0	0
T6	113631	0	0	0
T8	629245	0	0	0
T9	375100	1	0	0
T10	416514	0	0	0
T16	923178	0	0	0
T21	131244	8	0	0
T22	41045	0	0	0
T23	563487	0	0	0
T24	34564	0	0	0
T25	2248	0	0	0
T27	16755	0	0	0
T28	11625	0	0	0
T29	1092987	0	0	0
T30	13800	0	0	0
T31	77439	2	0	0
T34	0	2	0	0
T37	0	7	0	0
T50	11757	0	0	0
T68	2730	0	0	0
T70	0	1	0	0
T73	0	2	0	0
T75	0	2	0	0
T79	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0
T89	0	3	0	0
T90	0	1	0	0
T91	0	4	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	3	0	0
T95	0	2	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6557	0	0
T13	374652	1430	0	0
T14	0	1429	0	0
T15	0	1498	0	0
T39	0	725	0	0
T40	0	1475	0	0
T41	11656	0	0	0
T42	88864	0	0	0
T43	3650492	0	0	0
T44	4760	0	0	0
T45	440648	0	0	0
T46	1255788	0	0	0
T47	1020448	0	0	0
T48	105576	0	0	0
T49	186508	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5477	0	0
T13	374652	1190	0	0
T14	0	1189	0	0
T15	0	1258	0	0
T39	0	605	0	0
T40	0	1235	0	0
T41	11656	0	0	0
T42	88864	0	0	0
T43	3650492	0	0	0
T44	4760	0	0	0
T45	440648	0	0	0
T46	1255788	0	0	0
T47	1020448	0	0	0
T48	105576	0	0	0
T49	186508	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	15556	15336	0	0
T2	777708	777424	0	0
T3	149880	149576	0	0
T4	733652	732680	0	0
T6	151508	151156	0	0
T27	22340	22048	0	0
T28	15500	15200	0	0
T29	1457316	1456944	0	0
T30	18400	18120	0	0
T31	103252	102944	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	15556	15336	0	0
T2	777708	777424	0	0
T3	149880	149576	0	0
T4	733652	732680	0	0
T6	151508	151156	0	0
T27	22340	22048	0	0
T28	15500	15200	0	0
T29	1457316	1456944	0	0
T30	18400	18120	0	0
T31	103252	102944	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T6
1	0	1	Covered	T2,T27,T28
1	1	0	Covered	T2,T4,T31
1	1	1	Covered	T2,T21,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T22
0	1	Covered	T2,T21,T34
1	0	Covered	T21,T17,T34

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T21,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T17,T34

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T22
1	0	Not Covered
1	1	Covered	T2,T21,T34

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T2,T3,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T21,T9

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T35,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T6,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T21,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T3,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T6
Phase1St	198	Covered	T2,T3,T6
Phase2St	215	Covered	T2,T3,T6
Phase3St	233	Covered	T2,T3,T6
TerminalSt	249	Covered	T2,T3,T6
TimeoutSt	159	Covered	T2,T21,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T2,T3,T6
IdleSt->TimeoutSt	159	Covered	T2,T21,T22
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T2,T36,T89
Phase0St->Phase1St	198	Covered	T2,T3,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T34,T36
Phase1St->Phase2St	215	Covered	T2,T3,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T34,T37,T69
Phase2St->Phase3St	233	Covered	T2,T3,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T20,T38,T34
Phase3St->TerminalSt	249	Covered	T2,T3,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T4,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T21,T22
TimeoutSt->Phase0St	172	Covered	T2,T21,T17

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T17
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T36,T79
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T34,T36
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T34,T37,T69
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T38,T34
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	623977616	273	0	0
CheckAccumTrig0_A	623977616	801	0	0
CheckAccumTrig1_A	623977616	28	0	0
CheckClr_A	623977616	351	0	0
CheckEn_A	623608333	222868399	0	0
CheckPhase0_A	623977616	876	0	0
CheckPhase1_A	623977616	854	0	0
CheckPhase2_A	623977616	834	0	0
CheckPhase3_A	623977616	817	0	0
CheckTimeout0_A	623977616	983	0	0
CheckTimeoutSt1_A	623977616	102212	0	0
CheckTimeoutSt2_A	623977616	889	0	0
CheckTimeoutStTrig_A	623977616	65	0	0
ErrorStAllEscAsserted_A	623977616	1662	0	0
ErrorStIsTerminal_A	623977616	1392	0	0
EscStateOut_A	623606642	623537595	0	0
u_state_regs_A	623977616	623795199	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	273	0	0
T13	93663	48	0	0
T14	0	45	0	0
T15	0	61	0	0
T39	0	47	0	0
T40	0	72	0	0
T41	2914	0	0	0
T42	22216	0	0	0
T43	912623	0	0	0
T44	1190	0	0	0
T45	110162	0	0	0
T46	313947	0	0	0
T47	255112	0	0	0
T48	26394	0	0	0
T49	46627	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	801	0	0
T2	194427	7	0	0
T3	37470	1	0	0
T4	183413	3	0	0
T6	37877	2	0	0
T8	0	1	0	0
T9	0	4	0	0
T16	0	7	0	0
T21	0	7	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T35	0	1	0	0
T50	3919	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	28	0	0
T8	629245	0	0	0
T9	375100	0	0	0
T10	416514	0	0	0
T16	923178	0	0	0
T17	0	1	0	0
T21	131244	1	0	0
T22	41045	0	0	0
T23	563487	0	0	0
T24	34564	0	0	0
T25	2248	0	0	0
T34	0	3	0	0
T37	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T68	2730	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	351	0	0
T2	194427	2	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	1	0	0
T9	0	2	0	0
T16	0	6	0	0
T20	0	2	0	0
T21	0	4	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T34	0	8	0	0
T38	0	1	0	0
T50	3919	0	0	0
T77	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623608333	222868399	0	0
T1	3889	3097	0	0
T2	194427	180755	0	0
T3	37470	1689	0	0
T4	183413	14170	0	0
T6	37877	636	0	0
T27	5585	2767	0	0
T28	3875	2613	0	0
T29	364329	364235	0	0
T30	4600	3180	0	0
T31	25813	20262	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	876	0	0
T2	194427	7	0	0
T3	37470	1	0	0
T4	183413	3	0	0
T6	37877	2	0	0
T8	0	1	0	0
T9	0	4	0	0
T16	0	7	0	0
T21	0	9	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T35	0	1	0	0
T50	3919	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	854	0	0
T2	194427	7	0	0
T3	37470	1	0	0
T4	183413	3	0	0
T6	37877	1	0	0
T8	0	1	0	0
T9	0	4	0	0
T16	0	7	0	0
T21	0	9	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T35	0	1	0	0
T50	3919	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	834	0	0
T2	194427	7	0	0
T3	37470	1	0	0
T4	183413	3	0	0
T6	37877	1	0	0
T8	0	1	0	0
T9	0	4	0	0
T16	0	7	0	0
T21	0	9	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T35	0	1	0	0
T50	3919	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	817	0	0
T2	194427	7	0	0
T3	37470	1	0	0
T4	183413	3	0	0
T6	37877	1	0	0
T8	0	1	0	0
T9	0	4	0	0
T16	0	7	0	0
T21	0	9	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T35	0	1	0	0
T50	3919	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	983	0	0
T2	194427	7	0	0
T3	37470	0	0	0
T4	183413	0	0	0
T6	37877	0	0	0
T9	0	14	0	0
T17	0	4	0	0
T21	0	3	0	0
T22	0	1	0	0
T26	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T50	3919	0	0	0
T51	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	102212	0	0
T2	194427	413	0	0
T3	37470	0	0	0
T4	183413	0	0	0
T6	37877	0	0	0
T9	0	2325	0	0
T17	0	255	0	0
T21	0	193	0	0
T22	0	177	0	0
T26	0	101	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T50	3919	0	0	0
T51	0	47	0	0
T86	0	141	0	0
T87	0	79	0	0
T88	0	548	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	889	0	0
T2	194427	6	0	0
T3	37470	0	0	0
T4	183413	0	0	0
T6	37877	0	0	0
T9	0	14	0	0
T17	0	3	0	0
T21	0	1	0	0
T22	0	1	0	0
T26	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T50	3919	0	0	0
T51	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	65	0	0
T2	194427	1	0	0
T3	37470	0	0	0
T4	183413	0	0	0
T6	37877	0	0	0
T21	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T34	0	1	0	0
T37	0	3	0	0
T50	3919	0	0	0
T82	0	1	0	0
T89	0	1	0	0
T91	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1662	0	0
T13	93663	351	0	0
T14	0	364	0	0
T15	0	402	0	0
T39	0	181	0	0
T40	0	364	0	0
T41	2914	0	0	0
T42	22216	0	0	0
T43	912623	0	0	0
T44	1190	0	0	0
T45	110162	0	0	0
T46	313947	0	0	0
T47	255112	0	0	0
T48	26394	0	0	0
T49	46627	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1392	0	0
T13	93663	291	0	0
T14	0	304	0	0
T15	0	342	0	0
T39	0	151	0	0
T40	0	304	0	0
T41	2914	0	0	0
T42	22216	0	0	0
T43	912623	0	0	0
T44	1190	0	0	0
T45	110162	0	0	0
T46	313947	0	0	0
T47	255112	0	0	0
T48	26394	0	0	0
T49	46627	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623606642	623537595	0	0
T1	3889	3834	0	0
T2	194427	194356	0	0
T3	37470	37394	0	0
T4	183413	183170	0	0
T6	37877	37789	0	0
T27	5585	5512	0	0
T28	3875	3800	0	0
T29	364329	364236	0	0
T30	4600	4530	0	0
T31	25813	25736	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	623795199	0	0
T1	3889	3834	0	0
T2	194427	194356	0	0
T3	37470	37394	0	0
T4	183413	183170	0	0
T6	37877	37789	0	0
T27	5585	5512	0	0
T28	3875	3800	0	0
T29	364329	364236	0	0
T30	4600	4530	0	0
T31	25813	25736	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T28
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T21
1	0	1	Covered	T1,T28,T7
1	1	0	Covered	T2,T4,T31
1	1	1	Covered	T2,T4,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T21
0	1	Covered	T21,T37,T70
1	0	Covered	T17,T79,T81

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T79,T81

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T21
1	0	Not Covered
1	1	Covered	T21,T37,T70

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T7,T21,T24

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T2,T4,T23

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T9,T97,T34

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T4,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T2,T4,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T2,T4,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T89,T56,T98
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T10,T81,T99
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T100,T101,T102
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T10,T34,T103
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T4,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T24
TimeoutSt->Phase0St	172	Covered	T21,T17,T37

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T17,T37
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T104,T105
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T81,T99
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T100,T101,T102
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T10,T34,T103
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T24,T10,T37
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	623977616	329	0	0
CheckAccumTrig0_A	623977616	460	0	0
CheckAccumTrig1_A	623977616	23	0	0
CheckClr_A	623977616	211	0	0
CheckEn_A	623608333	303622442	0	0
CheckPhase0_A	623977616	536	0	0
CheckPhase1_A	623977616	526	0	0
CheckPhase2_A	623977616	519	0	0
CheckPhase3_A	623977616	507	0	0
CheckTimeout0_A	623977616	1053	0	0
CheckTimeoutSt1_A	623977616	101968	0	0
CheckTimeoutSt2_A	623977616	966	0	0
CheckTimeoutStTrig_A	623977616	62	0	0
ErrorStAllEscAsserted_A	623977616	1618	0	0
ErrorStIsTerminal_A	623977616	1348	0	0
EscStateOut_A	623606642	623537595	0	0
u_state_regs_A	623977616	623795199	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	329	0	0
T13	93663	65	0	0
T14	0	86	0	0
T15	0	75	0	0
T39	0	34	0	0
T40	0	69	0	0
T41	2914	0	0	0
T42	22216	0	0	0
T43	912623	0	0	0
T44	1190	0	0	0
T45	110162	0	0	0
T46	313947	0	0	0
T47	255112	0	0	0
T48	26394	0	0	0
T49	46627	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	460	0	0
T1	3889	1	0	0
T2	194427	2	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T21	0	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T26	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	23	0	0
T17	350353	1	0	0
T18	976323	0	0	0
T19	164078	0	0	0
T20	111017	0	0	0
T26	815353	0	0	0
T32	0	1	0	0
T38	650273	0	0	0
T56	0	1	0	0
T77	21671	0	0	0
T79	0	1	0	0
T81	0	3	0	0
T85	31228	0	0	0
T86	6371	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	184538	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	211	0	0
T8	629245	0	0	0
T9	375100	0	0	0
T10	416514	3	0	0
T16	923178	0	0	0
T17	350353	0	0	0
T18	976323	0	0	0
T24	34564	1	0	0
T25	2248	0	0	0
T26	815353	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T68	2730	0	0	0
T76	0	1	0	0
T79	0	1	0	0
T89	0	1	0	0
T95	0	4	0	0
T112	0	1	0	0
T113	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623608333	303622442	0	0
T1	3889	3157	0	0
T2	194427	153620	0	0
T3	37470	37393	0	0
T4	183413	102973	0	0
T6	37877	37788	0	0
T27	5585	5511	0	0
T28	3875	594	0	0
T29	364329	364235	0	0
T30	4600	3259	0	0
T31	25813	25735	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	536	0	0
T1	3889	1	0	0
T2	194427	2	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T17	0	1	0	0
T21	0	2	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	526	0	0
T1	3889	1	0	0
T2	194427	2	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T10	0	3	0	0
T17	0	1	0	0
T21	0	2	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	519	0	0
T1	3889	1	0	0
T2	194427	2	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T10	0	3	0	0
T17	0	1	0	0
T21	0	2	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	507	0	0
T1	3889	1	0	0
T2	194427	2	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T10	0	2	0	0
T17	0	1	0	0
T21	0	2	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1053	0	0
T2	194427	7	0	0
T3	37470	0	0	0
T4	183413	5	0	0
T6	37877	0	0	0
T9	0	16	0	0
T17	0	4	0	0
T21	0	1	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T34	0	35	0	0
T50	3919	0	0	0
T51	0	2	0	0
T86	0	1	0	0
T87	0	9	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	101968	0	0
T2	194427	478	0	0
T3	37470	0	0	0
T4	183413	878	0	0
T6	37877	0	0	0
T9	0	2290	0	0
T17	0	309	0	0
T21	0	43	0	0
T24	0	161	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T34	0	3121	0	0
T50	3919	0	0	0
T51	0	84	0	0
T86	0	43	0	0
T87	0	628	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	966	0	0
T2	194427	7	0	0
T3	37470	0	0	0
T4	183413	5	0	0
T6	37877	0	0	0
T9	0	16	0	0
T17	0	3	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T34	0	35	0	0
T37	0	309	0	0
T50	3919	0	0	0
T51	0	2	0	0
T86	0	1	0	0
T87	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	62	0	0
T8	629245	0	0	0
T9	375100	0	0	0
T10	416514	0	0	0
T16	923178	0	0	0
T21	131244	1	0	0
T22	41045	0	0	0
T23	563487	0	0	0
T24	34564	0	0	0
T25	2248	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T68	2730	0	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T81	0	1	0	0
T89	0	2	0	0
T112	0	1	0	0
T114	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1618	0	0
T13	93663	372	0	0
T14	0	341	0	0
T15	0	377	0	0
T39	0	175	0	0
T40	0	353	0	0
T41	2914	0	0	0
T42	22216	0	0	0
T43	912623	0	0	0
T44	1190	0	0	0
T45	110162	0	0	0
T46	313947	0	0	0
T47	255112	0	0	0
T48	26394	0	0	0
T49	46627	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1348	0	0
T13	93663	312	0	0
T14	0	281	0	0
T15	0	317	0	0
T39	0	145	0	0
T40	0	293	0	0
T41	2914	0	0	0
T42	22216	0	0	0
T43	912623	0	0	0
T44	1190	0	0	0
T45	110162	0	0	0
T46	313947	0	0	0
T47	255112	0	0	0
T48	26394	0	0	0
T49	46627	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623606642	623537595	0	0
T1	3889	3834	0	0
T2	194427	194356	0	0
T3	37470	37394	0	0
T4	183413	183170	0	0
T6	37877	37789	0	0
T27	5585	5512	0	0
T28	3875	3800	0	0
T29	364329	364236	0	0
T30	4600	4530	0	0
T31	25813	25736	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	623795199	0	0
T1	3889	3834	0	0
T2	194427	194356	0	0
T3	37470	37394	0	0
T4	183413	183170	0	0
T6	37877	37789	0	0
T27	5585	5512	0	0
T28	3875	3800	0	0
T29	364329	364236	0	0
T30	4600	4530	0	0
T31	25813	25736	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T29,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T29,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T29,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T32
1	1	1	Covered	T2,T29,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T4
1	0	1	Covered	T2,T29,T26
1	1	0	Covered	T2,T31,T21
1	1	1	Covered	T2,T4,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T21
0	1	Covered	T2,T9,T34
1	0	Covered	T52,T53,T58

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T52,T53,T58

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T21
1	0	Not Covered
1	1	Covered	T2,T9,T34

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T24
1	Covered	T2,T29,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T29,T4
1	Covered	T2,T9,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T29,T4
1	Covered	T2,T17,T38

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T29,T21
1	Covered	T4,T24,T8

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T29,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T4,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T21,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T4,T24

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T29,T4
Phase1St	198	Covered	T2,T29,T4
Phase2St	215	Covered	T2,T29,T4
Phase3St	233	Covered	T2,T29,T4
TerminalSt	249	Covered	T2,T29,T4
TimeoutSt	159	Covered	T2,T4,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T2,T29,T4
IdleSt->TimeoutSt	159	Covered	T2,T4,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T34,T63,T115
Phase0St->Phase1St	198	Covered	T2,T29,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T116,T98,T62
Phase1St->Phase2St	215	Covered	T2,T29,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T84,T115,T117
Phase2St->Phase3St	233	Covered	T2,T29,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T79,T54,T118
Phase3St->TerminalSt	249	Covered	T2,T29,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T4,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T21
TimeoutSt->Phase0St	172	Covered	T2,T9,T34

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T29,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T34
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T63
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T29,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T29,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T116,T98,T62
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T29,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T29,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T84,T115,T117
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T29,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T29,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T79,T54,T118
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T29,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T29,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T38,T34
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T29,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	623977616	294	0	0
CheckAccumTrig0_A	623977616	442	0	0
CheckAccumTrig1_A	623977616	17	0	0
CheckClr_A	623977616	182	0	0
CheckEn_A	623608333	291133224	0	0
CheckPhase0_A	623977616	510	0	0
CheckPhase1_A	623977616	505	0	0
CheckPhase2_A	623977616	498	0	0
CheckPhase3_A	623977616	493	0	0
CheckTimeout0_A	623977616	1505	0	0
CheckTimeoutSt1_A	623977616	130962	0	0
CheckTimeoutSt2_A	623977616	1432	0	0
CheckTimeoutStTrig_A	623977616	54	0	0
ErrorStAllEscAsserted_A	623977616	1597	0	0
ErrorStIsTerminal_A	623977616	1327	0	0
EscStateOut_A	623606642	623537595	0	0
u_state_regs_A	623977616	623795199	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	294	0	0
T13	93663	69	0	0
T14	0	75	0	0
T15	0	53	0	0
T39	0	29	0	0
T40	0	68	0	0
T41	2914	0	0	0
T42	22216	0	0	0
T43	912623	0	0	0
T44	1190	0	0	0
T45	110162	0	0	0
T46	313947	0	0	0
T47	255112	0	0	0
T48	26394	0	0	0
T49	46627	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	442	0	0
T2	194427	2	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	0	0	0
T8	0	1	0	0
T10	0	4	0	0
T17	0	2	0	0
T21	0	1	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	1	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T38	0	2	0	0
T50	3919	0	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	17	0	0
T36	228682	0	0	0
T47	0	1	0	0
T52	202135	1	0	0
T53	0	1	0	0
T58	0	1	0	0
T61	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T69	10231	0	0	0
T70	50384	0	0	0
T71	1533	0	0	0
T72	52760	0	0	0
T73	31711	0	0	0
T74	931604	0	0	0
T75	123667	0	0	0
T76	21427	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	182	0	0
T10	416514	3	0	0
T17	350353	0	0	0
T18	976323	0	0	0
T19	164078	0	0	0
T20	111017	0	0	0
T26	815353	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T68	2730	0	0	0
T77	21671	0	0	0
T78	0	1	0	0
T79	0	4	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	31228	0	0	0
T86	6371	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623608333	291133224	0	0
T1	3889	3122	0	0
T2	194427	145318	0	0
T3	37470	37393	0	0
T4	183413	99495	0	0
T6	37877	640	0	0
T27	5585	5511	0	0
T28	3875	2758	0	0
T29	364329	7106	0	0
T30	4600	3200	0	0
T31	25813	25735	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	510	0	0
T2	194427	3	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T17	0	2	0	0
T21	0	1	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	1	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T38	0	2	0	0
T50	3919	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	505	0	0
T2	194427	3	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T17	0	2	0	0
T21	0	1	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	1	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T38	0	2	0	0
T50	3919	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	498	0	0
T2	194427	3	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T17	0	2	0	0
T21	0	1	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	1	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T38	0	2	0	0
T50	3919	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	493	0	0
T2	194427	3	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T17	0	2	0	0
T21	0	1	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	1	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T38	0	2	0	0
T50	3919	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1505	0	0
T2	194427	13	0	0
T3	37470	0	0	0
T4	183413	2	0	0
T6	37877	0	0	0
T9	0	4	0	0
T17	0	1	0	0
T21	0	1	0	0
T26	0	41	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T34	0	2	0	0
T37	0	46	0	0
T50	3919	0	0	0
T52	0	1	0	0
T88	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	130962	0	0
T2	194427	862	0	0
T3	37470	0	0	0
T4	183413	321	0	0
T6	37877	0	0	0
T9	0	511	0	0
T17	0	124	0	0
T21	0	152	0	0
T26	0	2368	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T34	0	666	0	0
T37	0	3963	0	0
T50	3919	0	0	0
T70	0	319	0	0
T88	0	561	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1432	0	0
T2	194427	12	0	0
T3	37470	0	0	0
T4	183413	2	0	0
T6	37877	0	0	0
T9	0	3	0	0
T17	0	1	0	0
T21	0	1	0	0
T26	0	41	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T34	0	1	0	0
T37	0	45	0	0
T50	3919	0	0	0
T70	0	2	0	0
T88	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	54	0	0
T2	194427	1	0	0
T3	37470	0	0	0
T4	183413	0	0	0
T6	37877	0	0	0
T9	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T50	3919	0	0	0
T73	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1597	0	0
T13	93663	349	0	0
T14	0	347	0	0
T15	0	370	0	0
T39	0	161	0	0
T40	0	370	0	0
T41	2914	0	0	0
T42	22216	0	0	0
T43	912623	0	0	0
T44	1190	0	0	0
T45	110162	0	0	0
T46	313947	0	0	0
T47	255112	0	0	0
T48	26394	0	0	0
T49	46627	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1327	0	0
T13	93663	289	0	0
T14	0	287	0	0
T15	0	310	0	0
T39	0	131	0	0
T40	0	310	0	0
T41	2914	0	0	0
T42	22216	0	0	0
T43	912623	0	0	0
T44	1190	0	0	0
T45	110162	0	0	0
T46	313947	0	0	0
T47	255112	0	0	0
T48	26394	0	0	0
T49	46627	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623606642	623537595	0	0
T1	3889	3834	0	0
T2	194427	194356	0	0
T3	37470	37394	0	0
T4	183413	183170	0	0
T6	37877	37789	0	0
T27	5585	5512	0	0
T28	3875	3800	0	0
T29	364329	364236	0	0
T30	4600	4530	0	0
T31	25813	25736	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	623795199	0	0
T1	3889	3834	0	0
T2	194427	194356	0	0
T3	37470	37394	0	0
T4	183413	183170	0	0
T6	37877	37789	0	0
T27	5585	5512	0	0
T28	3875	3800	0	0
T29	364329	364236	0	0
T30	4600	4530	0	0
T31	25813	25736	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T29,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T29,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T29,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T33
1	1	1	Covered	T2,T29,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T4
1	0	1	Covered	T2,T28,T29
1	1	0	Covered	T2,T4,T21
1	1	1	Covered	T2,T4,T31

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T31
0	1	Covered	T2,T4,T31
1	0	Covered	T55,T56,T58

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T31
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T55,T56,T58

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T31
1	0	Covered	T33
1	1	Covered	T2,T4,T31

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T31
1	Covered	T29,T4,T30

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T29,T4
1	Covered	T2,T31,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T29,T4
1	Covered	T21,T8,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T29,T4
1	Covered	T2,T4,T21

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T29,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T4,T30,T31

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T29,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T29,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T29,T4
Phase1St	198	Covered	T2,T29,T4
Phase2St	215	Covered	T2,T29,T4
Phase3St	233	Covered	T2,T29,T4
TerminalSt	249	Covered	T2,T29,T4
TimeoutSt	159	Covered	T2,T4,T31

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T2,T29,T4
IdleSt->TimeoutSt	159	Covered	T2,T4,T31
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T89,T112,T98
Phase0St->Phase1St	198	Covered	T2,T29,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T112,T119,T120
Phase1St->Phase2St	215	Covered	T2,T29,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T112,T81
Phase2St->Phase3St	233	Covered	T2,T29,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T91,T112,T121
Phase3St->TerminalSt	249	Covered	T2,T29,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T4,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T9
TimeoutSt->Phase0St	172	Covered	T2,T4,T31

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T29,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T31
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T31
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T31
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T9
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T112,T98,T62
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T29,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T29,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T112,T119,T120
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T29,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T29,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T112,T81
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T29,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T29,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T91,T112,T121
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T29,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T29,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T21,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T29,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	623977616	312	0	0
CheckAccumTrig0_A	623977616	534	0	0
CheckAccumTrig1_A	623977616	13	0	0
CheckClr_A	623977616	275	0	0
CheckEn_A	623608333	278510454	0	0
CheckPhase0_A	623977616	604	0	0
CheckPhase1_A	623977616	589	0	0
CheckPhase2_A	623977616	569	0	0
CheckPhase3_A	623977616	553	0	0
CheckTimeout0_A	623977616	1635	0	0
CheckTimeoutSt1_A	623977616	122444	0	0
CheckTimeoutSt2_A	623977616	1549	0	0
CheckTimeoutStTrig_A	623977616	71	0	0
ErrorStAllEscAsserted_A	623977616	1680	0	0
ErrorStIsTerminal_A	623977616	1410	0	0
EscStateOut_A	623606642	623537595	0	0
u_state_regs_A	623977616	623795199	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	312	0	0
T13	93663	52	0	0
T14	0	97	0	0
T15	0	68	0	0
T39	0	24	0	0
T40	0	71	0	0
T41	2914	0	0	0
T42	22216	0	0	0
T43	912623	0	0	0
T44	1190	0	0	0
T45	110162	0	0	0
T46	313947	0	0	0
T47	255112	0	0	0
T48	26394	0	0	0
T49	46627	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	534	0	0
T2	194427	4	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	1	0	0
T30	4600	1	0	0
T31	25813	0	0	0
T50	3919	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	13	0	0
T32	0	2	0	0
T55	290302	1	0	0
T56	176548	1	0	0
T57	138060	0	0	0
T58	206964	1	0	0
T100	327150	0	0	0
T108	0	1	0	0
T110	0	1	0	0
T116	531583	0	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	1365	0	0	0
T127	8507	0	0	0
T128	27091	0	0	0
T129	54187	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	275	0	0
T2	194427	2	0	0
T3	37470	0	0	0
T4	183413	0	0	0
T6	37877	0	0	0
T17	0	2	0	0
T18	0	1	0	0
T21	0	5	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	1	0	0
T34	0	5	0	0
T38	0	1	0	0
T50	3919	0	0	0
T51	0	1	0	0
T97	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623608333	278510454	0	0
T1	3889	3137	0	0
T2	194427	145311	0	0
T3	37470	37393	0	0
T4	183413	109279	0	0
T6	37877	36605	0	0
T27	5585	5511	0	0
T28	3875	2758	0	0
T29	364329	11189	0	0
T30	4600	3226	0	0
T31	25813	8202	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	604	0	0
T2	194427	5	0	0
T3	37470	0	0	0
T4	183413	2	0	0
T6	37877	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T21	0	7	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	1	0	0
T30	4600	1	0	0
T31	25813	2	0	0
T50	3919	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	589	0	0
T2	194427	5	0	0
T3	37470	0	0	0
T4	183413	2	0	0
T6	37877	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T21	0	7	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	1	0	0
T30	4600	1	0	0
T31	25813	2	0	0
T50	3919	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	569	0	0
T2	194427	5	0	0
T3	37470	0	0	0
T4	183413	2	0	0
T6	37877	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T21	0	7	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	1	0	0
T30	4600	1	0	0
T31	25813	1	0	0
T50	3919	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	553	0	0
T2	194427	5	0	0
T3	37470	0	0	0
T4	183413	2	0	0
T6	37877	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T21	0	7	0	0
T24	0	1	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	1	0	0
T30	4600	1	0	0
T31	25813	1	0	0
T50	3919	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1635	0	0
T2	194427	8	0	0
T3	37470	0	0	0
T4	183413	3	0	0
T6	37877	0	0	0
T9	0	24	0	0
T17	0	2	0	0
T21	0	6	0	0
T26	0	40	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	2	0	0
T37	0	44	0	0
T50	3919	0	0	0
T52	0	1	0	0
T88	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	122444	0	0
T2	194427	484	0	0
T3	37470	0	0	0
T4	183413	341	0	0
T6	37877	0	0	0
T9	0	2668	0	0
T17	0	118	0	0
T21	0	24	0	0
T26	0	2214	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	78	0	0
T37	0	3560	0	0
T50	3919	0	0	0
T52	0	133	0	0
T88	0	526	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1549	0	0
T2	194427	7	0	0
T3	37470	0	0	0
T4	183413	2	0	0
T6	37877	0	0	0
T9	0	24	0	0
T17	0	2	0	0
T26	0	40	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	0	0	0
T36	0	1	0	0
T37	0	44	0	0
T50	3919	0	0	0
T52	0	1	0	0
T73	0	1	0	0
T88	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	71	0	0
T2	194427	1	0	0
T3	37470	0	0	0
T4	183413	1	0	0
T6	37877	0	0	0
T21	0	6	0	0
T27	5585	0	0	0
T28	3875	0	0	0
T29	364329	0	0	0
T30	4600	0	0	0
T31	25813	2	0	0
T50	3919	0	0	0
T73	0	1	0	0
T90	0	1	0	0
T91	0	3	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1680	0	0
T13	93663	358	0	0
T14	0	377	0	0
T15	0	349	0	0
T39	0	208	0	0
T40	0	388	0	0
T41	2914	0	0	0
T42	22216	0	0	0
T43	912623	0	0	0
T44	1190	0	0	0
T45	110162	0	0	0
T46	313947	0	0	0
T47	255112	0	0	0
T48	26394	0	0	0
T49	46627	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	1410	0	0
T13	93663	298	0	0
T14	0	317	0	0
T15	0	289	0	0
T39	0	178	0	0
T40	0	328	0	0
T41	2914	0	0	0
T42	22216	0	0	0
T43	912623	0	0	0
T44	1190	0	0	0
T45	110162	0	0	0
T46	313947	0	0	0
T47	255112	0	0	0
T48	26394	0	0	0
T49	46627	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623606642	623537595	0	0
T1	3889	3834	0	0
T2	194427	194356	0	0
T3	37470	37394	0	0
T4	183413	183170	0	0
T6	37877	37789	0	0
T27	5585	5512	0	0
T28	3875	3800	0	0
T29	364329	364236	0	0
T30	4600	4530	0	0
T31	25813	25736	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623977616	623795199	0	0
T1	3889	3834	0	0
T2	194427	194356	0	0
T3	37470	37394	0	0
T4	183413	183170	0	0
T6	37877	37789	0	0
T27	5585	5512	0	0
T28	3875	3800	0	0
T29	364329	364236	0	0
T30	4600	4530	0	0
T31	25813	25736	0	0