Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61440426	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29584116

1

T1

637

T2

17431

T3

3993

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13890023	1			T1	255		T2	6680		T3	1734
values[0x0]	37811718	1			T1	862		T2	24413		T3	5476
values[0x1]	39322801	1			T1	864		T2	24233		T3	5410

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52693076	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38331466

1

T1

807

T2

22029

T3

5053

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	285819	1			T1	4		T3	30		T6	39
valid_sources[0x01]	274789	1			T1	4		T3	46		T6	23
valid_sources[0x02]	278495	1			T1	5		T3	29		T6	32
valid_sources[0x03]	274294	1			T1	7		T3	40		T6	31
valid_sources[0x04]	280448	1			T1	10		T3	36		T6	29
valid_sources[0x05]	284440	1			T1	8		T3	58		T6	32
valid_sources[0x06]	278884	1			T1	8		T3	55		T6	34
valid_sources[0x07]	282035	1			T1	11		T3	69		T6	30
valid_sources[0x08]	279233	1			T1	8		T3	51		T6	37
valid_sources[0x09]	276474	1			T1	10		T3	48		T6	32
valid_sources[0x0a]	284418	1			T1	9		T3	44		T6	34
valid_sources[0x0b]	301911	1			T1	6		T3	88		T6	36
valid_sources[0x0c]	291128	1			T1	6		T3	32		T6	39
valid_sources[0x0d]	278986	1			T1	6		T3	28		T6	45
valid_sources[0x0e]	278320	1			T1	4		T3	45		T6	38
valid_sources[0x0f]	284038	1			T1	8		T3	45		T6	29
valid_sources[0x10]	288999	1			T1	4		T3	60		T6	21
valid_sources[0x11]	301060	1			T1	6		T3	26		T6	44
valid_sources[0x12]	275615	1			T1	6		T3	43		T6	39
valid_sources[0x13]	280900	1			T1	13		T3	48		T6	34
valid_sources[0x14]	279742	1			T1	8		T3	59		T6	42
valid_sources[0x15]	290723	1			T1	8		T3	34		T6	36
valid_sources[0x16]	717511	1			T1	3		T3	50		T6	30
valid_sources[0x17]	289717	1			T1	13		T3	33		T6	45
valid_sources[0x18]	287085	1			T1	10		T3	54		T6	40
valid_sources[0x19]	275215	1			T1	7		T3	43		T6	40
valid_sources[0x1a]	274039	1			T1	4		T3	66		T6	34
valid_sources[0x1b]	280744	1			T1	9		T3	34		T6	33
valid_sources[0x1c]	1357744	1			T1	9		T3	34		T6	31
valid_sources[0x1d]	597995	1			T1	9		T3	65		T6	39
valid_sources[0x1e]	299441	1			T1	6		T3	56		T6	39
valid_sources[0x1f]	668109	1			T1	11		T3	49		T6	26
valid_sources[0x20]	273393	1			T1	8		T3	48		T6	34
valid_sources[0x21]	272116	1			T1	6		T3	49		T6	38
valid_sources[0x22]	274421	1			T1	6		T3	60		T6	31
valid_sources[0x23]	277515	1			T1	10		T3	48		T6	38
valid_sources[0x24]	281982	1			T1	9		T3	46		T6	38
valid_sources[0x25]	277928	1			T1	6		T3	39		T6	27
valid_sources[0x26]	273107	1			T1	11		T3	41		T6	32
valid_sources[0x27]	274073	1			T1	8		T3	46		T6	42
valid_sources[0x28]	874526	1			T1	5		T3	38		T6	36
valid_sources[0x29]	272723	1			T1	10		T3	40		T6	39
valid_sources[0x2a]	282838	1			T1	11		T3	50		T6	34
valid_sources[0x2b]	276315	1			T1	7		T3	48		T6	24
valid_sources[0x2c]	583911	1			T1	9		T3	42		T6	27
valid_sources[0x2d]	580262	1			T1	4		T3	50		T6	36
valid_sources[0x2e]	289827	1			T1	9		T3	40		T6	42
valid_sources[0x2f]	276216	1			T1	3		T3	45		T6	37
valid_sources[0x30]	276374	1			T1	10		T3	53		T6	30
valid_sources[0x31]	274866	1			T1	7		T3	51		T6	44
valid_sources[0x32]	277138	1			T1	5		T3	34		T6	35
valid_sources[0x33]	277708	1			T1	10		T3	41		T6	31
valid_sources[0x34]	287339	1			T1	7		T3	50		T6	30
valid_sources[0x35]	283106	1			T1	5		T3	61		T6	31
valid_sources[0x36]	713096	1			T1	7		T3	48		T6	24
valid_sources[0x37]	288593	1			T1	6		T3	54		T6	36
valid_sources[0x38]	283134	1			T1	8		T3	54		T6	36
valid_sources[0x39]	670520	1			T1	14		T3	66		T6	32
valid_sources[0x3a]	300189	1			T1	12		T3	43		T6	39
valid_sources[0x3b]	293360	1			T1	4		T3	40		T6	36
valid_sources[0x3c]	281125	1			T1	9		T3	67		T6	36
valid_sources[0x3d]	742035	1			T1	9		T3	50		T6	40
valid_sources[0x3e]	277368	1			T1	6		T3	37		T6	27
valid_sources[0x3f]	277252	1			T1	11		T3	40		T6	33
valid_sources[0x40]	281915	1			T1	9		T3	64		T6	38
valid_sources[0x41]	285086	1			T1	7		T3	39		T6	44
valid_sources[0x42]	282765	1			T1	5		T3	58		T6	38
valid_sources[0x43]	277800	1			T1	9		T3	55		T6	44
valid_sources[0x44]	1067315	1			T1	6		T3	39		T6	41
valid_sources[0x45]	280212	1			T1	10		T3	37		T6	50
valid_sources[0x46]	281759	1			T1	6		T3	71		T6	38
valid_sources[0x47]	726992	1			T1	11		T3	29		T6	44
valid_sources[0x48]	285892	1			T1	10		T3	48		T6	38
valid_sources[0x49]	297140	1			T1	9		T3	44		T6	41
valid_sources[0x4a]	284981	1			T1	9		T3	45		T6	42
valid_sources[0x4b]	291629	1			T1	8		T3	72		T6	45
valid_sources[0x4c]	606593	1			T1	8		T3	55		T6	45
valid_sources[0x4d]	273839	1			T1	7		T3	69		T6	26
valid_sources[0x4e]	278820	1			T1	7		T3	37		T6	36
valid_sources[0x4f]	280305	1			T1	7		T3	57		T6	45
valid_sources[0x50]	1110339	1			T1	3		T3	42		T6	43
valid_sources[0x51]	283632	1			T1	6		T3	54		T6	31
valid_sources[0x52]	646696	1			T1	6		T3	53		T6	40
valid_sources[0x53]	276806	1			T1	9		T3	46		T6	34
valid_sources[0x54]	288841	1			T1	9		T3	53		T6	38
valid_sources[0x55]	275271	1			T1	6		T3	41		T6	34
valid_sources[0x56]	587443	1			T1	6		T3	54		T6	47
valid_sources[0x57]	285136	1			T1	7		T3	39		T6	34
valid_sources[0x58]	537199	1			T1	7		T3	38		T6	27
valid_sources[0x59]	281439	1			T1	7		T3	48		T6	35
valid_sources[0x5a]	279978	1			T1	9		T3	54		T6	33
valid_sources[0x5b]	280058	1			T1	10		T3	51		T6	37
valid_sources[0x5c]	279576	1			T1	11		T3	49		T6	28
valid_sources[0x5d]	279598	1			T1	9		T3	48		T6	38
valid_sources[0x5e]	288345	1			T1	6		T3	39		T6	45
valid_sources[0x5f]	279846	1			T1	7		T3	47		T6	30
valid_sources[0x60]	295919	1			T1	12		T3	48		T6	41
valid_sources[0x61]	311552	1			T1	9		T3	69		T6	30
valid_sources[0x62]	284486	1			T1	11		T3	38		T6	33
valid_sources[0x63]	284809	1			T1	5		T3	46		T6	36
valid_sources[0x64]	277146	1			T1	4		T3	68		T6	32
valid_sources[0x65]	278533	1			T1	10		T3	45		T6	33
valid_sources[0x66]	532839	1			T1	4		T3	52		T6	26
valid_sources[0x67]	286921	1			T1	7		T3	75		T6	28
valid_sources[0x68]	704162	1			T1	6		T3	35		T6	36
valid_sources[0x69]	285599	1			T1	6		T3	59		T6	47
valid_sources[0x6a]	277229	1			T1	6		T3	68		T6	30
valid_sources[0x6b]	852804	1			T1	8		T3	41		T6	28
valid_sources[0x6c]	280216	1			T1	9		T3	39		T6	36
valid_sources[0x6d]	644665	1			T1	10		T3	53		T6	38
valid_sources[0x6e]	274416	1			T1	5		T3	58		T6	39
valid_sources[0x6f]	622992	1			T1	8		T3	56		T6	26
valid_sources[0x70]	296126	1			T1	5		T3	76		T6	41
valid_sources[0x71]	307744	1			T1	10		T3	37		T6	37
valid_sources[0x72]	288865	1			T1	7		T3	45		T6	28
valid_sources[0x73]	292967	1			T1	11		T3	72		T6	28
valid_sources[0x74]	278374	1			T1	10		T3	65		T6	32
valid_sources[0x75]	297909	1			T1	5		T3	51		T6	30
valid_sources[0x76]	282097	1			T1	3		T3	50		T6	18
valid_sources[0x77]	277070	1			T1	6		T3	37		T6	39
valid_sources[0x78]	280712	1			T1	10		T3	47		T6	51
valid_sources[0x79]	511999	1			T1	6		T3	44		T6	41
valid_sources[0x7a]	281563	1			T1	9		T3	37		T6	35
valid_sources[0x7b]	307896	1			T1	5		T3	51		T6	35
valid_sources[0x7c]	273659	1			T1	4		T3	72		T6	35
valid_sources[0x7d]	278345	1			T1	12		T3	48		T6	39
valid_sources[0x7e]	282687	1			T1	11		T3	52		T6	32
valid_sources[0x7f]	275216	1			T1	8		T3	52		T6	37
valid_sources[0x80]	275363	1			T1	7		T3	45		T6	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6840452

1

T1

133

T2

3290

T3

844

values[0x0]

all_enables

biggest_size

14391308

1

T1

307

T2

9062

T3

2030

values[0x1]

all_enables

biggest_size

8352356

1

T1

197

T2

5079

T3

1119