Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T219
1	1	Covered	T2,T3,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	17228	0	0
DisabledNoTrigBkwd_A	2147483647	713999	0	0
DisabledNoTrigFwd_A	2147483647	1336985254	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17228	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	0	0	0
T21	5013	1579	0	0
T22	4408	1050	0	0
T23	33376	0	0	0
T48	29503	0	0	0
T49	160338	0	0	0
T86	45192	0	0	0
T130	46899	0	0	0
T131	10319	0	0	0
T206	16130	0	0	0
T219	0	1076	0	0
T220	0	731	0	0
T221	0	482	0	0
T222	3974	1569	0	0
T223	1294	551	0	0
T224	6838	1035	0	0
T225	0	677	0	0
T226	0	573	0	0
T227	0	683	0	0
T228	0	438	0	0
T229	0	895	0	0
T230	0	847	0	0
T231	0	1366	0	0
T232	0	602	0	0
T233	0	1198	0	0
T234	0	1004	0	0
T235	0	383	0	0
T236	0	489	0	0
T237	626508	0	0	0
T238	256450	0	0	0
T239	171078	0	0	0
T240	121895	0	0	0
T241	12072	0	0	0
T242	558392	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	713999	0	0
T2	609924	63	0	0
T3	57292	5	0	0
T4	435952	8848	0	0
T5	1429104	1116	0	0
T6	409948	156	0	0
T7	881018	978	0	0
T8	0	474	0	0
T9	0	1188	0	0
T16	0	6257	0	0
T17	0	481	0	0
T20	90390	115	0	0
T24	0	141	0	0
T25	21384	8	0	0
T26	50584	41	0	0
T27	66188	27	0	0
T28	104772	3	0	0
T29	36312	0	0	0
T48	0	315	0	0
T49	0	16	0	0
T50	0	14	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1336985254	0	0
T1	98544	93206	0	0
T2	2439696	1320935	0	0
T3	114584	32564	0	0
T4	435952	219124	0	0
T6	409948	76919	0	0
T25	21384	15121	0	0
T26	50584	38691	0	0
T27	66188	47049	0	0
T28	104772	78879	0	0
T29	36312	22061	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T25
1	1	Covered	T2,T3,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T220
1	1	Covered	T2,T3,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T25

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	614671084	6244	0	0
DisabledNoTrigBkwd_A	614671084	212666	0	0
DisabledNoTrigFwd_A	614671084	305602568	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	6244	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	0	0	0
T21	5013	1579	0	0
T22	4408	1050	0	0
T23	33376	0	0	0
T48	29503	0	0	0
T49	160338	0	0	0
T130	46899	0	0	0
T131	10319	0	0	0
T220	0	731	0	0
T221	0	482	0	0
T223	0	551	0	0
T226	0	573	0	0
T229	0	895	0	0
T235	0	383	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	212666	0	0
T2	609924	63	0	0
T3	28646	0	0	0
T4	108988	2759	0	0
T5	357276	41	0	0
T6	102487	34	0	0
T7	0	4	0	0
T20	0	110	0	0
T25	5346	6	0	0
T26	12646	41	0	0
T27	16547	19	0	0
T28	26193	3	0	0
T29	9078	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	305602568	0	0
T1	24636	24549	0	0
T2	609924	9707	0	0
T3	28646	607	0	0
T4	108988	582	0	0
T6	102487	3071	0	0
T25	5346	2575	0	0
T26	12646	936	0	0
T27	16547	6164	0	0
T28	26193	582	0	0
T29	9078	5234	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T25
1	1	Covered	T3,T6,T29

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T222,T231,T233
1	1	Covered	T3,T6,T29

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	614671084	4133	0	0
DisabledNoTrigBkwd_A	614671084	173190	0	0
DisabledNoTrigFwd_A	614671084	355240905	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	4133	0	0
T86	22596	0	0	0
T222	3974	1569	0	0
T223	1294	0	0	0
T224	3419	0	0	0
T231	0	1366	0	0
T233	0	1198	0	0
T237	626508	0	0	0
T238	256450	0	0	0
T239	171078	0	0	0
T240	121895	0	0	0
T241	6036	0	0	0
T242	279196	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	173190	0	0
T3	28646	5	0	0
T4	108988	6089	0	0
T5	357276	17	0	0
T6	102487	35	0	0
T8	0	474	0	0
T16	0	4572	0	0
T20	30130	2	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	0	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	1	0	0
T49	0	13	0	0
T50	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	355240905	0	0
T1	24636	19559	0	0
T2	609924	605244	0	0
T3	28646	3813	0	0
T4	108988	586	0	0
T6	102487	36687	0	0
T25	5346	5252	0	0
T26	12646	12585	0	0
T27	16547	16481	0	0
T28	26193	26099	0	0
T29	9078	6156	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T25
1	0	Covered	T3,T6,T25
1	1	Covered	T3,T6,T25

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T224,T227,T228
1	1	Covered	T3,T6,T25

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T25,T27

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	614671084	3605	0	0
DisabledNoTrigBkwd_A	614671084	169585	0	0
DisabledNoTrigFwd_A	614671084	328591604	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	3605	0	0
T86	22596	0	0	0
T97	397462	0	0	0
T99	64242	0	0	0
T206	16130	0	0	0
T215	13529	0	0	0
T224	3419	1035	0	0
T227	0	683	0	0
T228	0	438	0	0
T230	0	847	0	0
T232	0	602	0	0
T241	6036	0	0	0
T242	279196	0	0	0
T243	548882	0	0	0
T244	29438	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	169585	0	0
T4	108988	0	0	0
T5	357276	1056	0	0
T6	102487	45	0	0
T7	440509	318	0	0
T9	0	1186	0	0
T17	0	481	0	0
T20	30130	2	0	0
T25	5346	2	0	0
T26	12646	0	0	0
T27	16547	3	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	40	0	0
T50	0	12	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	328591604	0	0
T1	24636	24549	0	0
T2	609924	609665	0	0
T3	28646	27525	0	0
T4	108988	108978	0	0
T6	102487	34007	0	0
T25	5346	2042	0	0
T26	12646	12585	0	0
T27	16547	15217	0	0
T28	26193	26099	0	0
T29	9078	8994	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T25,T27,T29
1	1	Covered	T3,T6,T27

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T219,T225,T234
1	1	Covered	T3,T6,T27

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T27,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	614671084	3246	0	0
DisabledNoTrigBkwd_A	614671084	158558	0	0
DisabledNoTrigFwd_A	614671084	347550177	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	3246	0	0
T35	152930	0	0	0
T74	181469	0	0	0
T75	33027	0	0	0
T80	135789	0	0	0
T81	4445	0	0	0
T213	483247	0	0	0
T217	150671	0	0	0
T219	3558	1076	0	0
T225	0	677	0	0
T234	0	1004	0	0
T236	0	489	0	0
T245	21128	0	0	0
T246	38158	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	158558	0	0
T4	108988	0	0	0
T5	357276	2	0	0
T6	102487	42	0	0
T7	440509	656	0	0
T9	0	2	0	0
T16	0	1685	0	0
T20	30130	1	0	0
T24	0	141	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	5	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	274	0	0
T49	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	347550177	0	0
T1	24636	24549	0	0
T2	609924	96319	0	0
T3	28646	619	0	0
T4	108988	108978	0	0
T6	102487	3154	0	0
T25	5346	5252	0	0
T26	12646	12585	0	0
T27	16547	9187	0	0
T28	26193	26099	0	0
T29	9078	1677	0	0