Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T25
1	0	1	Covered	T3,T6,T4
1	1	0	Covered	T25,T27,T29
1	1	1	Covered	T25,T27,T29

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T25,T27,T29
0	1	Covered	T5,T16,T30
1	0	Covered	T5,T20,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T25,T27,T29
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T20,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T27,T29
1	0	Not Covered
1	1	Covered	T5,T16,T30

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T6,T26

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T25,T4,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T25
1	Covered	T2,T3,T25

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T6,T27,T28

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T6,T25

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T6,T25

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T6,T26

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T6
Phase1St	198	Covered	T2,T3,T6
Phase2St	215	Covered	T2,T3,T6
Phase3St	233	Covered	T2,T3,T6
TerminalSt	249	Covered	T2,T3,T6
TimeoutSt	159	Covered	T25,T27,T29

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T2,T3,T6
IdleSt->TimeoutSt	159	Covered	T25,T27,T29
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T11,T32,T33
Phase0St->Phase1St	198	Covered	T2,T3,T6
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T27,T5,T24
Phase1St->Phase2St	215	Covered	T2,T3,T6
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T7,T24,T19
Phase2St->Phase3St	233	Covered	T2,T3,T6
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T34,T35,T36
Phase3St->TerminalSt	249	Covered	T2,T3,T6
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T25,T26
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T25,T27,T29
TimeoutSt->Phase0St	172	Covered	T5,T20,T16

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T27,T29
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T20,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T25,T27,T29
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T25,T27,T29
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T11,T32,T36
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T5,T24
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T24,T19
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T35,T36
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T25,T26,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1050	0	0
CheckAccumTrig0_A	2147483647	2110	0	0
CheckAccumTrig1_A	2147483647	117	0	0
CheckClr_A	2147483647	993	0	0
CheckEn_A	2147483647	1063789410	0	0
CheckPhase0_A	2147483647	2399	0	0
CheckPhase1_A	2147483647	2359	0	0
CheckPhase2_A	2147483647	2315	0	0
CheckPhase3_A	2147483647	2276	0	0
CheckTimeout0_A	2147483647	8411	0	0
CheckTimeoutSt1_A	2147483647	688248	0	0
CheckTimeoutSt2_A	2147483647	8089	0	0
CheckTimeoutStTrig_A	2147483647	204	0	0
ErrorStAllEscAsserted_A	2147483647	5878	0	0
ErrorStIsTerminal_A	2147483647	4918	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1050	0	0
T13	1532432	252	0	0
T14	0	140	0	0
T15	0	255	0	0
T37	0	261	0	0
T38	0	142	0	0
T39	33728	0	0	0
T40	1936544	0	0	0
T41	77468	0	0	0
T42	518992	0	0	0
T43	65908	0	0	0
T44	1269832	0	0	0
T45	402324	0	0	0
T46	132848	0	0	0
T47	101432	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2110	0	0
T2	609924	2	0	0
T3	57292	1	0	0
T4	435952	2	0	0
T5	1429104	10	0	0
T6	409948	7	0	0
T7	881018	5	0	0
T8	0	1	0	0
T9	0	3	0	0
T11	0	2	0	0
T16	0	2	0	0
T17	0	2	0	0
T18	0	1	0	0
T20	90390	4	0	0
T24	0	1	0	0
T25	21384	2	0	0
T26	50584	3	0	0
T27	66188	5	0	0
T28	104772	1	0	0
T29	36312	0	0	0
T48	0	4	0	0
T49	0	2	0	0
T50	0	6	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117	0	0
T5	357276	1	0	0
T7	881018	0	0	0
T8	1228202	0	0	0
T9	617408	0	0	0
T13	383108	0	0	0
T16	284120	0	0	0
T20	60260	1	0	0
T21	10026	0	0	0
T22	8816	0	0	0
T23	66752	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	166931	0	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T43	0	1	0	0
T48	59006	0	0	0
T49	160338	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	37572	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	4	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	304601	0	0	0
T68	15515	0	0	0
T69	77963	0	0	0
T70	35884	0	0	0
T71	121306	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	993	0	0
T4	326964	0	0	0
T5	1429104	4	0	0
T6	102487	0	0	0
T7	1762036	0	0	0
T8	1228202	0	0	0
T9	308704	1	0	0
T16	284120	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	10	0	0
T20	120520	2	0	0
T21	15039	0	0	0
T22	4408	0	0	0
T23	33376	0	0	0
T24	0	6	0	0
T25	10692	1	0	0
T26	25292	2	0	0
T27	49641	2	0	0
T28	78579	0	0	0
T29	27234	0	0	0
T31	0	1	0	0
T34	0	6	0	0
T48	29503	3	0	0
T50	0	5	0	0
T51	0	3	0	0
T52	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	4	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1063789410	0	0
T1	98544	93202	0	0
T2	2439696	1320930	0	0
T3	114584	32563	0	0
T4	435952	219124	0	0
T6	409948	18468	0	0
T25	21384	15118	0	0
T26	50584	38688	0	0
T27	66188	39184	0	0
T28	104772	78876	0	0
T29	36312	22058	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2399	0	0
T2	609924	2	0	0
T3	57292	1	0	0
T4	435952	2	0	0
T5	1429104	15	0	0
T6	409948	7	0	0
T7	881018	5	0	0
T8	0	1	0	0
T9	0	3	0	0
T16	0	4	0	0
T20	90390	5	0	0
T24	0	1	0	0
T25	21384	2	0	0
T26	50584	3	0	0
T27	66188	5	0	0
T28	104772	1	0	0
T29	36312	0	0	0
T30	0	1	0	0
T48	0	4	0	0
T49	0	2	0	0
T50	0	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2359	0	0
T2	609924	2	0	0
T3	57292	1	0	0
T4	435952	2	0	0
T5	1429104	14	0	0
T6	409948	6	0	0
T7	881018	5	0	0
T8	0	1	0	0
T9	0	3	0	0
T16	0	4	0	0
T17	0	2	0	0
T20	90390	5	0	0
T24	0	1	0	0
T25	21384	2	0	0
T26	50584	3	0	0
T27	66188	4	0	0
T28	104772	1	0	0
T29	36312	0	0	0
T30	0	1	0	0
T48	0	4	0	0
T49	0	2	0	0
T50	0	5	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2315	0	0
T2	609924	2	0	0
T3	57292	1	0	0
T4	435952	2	0	0
T5	1429104	14	0	0
T6	409948	6	0	0
T7	881018	4	0	0
T8	0	1	0	0
T9	0	3	0	0
T16	0	4	0	0
T17	0	2	0	0
T20	90390	5	0	0
T24	0	1	0	0
T25	21384	2	0	0
T26	50584	3	0	0
T27	66188	4	0	0
T28	104772	1	0	0
T29	36312	0	0	0
T30	0	1	0	0
T48	0	4	0	0
T49	0	2	0	0
T50	0	5	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2276	0	0
T2	609924	2	0	0
T3	57292	1	0	0
T4	435952	2	0	0
T5	1429104	14	0	0
T6	409948	6	0	0
T7	881018	3	0	0
T8	0	1	0	0
T9	0	3	0	0
T16	0	4	0	0
T17	0	2	0	0
T20	90390	5	0	0
T24	0	1	0	0
T25	21384	2	0	0
T26	50584	3	0	0
T27	66188	4	0	0
T28	104772	1	0	0
T29	36312	0	0	0
T30	0	1	0	0
T48	0	4	0	0
T49	0	2	0	0
T50	0	5	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8411	0	0
T4	326964	0	0	0
T5	1429104	9	0	0
T7	1762036	0	0	0
T8	1842303	0	0	0
T9	617408	0	0	0
T16	426180	6	0	0
T17	0	1	0	0
T20	120520	2	0	0
T21	20052	0	0	0
T22	8816	0	0	0
T23	33376	0	0	0
T24	0	534	0	0
T25	5346	1	0	0
T26	12646	0	0	0
T27	33094	1	0	0
T28	52386	0	0	0
T29	27234	4	0	0
T30	0	2	0	0
T31	0	1	0	0
T34	0	7	0	0
T48	29503	0	0	0
T51	0	2	0	0
T52	0	3	0	0
T73	0	37	0	0
T74	0	19	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	10	0	0
T79	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	688248	0	0
T4	326964	0	0	0
T5	1429104	1120	0	0
T7	1762036	0	0	0
T8	1842303	0	0	0
T9	617408	0	0	0
T16	426180	128	0	0
T17	0	268	0	0
T20	120520	65	0	0
T21	20052	0	0	0
T22	8816	0	0	0
T23	33376	0	0	0
T24	0	26804	0	0
T25	5346	56	0	0
T26	12646	0	0	0
T27	33094	47	0	0
T28	52386	0	0	0
T29	27234	327	0	0
T30	0	235	0	0
T31	0	1	0	0
T34	0	513	0	0
T48	29503	0	0	0
T51	0	166	0	0
T52	0	107	0	0
T73	0	2147	0	0
T74	0	3882	0	0
T76	0	22	0	0
T77	0	44	0	0
T78	0	1607	0	0
T79	0	1047	0	0
T80	0	406	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8089	0	0
T4	326964	0	0	0
T5	1429104	4	0	0
T7	1762036	0	0	0
T8	1842303	0	0	0
T9	617408	0	0	0
T16	426180	4	0	0
T17	0	1	0	0
T20	120520	1	0	0
T21	20052	0	0	0
T22	8816	0	0	0
T23	33376	0	0	0
T24	0	534	0	0
T25	5346	1	0	0
T26	12646	0	0	0
T27	33094	1	0	0
T28	52386	0	0	0
T29	27234	4	0	0
T30	0	1	0	0
T32	0	2	0	0
T35	0	2	0	0
T48	29503	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T73	0	36	0	0
T74	0	15	0	0
T75	0	2	0	0
T76	0	1	0	0
T78	0	16	0	0
T79	0	11	0	0
T80	0	58	0	0
T81	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	204	0	0
T5	1071828	4	0	0
T7	1321527	0	0	0
T8	1842303	0	0	0
T9	926112	0	0	0
T16	426180	1	0	0
T20	90390	0	0	0
T21	15039	0	0	0
T22	13224	0	0	0
T23	100128	0	0	0
T30	0	1	0	0
T32	0	5	0	0
T34	106289	2	0	0
T36	0	5	0	0
T40	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	88509	0	0	0
T52	253482	1	0	0
T58	0	2	0	0
T73	0	1	0	0
T74	0	4	0	0
T78	92018	0	0	0
T82	0	3	0	0
T83	0	2	0	0
T84	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	6	0	0
T88	0	3	0	0
T89	0	1	0	0
T90	556845	0	0	0
T91	114025	0	0	0
T92	783654	0	0	0
T93	235496	0	0	0
T94	165112	0	0	0
T95	111650	0	0	0
T96	379559	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5878	0	0
T13	1532432	1505	0	0
T14	0	756	0	0
T15	0	1420	0	0
T37	0	1446	0	0
T38	0	751	0	0
T39	33728	0	0	0
T40	1936544	0	0	0
T41	77468	0	0	0
T42	518992	0	0	0
T43	65908	0	0	0
T44	1269832	0	0	0
T45	402324	0	0	0
T46	132848	0	0	0
T47	101432	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4918	0	0
T13	1532432	1265	0	0
T14	0	636	0	0
T15	0	1180	0	0
T37	0	1206	0	0
T38	0	631	0	0
T39	33728	0	0	0
T40	1936544	0	0	0
T41	77468	0	0	0
T42	518992	0	0	0
T43	65908	0	0	0
T44	1269832	0	0	0
T45	402324	0	0	0
T46	132848	0	0	0
T47	101432	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	98544	98196	0	0
T2	2439696	2438660	0	0
T3	114584	114368	0	0
T4	435952	435912	0	0
T6	409948	409548	0	0
T25	21384	21008	0	0
T26	50584	50340	0	0
T27	66188	65924	0	0
T28	104772	104396	0	0
T29	36312	35976	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	98544	98196	0	0
T2	2439696	2438660	0	0
T3	114584	114368	0	0
T4	435952	435912	0	0
T6	409948	409548	0	0
T25	21384	21008	0	0
T26	50584	50340	0	0
T27	66188	65924	0	0
T28	104772	104396	0	0
T29	36312	35976	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T6,T25
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T25

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T6,T25

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T25,T26
1	0	1	Covered	T3,T6,T4
1	1	0	Covered	T25,T27,T29
1	1	1	Covered	T29,T5,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T5,T20
0	1	Covered	T34,T82,T32
1	0	Covered	T20,T31,T43

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T29,T5,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T31,T43

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T5,T20
1	0	Not Covered
1	1	Covered	T34,T82,T32

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T25
1	Covered	T2,T26,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T25
1	Covered	T4,T5,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T26
1	Covered	T2,T25,T27

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T25,T26
1	Covered	T6,T27,T28

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T6,T25

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T25,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T6,T25,T27

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T6,T26

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T6,T25
Phase1St	198	Covered	T2,T6,T25
Phase2St	215	Covered	T2,T6,T25
Phase3St	233	Covered	T2,T6,T25
TerminalSt	249	Covered	T2,T6,T25
TimeoutSt	159	Covered	T29,T5,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T2,T6,T25
IdleSt->TimeoutSt	159	Covered	T29,T5,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T32,T33,T97
Phase0St->Phase1St	198	Covered	T2,T6,T25
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T24,T97,T98
Phase1St->Phase2St	215	Covered	T2,T6,T25
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T24,T51,T74
Phase2St->Phase3St	233	Covered	T2,T6,T25
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T34,T35,T87
Phase3St->TerminalSt	249	Covered	T2,T6,T25
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T25,T26
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T29,T5,T20
TimeoutSt->Phase0St	172	Covered	T20,T31,T34

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T25
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T5,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T31,T34
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T29,T5,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T29,T5,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T99,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T6,T25
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T6,T25
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T98,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T6,T25
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T6,T25
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T51,T74
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T6,T25
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T6,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T35,T87
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T6,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T6,T25
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T25,T26,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T6,T25
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	614671084	263	0	0
CheckAccumTrig0_A	614671084	776	0	0
CheckAccumTrig1_A	614671084	49	0	0
CheckClr_A	614671084	391	0	0
CheckEn_A	614069008	225835987	0	0
CheckPhase0_A	614671084	873	0	0
CheckPhase1_A	614671084	859	0	0
CheckPhase2_A	614671084	842	0	0
CheckPhase3_A	614671084	825	0	0
CheckTimeout0_A	614671084	2453	0	0
CheckTimeoutSt1_A	614671084	206976	0	0
CheckTimeoutSt2_A	614671084	2344	0	0
CheckTimeoutStTrig_A	614671084	60	0	0
ErrorStAllEscAsserted_A	614671084	1456	0	0
ErrorStIsTerminal_A	614671084	1216	0	0
EscStateOut_A	614067008	613998612	0	0
u_state_regs_A	614671084	614501076	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	263	0	0
T13	383108	54	0	0
T14	0	23	0	0
T15	0	83	0	0
T37	0	74	0	0
T38	0	29	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T41	19367	0	0	0
T42	129748	0	0	0
T43	16477	0	0	0
T44	317458	0	0	0
T45	100581	0	0	0
T46	33212	0	0	0
T47	25358	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	776	0	0
T2	609924	2	0	0
T3	28646	0	0	0
T4	108988	1	0	0
T5	357276	4	0	0
T6	102487	1	0	0
T7	0	1	0	0
T20	0	1	0	0
T25	5346	1	0	0
T26	12646	3	0	0
T27	16547	2	0	0
T28	26193	1	0	0
T29	9078	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	49	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	0	0	0
T20	30130	1	0	0
T21	5013	0	0	0
T22	4408	0	0	0
T23	33376	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T48	29503	0	0	0
T49	160338	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	4	0	0
T60	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	391	0	0
T4	108988	0	0	0
T5	357276	0	0	0
T7	440509	0	0	0
T19	0	3	0	0
T20	30130	1	0	0
T21	5013	0	0	0
T24	0	6	0	0
T25	5346	1	0	0
T26	12646	2	0	0
T27	16547	1	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T31	0	1	0	0
T34	0	6	0	0
T48	0	2	0	0
T51	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614069008	225835987	0	0
T1	24636	24548	0	0
T2	609924	9707	0	0
T3	28646	607	0	0
T4	108988	582	0	0
T6	102487	3071	0	0
T25	5346	2574	0	0
T26	12646	936	0	0
T27	16547	4325	0	0
T28	26193	582	0	0
T29	9078	5233	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	873	0	0
T2	609924	2	0	0
T3	28646	0	0	0
T4	108988	1	0	0
T5	357276	4	0	0
T6	102487	1	0	0
T7	0	1	0	0
T20	0	2	0	0
T25	5346	1	0	0
T26	12646	3	0	0
T27	16547	2	0	0
T28	26193	1	0	0
T29	9078	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	859	0	0
T2	609924	2	0	0
T3	28646	0	0	0
T4	108988	1	0	0
T5	357276	4	0	0
T6	102487	1	0	0
T7	0	1	0	0
T20	0	2	0	0
T25	5346	1	0	0
T26	12646	3	0	0
T27	16547	2	0	0
T28	26193	1	0	0
T29	9078	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	842	0	0
T2	609924	2	0	0
T3	28646	0	0	0
T4	108988	1	0	0
T5	357276	4	0	0
T6	102487	1	0	0
T7	0	1	0	0
T20	0	2	0	0
T25	5346	1	0	0
T26	12646	3	0	0
T27	16547	2	0	0
T28	26193	1	0	0
T29	9078	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	825	0	0
T2	609924	2	0	0
T3	28646	0	0	0
T4	108988	1	0	0
T5	357276	4	0	0
T6	102487	1	0	0
T7	0	1	0	0
T20	0	2	0	0
T25	5346	1	0	0
T26	12646	3	0	0
T27	16547	2	0	0
T28	26193	1	0	0
T29	9078	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	2453	0	0
T4	108988	0	0	0
T5	357276	1	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	2	0	0
T20	30130	2	0	0
T21	5013	0	0	0
T22	4408	0	0	0
T29	9078	1	0	0
T31	0	1	0	0
T34	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T73	0	6	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	206976	0	0
T4	108988	0	0	0
T5	357276	183	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	30	0	0
T20	30130	65	0	0
T21	5013	0	0	0
T22	4408	0	0	0
T29	9078	97	0	0
T31	0	1	0	0
T34	0	75	0	0
T51	0	163	0	0
T52	0	90	0	0
T73	0	358	0	0
T76	0	22	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	2344	0	0
T4	108988	0	0	0
T5	357276	1	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	2	0	0
T20	30130	1	0	0
T21	5013	0	0	0
T22	4408	0	0	0
T29	9078	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T73	0	6	0	0
T76	0	1	0	0
T78	0	6	0	0
T79	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	60	0	0
T32	0	3	0	0
T34	106289	2	0	0
T36	0	1	0	0
T45	0	1	0	0
T52	253482	0	0	0
T78	92018	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T87	0	4	0	0
T88	0	2	0	0
T89	0	1	0	0
T90	556845	0	0	0
T91	114025	0	0	0
T92	783654	0	0	0
T93	235496	0	0	0
T94	165112	0	0	0
T95	111650	0	0	0
T96	379559	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	1456	0	0
T13	383108	373	0	0
T14	0	185	0	0
T15	0	355	0	0
T37	0	359	0	0
T38	0	184	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T41	19367	0	0	0
T42	129748	0	0	0
T43	16477	0	0	0
T44	317458	0	0	0
T45	100581	0	0	0
T46	33212	0	0	0
T47	25358	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	1216	0	0
T13	383108	313	0	0
T14	0	155	0	0
T15	0	295	0	0
T37	0	299	0	0
T38	0	154	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T41	19367	0	0	0
T42	129748	0	0	0
T43	16477	0	0	0
T44	317458	0	0	0
T45	100581	0	0	0
T46	33212	0	0	0
T47	25358	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614067008	613998612	0	0
T1	24636	24549	0	0
T2	609924	609665	0	0
T3	28646	28592	0	0
T4	108988	108978	0	0
T6	102487	102387	0	0
T25	5346	5252	0	0
T26	12646	12585	0	0
T27	16547	16481	0	0
T28	26193	26099	0	0
T29	9078	8994	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	614501076	0	0
T1	24636	24549	0	0
T2	609924	609665	0	0
T3	28646	28592	0	0
T4	108988	108978	0	0
T6	102487	102387	0	0
T25	5346	5252	0	0
T26	12646	12585	0	0
T27	16547	16481	0	0
T28	26193	26099	0	0
T29	9078	8994	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T6,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T6,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T29,T5
1	0	1	Covered	T3,T9,T49
1	1	0	Covered	T27,T29,T5
1	1	1	Covered	T5,T16,T30

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T16,T30
0	1	Covered	T5,T30,T73
1	0	Covered	T5,T51,T52

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T16,T30
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T51,T52

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T16,T30
1	0	Not Covered
1	1	Covered	T5,T30,T73

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T6,T5,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T4
1	Covered	T8,T17,T24

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T4,T5
1	Covered	T3,T30,T50

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T5
1	Covered	T4,T5,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T6,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T6,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T6,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T6,T4
Phase1St	198	Covered	T3,T6,T4
Phase2St	215	Covered	T3,T6,T4
Phase3St	233	Covered	T3,T6,T4
TerminalSt	249	Covered	T3,T6,T4
TimeoutSt	159	Covered	T5,T16,T30

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T3,T6,T4
IdleSt->TimeoutSt	159	Covered	T5,T16,T30
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T102,T103,T104
Phase0St->Phase1St	198	Covered	T3,T6,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T5,T52,T105
Phase1St->Phase2St	215	Covered	T3,T6,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T19,T106,T107
Phase2St->Phase3St	233	Covered	T3,T6,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T36,T106,T108
Phase3St->TerminalSt	249	Covered	T3,T6,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T5,T20,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T16,T17
TimeoutSt->Phase0St	172	Covered	T5,T30,T73

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T16,T30
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T30,T73
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T16,T30
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T16,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T102,T103,T104
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T6,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T6,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T52,T105
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T6,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T6,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T106,T107
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T6,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T6,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T36,T106,T108
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T6,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T6,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T20,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T6,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	614671084	243	0	0
CheckAccumTrig0_A	614671084	449	0	0
CheckAccumTrig1_A	614671084	17	0	0
CheckClr_A	614671084	176	0	0
CheckEn_A	614069008	280969517	0	0
CheckPhase0_A	614671084	502	0	0
CheckPhase1_A	614671084	496	0	0
CheckPhase2_A	614671084	489	0	0
CheckPhase3_A	614671084	481	0	0
CheckTimeout0_A	614671084	1851	0	0
CheckTimeoutSt1_A	614671084	148424	0	0
CheckTimeoutSt2_A	614671084	1794	0	0
CheckTimeoutStTrig_A	614671084	40	0	0
ErrorStAllEscAsserted_A	614671084	1463	0	0
ErrorStIsTerminal_A	614671084	1223	0	0
EscStateOut_A	614067008	613998612	0	0
u_state_regs_A	614671084	614501076	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	243	0	0
T13	383108	54	0	0
T14	0	35	0	0
T15	0	50	0	0
T37	0	65	0	0
T38	0	39	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T41	19367	0	0	0
T42	129748	0	0	0
T43	16477	0	0	0
T44	317458	0	0	0
T45	100581	0	0	0
T46	33212	0	0	0
T47	25358	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	449	0	0
T3	28646	1	0	0
T4	108988	1	0	0
T5	357276	2	0	0
T6	102487	1	0	0
T8	0	1	0	0
T16	0	2	0	0
T20	30130	1	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	0	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	17	0	0
T5	357276	1	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	0	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T22	4408	0	0	0
T23	33376	0	0	0
T32	0	1	0	0
T48	29503	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T61	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	176	0	0
T5	357276	2	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	1	0	0
T18	0	1	0	0
T19	0	7	0	0
T20	30130	1	0	0
T21	5013	0	0	0
T22	4408	0	0	0
T23	33376	0	0	0
T48	29503	0	0	0
T51	0	1	0	0
T52	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614069008	280969517	0	0
T1	24636	19558	0	0
T2	609924	605242	0	0
T3	28646	3813	0	0
T4	108988	586	0	0
T6	102487	3098	0	0
T25	5346	5251	0	0
T26	12646	12584	0	0
T27	16547	16480	0	0
T28	26193	26098	0	0
T29	9078	6155	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	502	0	0
T3	28646	1	0	0
T4	108988	1	0	0
T5	357276	4	0	0
T6	102487	1	0	0
T8	0	1	0	0
T16	0	2	0	0
T20	30130	1	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	0	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T30	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	496	0	0
T3	28646	1	0	0
T4	108988	1	0	0
T5	357276	3	0	0
T6	102487	1	0	0
T8	0	1	0	0
T16	0	2	0	0
T20	30130	1	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	0	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T30	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	489	0	0
T3	28646	1	0	0
T4	108988	1	0	0
T5	357276	3	0	0
T6	102487	1	0	0
T8	0	1	0	0
T16	0	2	0	0
T20	30130	1	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	0	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T30	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	481	0	0
T3	28646	1	0	0
T4	108988	1	0	0
T5	357276	3	0	0
T6	102487	1	0	0
T8	0	1	0	0
T16	0	2	0	0
T20	30130	1	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	0	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T30	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	1851	0	0
T5	357276	3	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	2	0	0
T17	0	1	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T22	4408	0	0	0
T23	33376	0	0	0
T24	0	258	0	0
T30	0	1	0	0
T48	29503	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T73	0	12	0	0
T74	0	13	0	0
T79	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	148424	0	0
T5	357276	291	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	87	0	0
T17	0	268	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T22	4408	0	0	0
T23	33376	0	0	0
T24	0	12889	0	0
T30	0	86	0	0
T48	29503	0	0	0
T51	0	3	0	0
T52	0	1	0	0
T73	0	690	0	0
T74	0	2926	0	0
T79	0	283	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	1794	0	0
T5	357276	1	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	2	0	0
T17	0	1	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T22	4408	0	0	0
T23	33376	0	0	0
T24	0	258	0	0
T32	0	2	0	0
T48	29503	0	0	0
T73	0	11	0	0
T74	0	12	0	0
T75	0	2	0	0
T79	0	2	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	40	0	0
T5	357276	1	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	0	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T22	4408	0	0	0
T23	33376	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T36	0	4	0	0
T40	0	1	0	0
T48	29503	0	0	0
T58	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T83	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	1463	0	0
T13	383108	388	0	0
T14	0	177	0	0
T15	0	350	0	0
T37	0	349	0	0
T38	0	199	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T41	19367	0	0	0
T42	129748	0	0	0
T43	16477	0	0	0
T44	317458	0	0	0
T45	100581	0	0	0
T46	33212	0	0	0
T47	25358	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	1223	0	0
T13	383108	328	0	0
T14	0	147	0	0
T15	0	290	0	0
T37	0	289	0	0
T38	0	169	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T41	19367	0	0	0
T42	129748	0	0	0
T43	16477	0	0	0
T44	317458	0	0	0
T45	100581	0	0	0
T46	33212	0	0	0
T47	25358	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614067008	613998612	0	0
T1	24636	24549	0	0
T2	609924	609665	0	0
T3	28646	28592	0	0
T4	108988	108978	0	0
T6	102487	102387	0	0
T25	5346	5252	0	0
T26	12646	12585	0	0
T27	16547	16481	0	0
T28	26193	26099	0	0
T29	9078	8994	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	614501076	0	0
T1	24636	24549	0	0
T2	609924	609665	0	0
T3	28646	28592	0	0
T4	108988	108978	0	0
T6	102487	102387	0	0
T25	5346	5252	0	0
T26	12646	12585	0	0
T27	16547	16481	0	0
T28	26193	26099	0	0
T29	9078	8994	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T6,T25,T27
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T25,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T25,T27

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T25,T27

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T25,T27,T5
1	0	1	Covered	T3,T7,T48
1	1	0	Covered	T25,T27,T29
1	1	1	Covered	T25,T5,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T25,T5,T16
0	1	Covered	T5,T16,T52
1	0	Covered	T53,T36,T109

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T25,T5,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T53,T36,T109

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T5,T16
1	0	Not Covered
1	1	Covered	T5,T16,T52

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T25,T27,T5
1	Covered	T6,T17,T110

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T27,T5
1	Covered	T25,T9,T48

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T25,T5
1	Covered	T5,T16,T48

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T25,T5
1	Covered	T5,T20,T7

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T6,T27,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T25,T27,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T27,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T5,T16,T48

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T6,T25,T27
Phase1St	198	Covered	T6,T25,T27
Phase2St	215	Covered	T6,T25,T5
Phase3St	233	Covered	T6,T25,T5
TerminalSt	249	Covered	T6,T25,T5
TimeoutSt	159	Covered	T25,T5,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T6,T25,T27
IdleSt->TimeoutSt	159	Covered	T25,T5,T16
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T36,T98,T102
Phase0St->Phase1St	198	Covered	T6,T25,T27
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T27,T111,T98
Phase1St->Phase2St	215	Covered	T6,T25,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T112,T113,T98
Phase2St->Phase3St	233	Covered	T6,T25,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T111,T114,T115
Phase3St->TerminalSt	249	Covered	T6,T25,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T5,T9,T48
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T25,T30,T24
TimeoutSt->Phase0St	172	Covered	T5,T16,T52

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T25,T27
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T5,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T16,T52
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T25,T5,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T25,T30,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T36,T98,T102
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T6,T25,T27
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T6,T25,T27
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T111,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T6,T25,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T6,T25,T27
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T112,T113,T98
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T6,T25,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T25,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T111,T114,T115
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T6,T25,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T25,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T9,T48
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T25,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	614671084	249	0	0
CheckAccumTrig0_A	614671084	432	0	0
CheckAccumTrig1_A	614671084	24	0	0
CheckClr_A	614671084	205	0	0
CheckEn_A	614069008	269838077	0	0
CheckPhase0_A	614671084	511	0	0
CheckPhase1_A	614671084	499	0	0
CheckPhase2_A	614671084	493	0	0
CheckPhase3_A	614671084	487	0	0
CheckTimeout0_A	614671084	2223	0	0
CheckTimeoutSt1_A	614671084	183411	0	0
CheckTimeoutSt2_A	614671084	2136	0	0
CheckTimeoutStTrig_A	614671084	63	0	0
ErrorStAllEscAsserted_A	614671084	1490	0	0
ErrorStIsTerminal_A	614671084	1250	0	0
EscStateOut_A	614067008	613998612	0	0
u_state_regs_A	614671084	614501076	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	249	0	0
T13	383108	53	0	0
T14	0	51	0	0
T15	0	60	0	0
T37	0	41	0	0
T38	0	44	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T41	19367	0	0	0
T42	129748	0	0	0
T43	16477	0	0	0
T44	317458	0	0	0
T45	100581	0	0	0
T46	33212	0	0	0
T47	25358	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	432	0	0
T4	108988	0	0	0
T5	357276	4	0	0
T6	102487	1	0	0
T7	440509	1	0	0
T9	0	2	0	0
T17	0	2	0	0
T20	30130	1	0	0
T25	5346	1	0	0
T26	12646	0	0	0
T27	16547	1	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	2	0	0
T50	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	24	0	0
T13	383108	0	0	0
T33	166931	0	0	0
T36	0	1	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T53	37572	1	0	0
T67	304601	0	0	0
T68	15515	0	0	0
T69	77963	0	0	0
T70	35884	0	0	0
T71	121306	0	0	0
T101	0	1	0	0
T109	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	2	0	0
T121	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	205	0	0
T4	108988	0	0	0
T5	357276	2	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	0	1	0	0
T16	142060	0	0	0
T17	0	1	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T27	16547	1	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	1	0	0
T50	0	5	0	0
T72	0	1	0	0
T74	0	3	0	0
T80	0	1	0	0
T110	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614069008	269838077	0	0
T1	24636	24548	0	0
T2	609924	609663	0	0
T3	28646	27524	0	0
T4	108988	108978	0	0
T6	102487	9145	0	0
T25	5346	2042	0	0
T26	12646	12584	0	0
T27	16547	15216	0	0
T28	26193	26098	0	0
T29	9078	8993	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	511	0	0
T4	108988	0	0	0
T5	357276	5	0	0
T6	102487	1	0	0
T7	440509	1	0	0
T9	0	2	0	0
T16	0	1	0	0
T20	30130	1	0	0
T25	5346	1	0	0
T26	12646	0	0	0
T27	16547	1	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	2	0	0
T50	0	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	499	0	0
T4	108988	0	0	0
T5	357276	5	0	0
T6	102487	1	0	0
T7	440509	1	0	0
T9	0	2	0	0
T16	0	1	0	0
T17	0	2	0	0
T20	30130	1	0	0
T25	5346	1	0	0
T26	12646	0	0	0
T27	16547	0	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	2	0	0
T50	0	5	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	493	0	0
T4	108988	0	0	0
T5	357276	5	0	0
T6	102487	1	0	0
T7	440509	1	0	0
T9	0	2	0	0
T16	0	1	0	0
T17	0	2	0	0
T20	30130	1	0	0
T25	5346	1	0	0
T26	12646	0	0	0
T27	16547	0	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	2	0	0
T50	0	5	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	487	0	0
T4	108988	0	0	0
T5	357276	5	0	0
T6	102487	1	0	0
T7	440509	1	0	0
T9	0	2	0	0
T16	0	1	0	0
T17	0	2	0	0
T20	30130	1	0	0
T25	5346	1	0	0
T26	12646	0	0	0
T27	16547	0	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	2	0	0
T50	0	5	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	2223	0	0
T4	108988	0	0	0
T5	357276	1	0	0
T7	440509	0	0	0
T16	0	1	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T24	0	275	0	0
T25	5346	1	0	0
T26	12646	0	0	0
T27	16547	0	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T30	0	1	0	0
T52	0	1	0	0
T73	0	11	0	0
T74	0	3	0	0
T78	0	6	0	0
T79	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	183411	0	0
T4	108988	0	0	0
T5	357276	87	0	0
T7	440509	0	0	0
T16	0	11	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T24	0	13780	0	0
T25	5346	56	0	0
T26	12646	0	0	0
T27	16547	0	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T30	0	149	0	0
T52	0	16	0	0
T73	0	623	0	0
T74	0	625	0	0
T78	0	984	0	0
T79	0	764	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	2136	0	0
T4	108988	0	0	0
T5	357276	0	0	0
T7	440509	0	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T24	0	275	0	0
T25	5346	1	0	0
T26	12646	0	0	0
T27	16547	0	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T30	0	1	0	0
T35	0	2	0	0
T73	0	11	0	0
T74	0	2	0	0
T78	0	6	0	0
T79	0	5	0	0
T80	0	53	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	63	0	0
T5	357276	1	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	1	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T22	4408	0	0	0
T23	33376	0	0	0
T32	0	1	0	0
T47	0	1	0	0
T48	29503	0	0	0
T52	0	1	0	0
T74	0	1	0	0
T82	0	1	0	0
T84	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	1490	0	0
T13	383108	360	0	0
T14	0	197	0	0
T15	0	362	0	0
T37	0	360	0	0
T38	0	211	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T41	19367	0	0	0
T42	129748	0	0	0
T43	16477	0	0	0
T44	317458	0	0	0
T45	100581	0	0	0
T46	33212	0	0	0
T47	25358	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	1250	0	0
T13	383108	300	0	0
T14	0	167	0	0
T15	0	302	0	0
T37	0	300	0	0
T38	0	181	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T41	19367	0	0	0
T42	129748	0	0	0
T43	16477	0	0	0
T44	317458	0	0	0
T45	100581	0	0	0
T46	33212	0	0	0
T47	25358	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614067008	613998612	0	0
T1	24636	24549	0	0
T2	609924	609665	0	0
T3	28646	28592	0	0
T4	108988	108978	0	0
T6	102487	102387	0	0
T25	5346	5252	0	0
T26	12646	12585	0	0
T27	16547	16481	0	0
T28	26193	26099	0	0
T29	9078	8994	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	614501076	0	0
T1	24636	24549	0	0
T2	609924	609665	0	0
T3	28646	28592	0	0
T4	108988	108978	0	0
T6	102487	102387	0	0
T25	5346	5252	0	0
T26	12646	12585	0	0
T27	16547	16481	0	0
T28	26193	26099	0	0
T29	9078	8994	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T6,T27,T29
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T27,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T27,T29

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T27,T20

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T29,T5
1	0	1	Covered	T3,T6,T48
1	1	0	Covered	T25,T5,T30
1	1	1	Covered	T27,T29,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T27,T29,T5
0	1	Covered	T5,T74,T40
1	0	Covered	T16,T34,T80

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T27,T29,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T34,T80

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T29,T5
1	0	Not Covered
1	1	Covered	T5,T74,T40

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T27,T5
1	Covered	T5,T48,T49

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T5,T7
1	Covered	T27,T20,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T27,T5
1	Covered	T9,T72,T90

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T27,T5,T20
1	Covered	T6,T5,T7

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T5,T20,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T27,T5,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T27,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T6,T27,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T6,T27,T5
Phase1St	198	Covered	T6,T27,T5
Phase2St	215	Covered	T6,T27,T5
Phase3St	233	Covered	T6,T27,T5
TerminalSt	249	Covered	T6,T27,T5
TimeoutSt	159	Covered	T27,T29,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T6,T27,T20
IdleSt->TimeoutSt	159	Covered	T27,T29,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T11,T60,T62
Phase0St->Phase1St	198	Covered	T6,T27,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T122,T123
Phase1St->Phase2St	215	Covered	T6,T27,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T7,T80,T124
Phase2St->Phase3St	233	Covered	T6,T27,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T7,T125,T97
Phase3St->TerminalSt	249	Covered	T6,T27,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T6,T27,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T27,T29,T5
TimeoutSt->Phase0St	172	Covered	T5,T16,T34

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T27,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T29,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T16,T34
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T27,T29,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T27,T29,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T11,T126,T127
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T6,T27,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T6,T27,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T122,T123
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T6,T27,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T6,T27,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T80,T124
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T6,T27,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T27,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T7,T125,T97
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T6,T27,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T27,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T27,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T27,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	614671084	295	0	0
CheckAccumTrig0_A	614671084	453	0	0
CheckAccumTrig1_A	614671084	27	0	0
CheckClr_A	614671084	221	0	0
CheckEn_A	614069008	287145829	0	0
CheckPhase0_A	614671084	513	0	0
CheckPhase1_A	614671084	505	0	0
CheckPhase2_A	614671084	491	0	0
CheckPhase3_A	614671084	483	0	0
CheckTimeout0_A	614671084	1884	0	0
CheckTimeoutSt1_A	614671084	149437	0	0
CheckTimeoutSt2_A	614671084	1815	0	0
CheckTimeoutStTrig_A	614671084	41	0	0
ErrorStAllEscAsserted_A	614671084	1469	0	0
ErrorStIsTerminal_A	614671084	1229	0	0
EscStateOut_A	614067008	613998612	0	0
u_state_regs_A	614671084	614501076	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	295	0	0
T13	383108	91	0	0
T14	0	31	0	0
T15	0	62	0	0
T37	0	81	0	0
T38	0	30	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T41	19367	0	0	0
T42	129748	0	0	0
T43	16477	0	0	0
T44	317458	0	0	0
T45	100581	0	0	0
T46	33212	0	0	0
T47	25358	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	453	0	0
T4	108988	0	0	0
T5	357276	0	0	0
T6	102487	4	0	0
T7	440509	3	0	0
T9	0	1	0	0
T11	0	2	0	0
T18	0	1	0	0
T20	30130	1	0	0
T24	0	1	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	2	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	27	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	1	0	0
T22	4408	0	0	0
T23	33376	0	0	0
T30	12553	0	0	0
T34	0	2	0	0
T48	29503	0	0	0
T49	160338	0	0	0
T54	0	1	0	0
T60	0	1	0	0
T80	0	1	0	0
T100	0	1	0	0
T102	0	1	0	0
T115	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	46899	0	0	0
T131	10319	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	221	0	0
T4	108988	0	0	0
T5	357276	1	0	0
T6	102487	3	0	0
T7	440509	2	0	0
T11	0	1	0	0
T20	30130	0	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	1	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T34	0	2	0	0
T48	0	1	0	0
T72	0	2	0	0
T74	0	1	0	0
T110	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614069008	287145829	0	0
T1	24636	24548	0	0
T2	609924	96318	0	0
T3	28646	619	0	0
T4	108988	108978	0	0
T6	102487	3154	0	0
T25	5346	5251	0	0
T26	12646	12584	0	0
T27	16547	3163	0	0
T28	26193	26098	0	0
T29	9078	1677	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	513	0	0
T4	108988	0	0	0
T5	357276	2	0	0
T6	102487	4	0	0
T7	440509	3	0	0
T9	0	1	0	0
T16	0	1	0	0
T20	30130	1	0	0
T24	0	1	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	2	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	505	0	0
T4	108988	0	0	0
T5	357276	2	0	0
T6	102487	3	0	0
T7	440509	3	0	0
T9	0	1	0	0
T16	0	1	0	0
T20	30130	1	0	0
T24	0	1	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	2	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	491	0	0
T4	108988	0	0	0
T5	357276	2	0	0
T6	102487	3	0	0
T7	440509	2	0	0
T9	0	1	0	0
T16	0	1	0	0
T20	30130	1	0	0
T24	0	1	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	2	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	483	0	0
T4	108988	0	0	0
T5	357276	2	0	0
T6	102487	3	0	0
T7	440509	1	0	0
T9	0	1	0	0
T16	0	1	0	0
T20	30130	1	0	0
T24	0	1	0	0
T25	5346	0	0	0
T26	12646	0	0	0
T27	16547	2	0	0
T28	26193	0	0	0
T29	9078	0	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	1884	0	0
T4	108988	0	0	0
T5	357276	4	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T16	142060	1	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T24	0	1	0	0
T27	16547	1	0	0
T28	26193	0	0	0
T29	9078	3	0	0
T34	0	5	0	0
T73	0	8	0	0
T74	0	3	0	0
T77	0	1	0	0
T78	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	149437	0	0
T4	108988	0	0	0
T5	357276	559	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T16	142060	0	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T24	0	135	0	0
T27	16547	47	0	0
T28	26193	0	0	0
T29	9078	230	0	0
T34	0	438	0	0
T73	0	476	0	0
T74	0	331	0	0
T77	0	44	0	0
T78	0	623	0	0
T80	0	406	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	1815	0	0
T4	108988	0	0	0
T5	357276	2	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T16	142060	0	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T24	0	1	0	0
T27	16547	1	0	0
T28	26193	0	0	0
T29	9078	3	0	0
T34	0	3	0	0
T73	0	8	0	0
T74	0	1	0	0
T77	0	1	0	0
T78	0	4	0	0
T80	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	41	0	0
T5	357276	2	0	0
T7	440509	0	0	0
T8	614101	0	0	0
T9	308704	0	0	0
T16	142060	0	0	0
T20	30130	0	0	0
T21	5013	0	0	0
T22	4408	0	0	0
T23	33376	0	0	0
T40	0	1	0	0
T48	29503	0	0	0
T54	0	1	0	0
T58	0	1	0	0
T62	0	1	0	0
T74	0	2	0	0
T85	0	1	0	0
T87	0	1	0	0
T114	0	2	0	0
T132	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	1469	0	0
T13	383108	384	0	0
T14	0	197	0	0
T15	0	353	0	0
T37	0	378	0	0
T38	0	157	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T41	19367	0	0	0
T42	129748	0	0	0
T43	16477	0	0	0
T44	317458	0	0	0
T45	100581	0	0	0
T46	33212	0	0	0
T47	25358	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	1229	0	0
T13	383108	324	0	0
T14	0	167	0	0
T15	0	293	0	0
T37	0	318	0	0
T38	0	127	0	0
T39	8432	0	0	0
T40	484136	0	0	0
T41	19367	0	0	0
T42	129748	0	0	0
T43	16477	0	0	0
T44	317458	0	0	0
T45	100581	0	0	0
T46	33212	0	0	0
T47	25358	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614067008	613998612	0	0
T1	24636	24549	0	0
T2	609924	609665	0	0
T3	28646	28592	0	0
T4	108988	108978	0	0
T6	102487	102387	0	0
T25	5346	5252	0	0
T26	12646	12585	0	0
T27	16547	16481	0	0
T28	26193	26099	0	0
T29	9078	8994	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614671084	614501076	0	0
T1	24636	24549	0	0
T2	609924	609665	0	0
T3	28646	28592	0	0
T4	108988	108978	0	0
T6	102487	102387	0	0
T25	5346	5252	0	0
T26	12646	12585	0	0
T27	16547	16481	0	0
T28	26193	26099	0	0
T29	9078	8994	0	0