Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T34,T41
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	17733	0	0
DisabledNoTrigBkwd_A	2147483647	892314	0	0
DisabledNoTrigFwd_A	2147483647	1506548758	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17733	0	0
T3	2648	369	0	0
T4	246283	0	0	0
T5	110591	0	0	0
T6	13377	0	0	0
T7	149782	0	0	0
T8	371368	0	0	0
T11	20921	0	0	0
T17	26026	0	0	0
T18	48540	0	0	0
T26	601161	0	0	0
T34	9950	1284	0	0
T35	3053	0	0	0
T41	0	1194	0	0
T42	167292	0	0	0
T59	0	1142	0	0
T60	1082	279	0	0
T61	51294	0	0	0
T62	19447	0	0	0
T63	81413	0	0	0
T64	454728	0	0	0
T65	332748	0	0	0
T66	8665	0	0	0
T200	85642	0	0	0
T201	0	896	0	0
T202	0	1565	0	0
T203	0	1268	0	0
T204	0	932	0	0
T205	0	955	0	0
T206	0	1143	0	0
T207	0	820	0	0
T208	0	639	0	0
T209	0	1161	0	0
T210	0	371	0	0
T211	0	1286	0	0
T212	0	607	0	0
T213	0	786	0	0
T214	0	497	0	0
T215	0	539	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	892314	0	0
T2	237988	25	0	0
T3	5296	3	0	0
T4	985132	1141	0	0
T5	442364	0	0	0
T6	26754	5	0	0
T7	599128	9	0	0
T8	1485472	74	0	0
T9	0	1301	0	0
T11	83684	0	0	0
T14	849684	220	0	0
T15	0	751	0	0
T16	0	15	0	0
T17	52052	3	0	0
T18	194160	0	0	0
T19	156544	6	0	0
T20	0	1215	0	0
T21	0	2	0	0
T22	0	148	0	0
T34	9950	28	0	0
T35	6106	1	0	0
T37	0	3	0	0
T38	0	39	0	0
T39	0	41	0	0
T40	0	31	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1506548758	0	0
T1	97364	32293	0	0
T2	475976	350052	0	0
T3	10592	8838	0	0
T4	985132	499062	0	0
T5	442364	2089328	0	0
T6	53508	27166	0	0
T7	599128	597503	0	0
T8	1485472	1295619	0	0
T17	104104	86182	0	0
T18	194160	140137	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T17
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T206,T210
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696279621	1883	0	0
DisabledNoTrigBkwd_A	696279621	267392	0	0
DisabledNoTrigFwd_A	696279621	328686840	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	1883	0	0
T3	2648	369	0	0
T4	246283	0	0	0
T5	110591	0	0	0
T6	13377	0	0	0
T7	149782	0	0	0
T8	371368	0	0	0
T11	20921	0	0	0
T17	26026	0	0	0
T18	48540	0	0	0
T34	4975	0	0	0
T206	0	1143	0	0
T210	0	371	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	267392	0	0
T2	118994	15	0	0
T3	2648	3	0	0
T4	246283	2	0	0
T5	110591	0	0	0
T6	13377	2	0	0
T7	149782	0	0	0
T8	371368	9	0	0
T11	20921	0	0	0
T15	0	751	0	0
T17	26026	3	0	0
T18	48540	0	0	0
T19	0	6	0	0
T20	0	1165	0	0
T37	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	328686840	0	0
T1	24341	3716	0	0
T2	118994	583	0	0
T3	2648	2195	0	0
T4	246283	245584	0	0
T5	110591	109326	0	0
T6	13377	8330	0	0
T7	149782	149774	0	0
T8	371368	365693	0	0
T17	26026	8311	0	0
T18	48540	32736	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T6,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T202,T204
1	1	Covered	T2,T6,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696279621	7784	0	0
DisabledNoTrigBkwd_A	696279621	211772	0	0
DisabledNoTrigFwd_A	696279621	406000781	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	7784	0	0
T26	601161	0	0	0
T42	167292	0	0	0
T60	1082	279	0	0
T61	51294	0	0	0
T62	19447	0	0	0
T63	81413	0	0	0
T64	454728	0	0	0
T65	332748	0	0	0
T66	8665	0	0	0
T200	85642	0	0	0
T202	0	1565	0	0
T204	0	932	0	0
T205	0	955	0	0
T207	0	820	0	0
T209	0	1161	0	0
T211	0	1286	0	0
T213	0	786	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	211772	0	0
T2	118994	10	0	0
T3	2648	0	0	0
T4	246283	7	0	0
T5	110591	0	0	0
T6	13377	3	0	0
T7	149782	0	0	0
T8	371368	38	0	0
T9	0	446	0	0
T11	20921	0	0	0
T16	0	15	0	0
T17	26026	0	0	0
T18	48540	0	0	0
T20	0	10	0	0
T22	0	148	0	0
T39	0	41	0	0
T40	0	31	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	406000781	0	0
T1	24341	24259	0	0
T2	118994	123178	0	0
T3	2648	2208	0	0
T4	246283	242301	0	0
T5	110591	90840	0	0
T6	13377	2749	0	0
T7	149782	149430	0	0
T8	371368	364564	0	0
T17	26026	25957	0	0
T18	48540	44968	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T18
1	1	Covered	T1,T2,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T59,T208
1	1	Covered	T1,T2,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696279621	3065	0	0
DisabledNoTrigBkwd_A	696279621	174554	0	0
DisabledNoTrigFwd_A	696279621	392671794	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	3065	0	0
T9	418505	0	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T34	4975	1284	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0
T38	459531	0	0	0
T59	0	1142	0	0
T208	0	639	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	174554	0	0
T4	246283	1132	0	0
T5	110591	0	0	0
T7	149782	9	0	0
T8	371368	27	0	0
T9	0	855	0	0
T11	20921	0	0	0
T14	424842	220	0	0
T18	48540	0	0	0
T19	78272	0	0	0
T20	0	40	0	0
T21	0	2	0	0
T34	4975	28	0	0
T35	3053	1	0	0
T38	0	39	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	392671794	0	0
T1	24341	3724	0	0
T2	118994	107304	0	0
T3	2648	2213	0	0
T4	246283	8105	0	0
T5	110591	938298	0	0
T6	13377	2768	0	0
T7	149782	148525	0	0
T8	371368	365338	0	0
T17	26026	25957	0	0
T18	48540	22646	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T6,T18
1	1	Covered	T1,T4,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T201,T203
1	1	Covered	T1,T4,T18

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696279621	5001	0	0
DisabledNoTrigBkwd_A	696279621	238596	0	0
DisabledNoTrigFwd_A	696279621	379189343	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	5001	0	0
T22	490430	0	0	0
T41	4837	1194	0	0
T42	167292	0	0	0
T59	2220	0	0	0
T60	1082	0	0	0
T61	51294	0	0	0
T62	19447	0	0	0
T63	81413	0	0	0
T64	454728	0	0	0
T65	332748	0	0	0
T201	0	896	0	0
T203	0	1268	0	0
T212	0	607	0	0
T214	0	497	0	0
T215	0	539	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	238596	0	0
T4	246283	948	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	1115	0	0
T11	20921	0	0	0
T14	424842	98	0	0
T15	0	711	0	0
T18	48540	0	0	0
T19	78272	0	0	0
T20	0	41	0	0
T22	0	7377	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	1456	0	0
T40	0	3	0	0
T41	0	20	0	0
T42	0	2352	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	379189343	0	0
T1	24341	594	0	0
T2	118994	118987	0	0
T3	2648	2222	0	0
T4	246283	3072	0	0
T5	110591	950864	0	0
T6	13377	13319	0	0
T7	149782	149774	0	0
T8	371368	200024	0	0
T17	26026	25957	0	0
T18	48540	39787	0	0