Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T18
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T1,T18,T8
1	1	1	Covered	T1,T6,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T18
0	1	Covered	T18,T19,T20
1	0	Covered	T21,T22,T23

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T21,T22,T23

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T18
1	0	Covered	T24,T25
1	1	Covered	T18,T19,T20

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T17
1	Covered	T3,T6,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T17,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T4,T8

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T6,T4,T7

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T6,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T6
Phase1St	198	Covered	T2,T3,T6
Phase2St	215	Covered	T2,T3,T6
Phase3St	233	Covered	T2,T3,T6
TerminalSt	249	Covered	T2,T3,T6
TimeoutSt	159	Covered	T1,T6,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T3,T6
IdleSt->TimeoutSt	159	Covered	T1,T6,T18
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T26,T27,T28
Phase0St->Phase1St	198	Covered	T2,T3,T6
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T20,T28,T29
Phase1St->Phase2St	215	Covered	T2,T3,T6
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T26,T30,T31
Phase2St->Phase3St	233	Covered	T2,T3,T6
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T20,T28,T31
Phase3St->TerminalSt	249	Covered	T2,T3,T6
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T6,T4,T8
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T6,T18
TimeoutSt->Phase0St	172	Covered	T18,T19,T20

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T27,T28
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T6,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T28,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T6,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T30,T31
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T6,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T28,T31
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T6,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T4,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	709	0	0
CheckAccumTrig0_A	2147483647	2355	0	0
CheckAccumTrig1_A	2147483647	120	0	0
CheckClr_A	2147483647	1115	0	0
CheckEn_A	2147483647	1150307302	0	0
CheckPhase0_A	2147483647	2688	0	0
CheckPhase1_A	2147483647	2636	0	0
CheckPhase2_A	2147483647	2575	0	0
CheckPhase3_A	2147483647	2522	0	0
CheckTimeout0_A	2147483647	6348	0	0
CheckTimeoutSt1_A	2147483647	661951	0	0
CheckTimeoutSt2_A	2147483647	5973	0	0
CheckTimeoutStTrig_A	2147483647	252	0	0
ErrorStAllEscAsserted_A	2147483647	3595	0	0
ErrorStIsTerminal_A	2147483647	2995	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	709	0	0
T9	1674020	0	0	0
T11	83684	155	0	0
T12	0	153	0	0
T13	0	127	0	0
T14	1699368	0	0	0
T15	437512	0	0	0
T19	313088	0	0	0
T20	813084	0	0	0
T32	0	157	0	0
T33	0	117	0	0
T34	19900	0	0	0
T35	12212	0	0	0
T36	143328	0	0	0
T37	57352	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2355	0	0
T2	237988	2	0	0
T3	5296	1	0	0
T4	985132	9	0	0
T5	442364	0	0	0
T6	26754	2	0	0
T7	599128	1	0	0
T8	1485472	8	0	0
T9	0	3	0	0
T11	83684	0	0	0
T14	849684	2	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	52052	1	0	0
T18	194160	0	0	0
T19	156544	0	0	0
T20	0	25	0	0
T22	0	6	0	0
T34	9950	1	0	0
T35	6106	1	0	0
T37	0	1	0	0
T38	0	9	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	120	0	0
T21	23107	1	0	0
T22	980860	2	0	0
T23	120142	1	0	0
T24	0	1	0	0
T27	294309	0	0	0
T28	512151	1	0	0
T30	281317	0	0	0
T42	334584	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	4	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	4440	0	0	0
T60	2164	0	0	0
T61	51294	0	0	0
T62	19447	0	0	0
T63	81413	0	0	0
T64	454728	0	0	0
T65	332748	0	0	0
T66	8665	0	0	0
T67	76285	0	0	0
T68	157659	0	0	0
T69	244312	0	0	0
T70	66686	0	0	0
T71	4393	0	0	0
T72	4559	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1115	0	0
T4	985132	5	0	0
T5	442364	0	0	0
T6	26754	2	0	0
T7	599128	0	0	0
T8	1485472	3	0	0
T9	0	1	0	0
T11	83684	0	0	0
T14	849684	0	0	0
T17	52052	0	0	0
T18	194160	0	0	0
T19	156544	0	0	0
T20	0	22	0	0
T22	0	6	0	0
T26	0	6	0	0
T27	0	1	0	0
T28	0	8	0	0
T30	0	7	0	0
T34	19900	0	0	0
T35	12212	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	3	0	0
T65	0	1	0	0
T67	0	3	0	0
T68	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1150307302	0	0
T1	97364	32292	0	0
T2	475976	350051	0	0
T3	10592	8838	0	0
T4	985132	44655	0	0
T5	442364	2089326	0	0
T6	53508	27165	0	0
T7	599128	452050	0	0
T8	1485472	1292982	0	0
T17	104104	86179	0	0
T18	194160	123200	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2688	0	0
T2	237988	2	0	0
T3	5296	1	0	0
T4	985132	6	0	0
T5	442364	0	0	0
T6	26754	2	0	0
T7	599128	1	0	0
T8	1485472	5	0	0
T9	0	3	0	0
T11	83684	0	0	0
T14	849684	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	52052	1	0	0
T18	194160	1	0	0
T19	156544	1	0	0
T20	0	24	0	0
T22	0	6	0	0
T34	9950	1	0	0
T35	6106	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2636	0	0
T2	237988	2	0	0
T3	5296	1	0	0
T4	985132	6	0	0
T5	442364	0	0	0
T6	26754	2	0	0
T7	599128	1	0	0
T8	1485472	5	0	0
T9	0	3	0	0
T11	83684	0	0	0
T14	849684	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	52052	1	0	0
T18	194160	1	0	0
T19	156544	1	0	0
T20	0	23	0	0
T22	0	6	0	0
T34	9950	1	0	0
T35	6106	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2575	0	0
T2	237988	2	0	0
T3	5296	1	0	0
T4	985132	6	0	0
T5	442364	0	0	0
T6	26754	2	0	0
T7	599128	1	0	0
T8	1485472	5	0	0
T9	0	3	0	0
T11	83684	0	0	0
T14	849684	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	52052	1	0	0
T18	194160	1	0	0
T19	156544	1	0	0
T20	0	23	0	0
T22	0	6	0	0
T34	9950	1	0	0
T35	6106	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2522	0	0
T2	237988	2	0	0
T3	5296	1	0	0
T4	985132	6	0	0
T5	442364	0	0	0
T6	26754	2	0	0
T7	599128	1	0	0
T8	1485472	5	0	0
T9	0	3	0	0
T11	83684	0	0	0
T14	849684	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	52052	1	0	0
T18	194160	1	0	0
T19	156544	1	0	0
T20	0	18	0	0
T22	0	6	0	0
T34	9950	1	0	0
T35	6106	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6348	0	0
T1	73023	24	0	0
T2	356982	0	0	0
T3	7944	0	0	0
T4	738849	0	0	0
T5	442364	0	0	0
T6	40131	1	0	0
T7	599128	0	0	0
T8	1485472	4	0	0
T11	20921	0	0	0
T14	424842	0	0	0
T17	78078	0	0	0
T18	194160	7	0	0
T19	78272	1	0	0
T20	203271	13	0	0
T21	0	1	0	0
T22	0	23	0	0
T23	0	2	0	0
T28	0	7	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	21	0	0
T40	0	2	0	0
T42	0	1	0	0
T65	0	2	0	0
T67	0	4	0	0
T70	0	1	0	0
T71	0	1	0	0
T76	0	3	0	0
T77	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	661951	0	0
T1	73023	1179	0	0
T2	356982	0	0	0
T3	7944	0	0	0
T4	738849	0	0	0
T5	442364	0	0	0
T6	40131	197	0	0
T7	599128	0	0	0
T8	1485472	573	0	0
T11	20921	0	0	0
T14	424842	0	0	0
T17	78078	0	0	0
T18	194160	1254	0	0
T19	78272	34	0	0
T20	203271	2050	0	0
T21	0	4	0	0
T22	0	3234	0	0
T23	0	205	0	0
T28	0	1070	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	1663	0	0
T40	0	307	0	0
T42	0	181	0	0
T65	0	169	0	0
T67	0	1241	0	0
T70	0	89	0	0
T71	0	116	0	0
T76	0	546	0	0
T77	0	382	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5973	0	0
T1	73023	24	0	0
T2	356982	0	0	0
T3	7944	0	0	0
T4	738849	0	0	0
T5	442364	0	0	0
T6	40131	1	0	0
T7	599128	0	0	0
T8	1485472	4	0	0
T11	20921	0	0	0
T14	424842	0	0	0
T17	78078	0	0	0
T18	194160	6	0	0
T19	78272	0	0	0
T20	203271	11	0	0
T22	0	15	0	0
T23	0	1	0	0
T28	0	1	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	18	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	4	0	0
T44	0	3	0	0
T65	0	1	0	0
T67	0	4	0	0
T71	0	1	0	0
T75	0	3	0	0
T76	0	3	0	0
T77	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	252	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	0	0	0
T9	837010	0	0	0
T10	1524069	0	0	0
T11	20921	0	0	0
T14	424842	0	0	0
T15	218756	0	0	0
T16	123595	0	0	0
T18	48540	1	0	0
T19	156544	1	0	0
T20	609813	1	0	0
T21	69321	0	0	0
T22	0	5	0	0
T28	0	6	0	0
T29	0	3	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	71664	0	0	0
T37	28676	0	0	0
T38	1378593	2	0	0
T39	561543	0	0	0
T40	51150	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T54	0	1	0	0
T67	0	1	0	0
T70	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	33644	0	0	0
T78	0	3	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	6	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3595	0	0
T9	1674020	0	0	0
T11	83684	736	0	0
T12	0	729	0	0
T13	0	689	0	0
T14	1699368	0	0	0
T15	437512	0	0	0
T19	313088	0	0	0
T20	813084	0	0	0
T32	0	728	0	0
T33	0	713	0	0
T34	19900	0	0	0
T35	12212	0	0	0
T36	143328	0	0	0
T37	57352	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2995	0	0
T9	1674020	0	0	0
T11	83684	616	0	0
T12	0	609	0	0
T13	0	569	0	0
T14	1699368	0	0	0
T15	437512	0	0	0
T19	313088	0	0	0
T20	813084	0	0	0
T32	0	608	0	0
T33	0	593	0	0
T34	19900	0	0	0
T35	12212	0	0	0
T36	143328	0	0	0
T37	57352	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	97364	97036	0	0
T2	475976	475948	0	0
T3	10592	10384	0	0
T4	985132	985100	0	0
T5	442364	442328	0	0
T6	53508	53276	0	0
T7	599128	599096	0	0
T8	1485472	1485368	0	0
T17	104104	103828	0	0
T18	194160	193952	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	97364	97036	0	0
T2	475976	475948	0	0
T3	10592	10384	0	0
T4	985132	985100	0	0
T5	442364	442328	0	0
T6	53508	53276	0	0
T7	599128	599096	0	0
T8	1485472	1485368	0	0
T17	104104	103828	0	0
T18	194160	193952	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T6,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T18,T8
1	0	1	Covered	T2,T4,T7
1	1	0	Covered	T1,T18,T8
1	1	1	Covered	T18,T20,T38

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T38
0	1	Covered	T20,T22,T70
1	0	Covered	T23,T44,T46

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T18,T20,T38
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T44,T46

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T38
1	0	Not Covered
1	1	Covered	T20,T22,T70

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T8
1	Covered	T6,T20,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T20,T40,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T8,T20
1	Covered	T2,T4,T9

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T8,T20,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T20,T9,T39

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T8,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T4,T8

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T6,T4
Phase1St	198	Covered	T2,T6,T4
Phase2St	215	Covered	T2,T6,T4
Phase3St	233	Covered	T2,T6,T4
TerminalSt	249	Covered	T2,T6,T4
TimeoutSt	159	Covered	T18,T20,T38

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T6,T4
IdleSt->TimeoutSt	159	Covered	T18,T20,T38
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T28,T49
Phase0St->Phase1St	198	Covered	T2,T6,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T82,T31,T49
Phase1St->Phase2St	215	Covered	T2,T6,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T83,T84
Phase2St->Phase3St	233	Covered	T2,T6,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T20,T28,T49
Phase3St->TerminalSt	249	Covered	T2,T6,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T6,T4,T8
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T18,T20,T38
TimeoutSt->Phase0St	172	Covered	T20,T22,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T38
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T22,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T38
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T38
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T28,T85
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T6,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T6,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T82,T31,T51
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T6,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T6,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T83,T84
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T6,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T6,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T28,T49
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T6,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T6,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T4,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T6,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696279621	178	0	0
CheckAccumTrig0_A	696279621	485	0	0
CheckAccumTrig1_A	696279621	24	0	0
CheckClr_A	696279621	236	0	0
CheckEn_A	696137851	327059724	0	0
CheckPhase0_A	696279621	564	0	0
CheckPhase1_A	696279621	551	0	0
CheckPhase2_A	696279621	541	0	0
CheckPhase3_A	696279621	524	0	0
CheckTimeout0_A	696279621	1059	0	0
CheckTimeoutSt1_A	696279621	133088	0	0
CheckTimeoutSt2_A	696279621	969	0	0
CheckTimeoutStTrig_A	696279621	65	0	0
ErrorStAllEscAsserted_A	696279621	950	0	0
ErrorStIsTerminal_A	696279621	800	0	0
EscStateOut_A	696136492	696064516	0	0
u_state_regs_A	696279621	696143932	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	178	0	0
T9	418505	0	0	0
T11	20921	39	0	0
T12	0	45	0	0
T13	0	29	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T32	0	32	0	0
T33	0	33	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	485	0	0
T2	118994	1	0	0
T3	2648	0	0	0
T4	246283	2	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	1	0	0
T9	0	2	0	0
T11	20921	0	0	0
T16	0	1	0	0
T17	26026	0	0	0
T18	48540	0	0	0
T20	0	5	0	0
T22	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	24	0	0
T23	120142	1	0	0
T24	0	1	0	0
T27	294309	0	0	0
T28	512151	0	0	0
T30	281317	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	4	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T67	76285	0	0	0
T68	157659	0	0	0
T69	244312	0	0	0
T70	66686	0	0	0
T71	4393	0	0	0
T72	4559	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	236	0	0
T4	246283	1	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	0	0	0
T9	0	1	0	0
T11	20921	0	0	0
T17	26026	0	0	0
T18	48540	0	0	0
T20	0	5	0	0
T22	0	2	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	0	4	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696137851	327059724	0	0
T1	24341	24258	0	0
T2	118994	123178	0	0
T3	2648	2208	0	0
T4	246283	22913	0	0
T5	110591	90840	0	0
T6	13377	2749	0	0
T7	149782	149430	0	0
T8	371368	364564	0	0
T17	26026	25956	0	0
T18	48540	44967	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	564	0	0
T2	118994	1	0	0
T3	2648	0	0	0
T4	246283	2	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	1	0	0
T9	0	2	0	0
T11	20921	0	0	0
T16	0	1	0	0
T17	26026	0	0	0
T18	48540	0	0	0
T20	0	6	0	0
T22	0	6	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	551	0	0
T2	118994	1	0	0
T3	2648	0	0	0
T4	246283	2	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	1	0	0
T9	0	2	0	0
T11	20921	0	0	0
T16	0	1	0	0
T17	26026	0	0	0
T18	48540	0	0	0
T20	0	6	0	0
T22	0	6	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	541	0	0
T2	118994	1	0	0
T3	2648	0	0	0
T4	246283	2	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	1	0	0
T9	0	2	0	0
T11	20921	0	0	0
T16	0	1	0	0
T17	26026	0	0	0
T18	48540	0	0	0
T20	0	6	0	0
T22	0	6	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	524	0	0
T2	118994	1	0	0
T3	2648	0	0	0
T4	246283	2	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	1	0	0
T9	0	2	0	0
T11	20921	0	0	0
T16	0	1	0	0
T17	26026	0	0	0
T18	48540	0	0	0
T20	0	5	0	0
T22	0	6	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	1059	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	0	0	0
T11	20921	0	0	0
T14	424842	0	0	0
T18	48540	1	0	0
T19	78272	0	0	0
T20	203271	4	0	0
T22	0	6	0	0
T23	0	1	0	0
T28	0	6	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	3	0	0
T42	0	1	0	0
T67	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	133088	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	0	0	0
T11	20921	0	0	0
T14	424842	0	0	0
T18	48540	198	0	0
T19	78272	0	0	0
T20	203271	427	0	0
T22	0	1655	0	0
T23	0	3	0	0
T28	0	855	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	263	0	0
T42	0	181	0	0
T67	0	49	0	0
T70	0	89	0	0
T71	0	116	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	969	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	0	0	0
T11	20921	0	0	0
T14	424842	0	0	0
T18	48540	1	0	0
T19	78272	0	0	0
T20	203271	3	0	0
T22	0	4	0	0
T28	0	1	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	3	0	0
T42	0	1	0	0
T43	0	1	0	0
T67	0	1	0	0
T71	0	1	0	0
T77	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	65	0	0
T9	418505	0	0	0
T10	508023	0	0	0
T15	109378	0	0	0
T20	203271	1	0	0
T21	23107	0	0	0
T22	0	2	0	0
T28	0	5	0	0
T29	0	1	0	0
T36	35832	0	0	0
T37	14338	0	0	0
T38	459531	0	0	0
T39	187181	0	0	0
T40	25575	0	0	0
T47	0	1	0	0
T54	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T81	0	4	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	950	0	0
T9	418505	0	0	0
T11	20921	186	0	0
T12	0	203	0	0
T13	0	177	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T32	0	193	0	0
T33	0	191	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	800	0	0
T9	418505	0	0	0
T11	20921	156	0	0
T12	0	173	0	0
T13	0	147	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T32	0	163	0	0
T33	0	161	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696136492	696064516	0	0
T1	24341	24259	0	0
T2	118994	118987	0	0
T3	2648	2596	0	0
T4	246283	246275	0	0
T5	110591	110582	0	0
T6	13377	13319	0	0
T7	149782	149774	0	0
T8	371368	371342	0	0
T17	26026	25957	0	0
T18	48540	48488	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	696143932	0	0
T1	24341	24259	0	0
T2	118994	118987	0	0
T3	2648	2596	0	0
T4	246283	246275	0	0
T5	110591	110582	0	0
T6	13377	13319	0	0
T7	149782	149774	0	0
T8	371368	371342	0	0
T17	26026	25957	0	0
T18	48540	48488	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T18
1	0	1	Covered	T2,T7,T34
1	1	0	Covered	T18,T20,T38
1	1	1	Covered	T1,T6,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T18
0	1	Covered	T18,T38,T22
1	0	Covered	T21,T43,T74

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T6,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T43,T74

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T18
1	0	Not Covered
1	1	Covered	T18,T38,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T8
1	Covered	T4,T18,T34

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T18,T7
1	Covered	T4,T35,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T18,T7
1	Covered	T8,T20,T9

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T18,T8
1	Covered	T4,T7,T38

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T18,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T18,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T18,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T18,T34

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T18,T7
Phase1St	198	Covered	T4,T18,T7
Phase2St	215	Covered	T4,T18,T7
Phase3St	233	Covered	T4,T18,T7
TerminalSt	249	Covered	T4,T18,T7
TimeoutSt	159	Covered	T1,T6,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T4,T7,T8
IdleSt->TimeoutSt	159	Covered	T1,T6,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T86,T87,T88
Phase0St->Phase1St	198	Covered	T4,T18,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T89,T84,T90
Phase1St->Phase2St	215	Covered	T4,T18,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T26,T31,T91
Phase2St->Phase3St	233	Covered	T4,T18,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T91,T56,T92
Phase3St->TerminalSt	249	Covered	T4,T18,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T8,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T6,T18
TimeoutSt->Phase0St	172	Covered	T18,T38,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T38,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T86,T88,T93
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T18,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T18,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T89,T84,T90
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T18,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T18,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T31,T91
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T18,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T18,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T91,T56,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T18,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T18,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T22,T65
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T18,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696279621	183	0	0
CheckAccumTrig0_A	696279621	504	0	0
CheckAccumTrig1_A	696279621	29	0	0
CheckClr_A	696279621	225	0	0
CheckEn_A	696137851	285867215	0	0
CheckPhase0_A	696279621	588	0	0
CheckPhase1_A	696279621	584	0	0
CheckPhase2_A	696279621	569	0	0
CheckPhase3_A	696279621	563	0	0
CheckTimeout0_A	696279621	1838	0	0
CheckTimeoutSt1_A	696279621	134191	0	0
CheckTimeoutSt2_A	696279621	1745	0	0
CheckTimeoutStTrig_A	696279621	63	0	0
ErrorStAllEscAsserted_A	696279621	879	0	0
ErrorStIsTerminal_A	696279621	729	0	0
EscStateOut_A	696136492	696064516	0	0
u_state_regs_A	696279621	696143932	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	183	0	0
T9	418505	0	0	0
T11	20921	41	0	0
T12	0	27	0	0
T13	0	35	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T32	0	39	0	0
T33	0	41	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	504	0	0
T4	246283	3	0	0
T5	110591	0	0	0
T7	149782	1	0	0
T8	371368	1	0	0
T9	0	1	0	0
T11	20921	0	0	0
T14	424842	1	0	0
T18	48540	0	0	0
T19	78272	0	0	0
T20	0	1	0	0
T34	4975	1	0	0
T35	3053	1	0	0
T38	0	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	29	0	0
T16	123595	0	0	0
T21	23107	1	0	0
T22	490430	0	0	0
T40	25575	0	0	0
T41	4837	0	0	0
T42	167292	0	0	0
T43	0	1	0	0
T53	0	1	0	0
T59	2220	0	0	0
T60	1082	0	0	0
T74	0	1	0	0
T76	33644	0	0	0
T87	0	2	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	28294	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	225	0	0
T4	246283	2	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	0	0	0
T11	20921	0	0	0
T14	424842	0	0	0
T18	48540	0	0	0
T19	78272	0	0	0
T22	0	3	0	0
T26	0	2	0	0
T28	0	1	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T65	0	1	0	0
T67	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696137851	285867215	0	0
T1	24341	3724	0	0
T2	118994	107303	0	0
T3	2648	2213	0	0
T4	246283	8105	0	0
T5	110591	938297	0	0
T6	13377	2768	0	0
T7	149782	3072	0	0
T8	371368	365338	0	0
T17	26026	25956	0	0
T18	48540	5712	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	588	0	0
T4	246283	3	0	0
T5	110591	0	0	0
T7	149782	1	0	0
T8	371368	1	0	0
T9	0	1	0	0
T11	20921	0	0	0
T14	424842	1	0	0
T18	48540	1	0	0
T19	78272	0	0	0
T20	0	1	0	0
T34	4975	1	0	0
T35	3053	1	0	0
T38	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	584	0	0
T4	246283	3	0	0
T5	110591	0	0	0
T7	149782	1	0	0
T8	371368	1	0	0
T9	0	1	0	0
T11	20921	0	0	0
T14	424842	1	0	0
T18	48540	1	0	0
T19	78272	0	0	0
T20	0	1	0	0
T34	4975	1	0	0
T35	3053	1	0	0
T38	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	569	0	0
T4	246283	3	0	0
T5	110591	0	0	0
T7	149782	1	0	0
T8	371368	1	0	0
T9	0	1	0	0
T11	20921	0	0	0
T14	424842	1	0	0
T18	48540	1	0	0
T19	78272	0	0	0
T20	0	1	0	0
T34	4975	1	0	0
T35	3053	1	0	0
T38	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	563	0	0
T4	246283	3	0	0
T5	110591	0	0	0
T7	149782	1	0	0
T8	371368	1	0	0
T9	0	1	0	0
T11	20921	0	0	0
T14	424842	1	0	0
T18	48540	1	0	0
T19	78272	0	0	0
T20	0	1	0	0
T34	4975	1	0	0
T35	3053	1	0	0
T38	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	1838	0	0
T1	24341	9	0	0
T2	118994	0	0	0
T3	2648	0	0	0
T4	246283	0	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	2	0	0
T17	26026	0	0	0
T18	48540	2	0	0
T20	0	3	0	0
T21	0	1	0	0
T22	0	3	0	0
T28	0	1	0	0
T38	0	9	0	0
T67	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	134191	0	0
T1	24341	460	0	0
T2	118994	0	0	0
T3	2648	0	0	0
T4	246283	0	0	0
T5	110591	0	0	0
T6	13377	197	0	0
T7	149782	0	0	0
T8	371368	273	0	0
T17	26026	0	0	0
T18	48540	333	0	0
T20	0	742	0	0
T21	0	4	0	0
T22	0	148	0	0
T28	0	215	0	0
T38	0	790	0	0
T67	0	477	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	1745	0	0
T1	24341	9	0	0
T2	118994	0	0	0
T3	2648	0	0	0
T4	246283	0	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	2	0	0
T17	26026	0	0	0
T18	48540	1	0	0
T20	0	3	0	0
T22	0	1	0	0
T38	0	8	0	0
T43	0	3	0	0
T44	0	3	0	0
T67	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	63	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	0	0	0
T11	20921	0	0	0
T14	424842	0	0	0
T18	48540	1	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T22	0	2	0	0
T28	0	1	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	1	0	0
T44	0	1	0	0
T51	0	2	0	0
T67	0	1	0	0
T74	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	879	0	0
T9	418505	0	0	0
T11	20921	167	0	0
T12	0	175	0	0
T13	0	160	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T32	0	187	0	0
T33	0	190	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	729	0	0
T9	418505	0	0	0
T11	20921	137	0	0
T12	0	145	0	0
T13	0	130	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T32	0	157	0	0
T33	0	160	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696136492	696064516	0	0
T1	24341	24259	0	0
T2	118994	118987	0	0
T3	2648	2596	0	0
T4	246283	246275	0	0
T5	110591	110582	0	0
T6	13377	13319	0	0
T7	149782	149774	0	0
T8	371368	371342	0	0
T17	26026	25957	0	0
T18	48540	48488	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	696143932	0	0
T1	24341	24259	0	0
T2	118994	118987	0	0
T3	2648	2596	0	0
T4	246283	246275	0	0
T5	110591	110582	0	0
T6	13377	13319	0	0
T7	149782	149774	0	0
T8	371368	371342	0	0
T17	26026	25957	0	0
T18	48540	48488	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T18
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T18

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T14

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T18,T8
1	0	1	Covered	T4,T14,T9
1	1	0	Covered	T18,T20,T38
1	1	1	Covered	T1,T18,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T20
0	1	Covered	T38,T22,T44
1	0	Covered	T20,T65,T46

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T18,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T65,T46

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T20
1	0	Not Covered
1	1	Covered	T38,T22,T44

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T8,T14
1	Covered	T4,T20,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T8,T20
1	Covered	T14,T20,T38

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T8,T14
1	Covered	T8,T38,T40

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T8,T14
1	Covered	T4,T8,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T8,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T8,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T8,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T8,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T8,T14
Phase1St	198	Covered	T4,T8,T14
Phase2St	215	Covered	T4,T8,T14
Phase3St	233	Covered	T4,T8,T14
TerminalSt	249	Covered	T4,T8,T14
TimeoutSt	159	Covered	T1,T18,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T4,T8,T14
IdleSt->TimeoutSt	159	Covered	T1,T18,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T97,T100,T101
Phase0St->Phase1St	198	Covered	T4,T8,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T102,T24,T103
Phase1St->Phase2St	215	Covered	T4,T8,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T104,T55,T24
Phase2St->Phase3St	233	Covered	T4,T8,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T105,T104,T106
Phase3St->TerminalSt	249	Covered	T4,T8,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T8,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T18,T20
TimeoutSt->Phase0St	172	Covered	T20,T38,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T38,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T97,T100,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T8,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T8,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T102,T24,T103
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T8,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T8,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T104,T55,T24
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T8,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T8,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T105,T104,T106
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T8,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T8,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T8,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T8,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696279621	186	0	0
CheckAccumTrig0_A	696279621	542	0	0
CheckAccumTrig1_A	696279621	21	0	0
CheckClr_A	696279621	256	0	0
CheckEn_A	696137851	287833970	0	0
CheckPhase0_A	696279621	614	0	0
CheckPhase1_A	696279621	606	0	0
CheckPhase2_A	696279621	596	0	0
CheckPhase3_A	696279621	590	0	0
CheckTimeout0_A	696279621	1346	0	0
CheckTimeoutSt1_A	696279621	156260	0	0
CheckTimeoutSt2_A	696279621	1262	0	0
CheckTimeoutStTrig_A	696279621	62	0	0
ErrorStAllEscAsserted_A	696279621	903	0	0
ErrorStIsTerminal_A	696279621	753	0	0
EscStateOut_A	696136492	696064516	0	0
u_state_regs_A	696279621	696143932	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	186	0	0
T9	418505	0	0	0
T11	20921	28	0	0
T12	0	45	0	0
T13	0	41	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T32	0	53	0	0
T33	0	19	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	542	0	0
T4	246283	3	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	3	0	0
T11	20921	0	0	0
T14	424842	1	0	0
T15	0	1	0	0
T18	48540	0	0	0
T19	78272	0	0	0
T20	0	2	0	0
T22	0	2	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	3	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	21	0	0
T9	418505	0	0	0
T10	508023	0	0	0
T15	109378	0	0	0
T20	203271	1	0	0
T21	23107	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0
T38	459531	0	0	0
T39	187181	0	0	0
T40	25575	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T65	0	1	0	0
T86	0	2	0	0
T95	0	1	0	0
T97	0	1	0	0
T107	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	256	0	0
T4	246283	2	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	1	0	0
T11	20921	0	0	0
T14	424842	0	0	0
T18	48540	0	0	0
T19	78272	0	0	0
T20	0	2	0	0
T26	0	1	0	0
T30	0	1	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T44	0	2	0	0
T64	0	1	0	0
T108	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696137851	287833970	0	0
T1	24341	594	0	0
T2	118994	118987	0	0
T3	2648	2222	0	0
T4	246283	3072	0	0
T5	110591	950863	0	0
T6	13377	13318	0	0
T7	149782	149774	0	0
T8	371368	200022	0	0
T17	26026	25956	0	0
T18	48540	39786	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	614	0	0
T4	246283	3	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	3	0	0
T11	20921	0	0	0
T14	424842	1	0	0
T15	0	1	0	0
T18	48540	0	0	0
T19	78272	0	0	0
T20	0	3	0	0
T22	0	3	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	4	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	606	0	0
T4	246283	3	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	3	0	0
T11	20921	0	0	0
T14	424842	1	0	0
T15	0	1	0	0
T18	48540	0	0	0
T19	78272	0	0	0
T20	0	3	0	0
T22	0	3	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	4	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	596	0	0
T4	246283	3	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	3	0	0
T11	20921	0	0	0
T14	424842	1	0	0
T15	0	1	0	0
T18	48540	0	0	0
T19	78272	0	0	0
T20	0	3	0	0
T22	0	3	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	4	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	590	0	0
T4	246283	3	0	0
T5	110591	0	0	0
T7	149782	0	0	0
T8	371368	3	0	0
T11	20921	0	0	0
T14	424842	1	0	0
T15	0	1	0	0
T18	48540	0	0	0
T19	78272	0	0	0
T20	0	3	0	0
T22	0	3	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T38	0	4	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	1346	0	0
T1	24341	6	0	0
T2	118994	0	0	0
T3	2648	0	0	0
T4	246283	0	0	0
T5	110591	0	0	0
T6	13377	0	0	0
T7	149782	0	0	0
T8	371368	0	0	0
T17	26026	0	0	0
T18	48540	1	0	0
T20	0	3	0	0
T22	0	3	0	0
T23	0	1	0	0
T38	0	5	0	0
T65	0	1	0	0
T67	0	1	0	0
T76	0	2	0	0
T77	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	156260	0	0
T1	24341	302	0	0
T2	118994	0	0	0
T3	2648	0	0	0
T4	246283	0	0	0
T5	110591	0	0	0
T6	13377	0	0	0
T7	149782	0	0	0
T8	371368	0	0	0
T17	26026	0	0	0
T18	48540	198	0	0
T20	0	340	0	0
T22	0	558	0	0
T23	0	202	0	0
T38	0	314	0	0
T65	0	9	0	0
T67	0	715	0	0
T76	0	373	0	0
T77	0	382	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	1262	0	0
T1	24341	6	0	0
T2	118994	0	0	0
T3	2648	0	0	0
T4	246283	0	0	0
T5	110591	0	0	0
T6	13377	0	0	0
T7	149782	0	0	0
T8	371368	0	0	0
T17	26026	0	0	0
T18	48540	1	0	0
T20	0	2	0	0
T22	0	2	0	0
T23	0	1	0	0
T38	0	4	0	0
T67	0	1	0	0
T75	0	3	0	0
T76	0	2	0	0
T77	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	62	0	0
T10	508023	0	0	0
T16	123595	0	0	0
T21	23107	0	0	0
T22	490430	1	0	0
T38	459531	1	0	0
T39	187181	0	0	0
T40	25575	0	0	0
T41	4837	0	0	0
T44	0	1	0	0
T53	0	1	0	0
T76	33644	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	2	0	0
T99	28294	0	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	903	0	0
T9	418505	0	0	0
T11	20921	189	0	0
T12	0	180	0	0
T13	0	194	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T32	0	173	0	0
T33	0	167	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	753	0	0
T9	418505	0	0	0
T11	20921	159	0	0
T12	0	150	0	0
T13	0	164	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T32	0	143	0	0
T33	0	137	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696136492	696064516	0	0
T1	24341	24259	0	0
T2	118994	118987	0	0
T3	2648	2596	0	0
T4	246283	246275	0	0
T5	110591	110582	0	0
T6	13377	13319	0	0
T7	149782	149774	0	0
T8	371368	371342	0	0
T17	26026	25957	0	0
T18	48540	48488	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	696143932	0	0
T1	24341	24259	0	0
T2	118994	118987	0	0
T3	2648	2596	0	0
T4	246283	246275	0	0
T5	110591	110582	0	0
T6	13377	13319	0	0
T7	149782	149774	0	0
T8	371368	371342	0	0
T17	26026	25957	0	0
T18	48540	48488	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T18
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T18,T8,T20
1	1	1	Covered	T1,T18,T8

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T8
0	1	Covered	T19,T38,T22
1	0	Covered	T22,T28,T44

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T18,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T28,T44

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T8
1	0	Covered	T24,T25
1	1	Covered	T19,T38,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T17
1	Covered	T3,T4,T8

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T4
1	Covered	T2,T17,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T19,T15,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T6,T20,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T17,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T8

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T6
Phase1St	198	Covered	T2,T3,T6
Phase2St	215	Covered	T2,T3,T6
Phase3St	233	Covered	T2,T3,T6
TerminalSt	249	Covered	T2,T3,T6
TimeoutSt	159	Covered	T1,T18,T8

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T3,T6
IdleSt->TimeoutSt	159	Covered	T1,T18,T8
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T26,T28,T48
Phase0St->Phase1St	198	Covered	T2,T3,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T20,T28,T29
Phase1St->Phase2St	215	Covered	T2,T3,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T30,T31,T51
Phase2St->Phase3St	233	Covered	T2,T3,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T20,T31,T112
Phase3St->TerminalSt	249	Covered	T2,T3,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T6,T8,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T18,T8
TimeoutSt->Phase0St	172	Covered	T19,T38,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T8
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T38,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T28,T48
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T6,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T28,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T6,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T30,T31,T51
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T6,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T31,T112
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T6,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T8,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696279621	162	0	0
CheckAccumTrig0_A	696279621	824	0	0
CheckAccumTrig1_A	696279621	46	0	0
CheckClr_A	696279621	398	0	0
CheckEn_A	696137851	249546393	0	0
CheckPhase0_A	696279621	922	0	0
CheckPhase1_A	696279621	895	0	0
CheckPhase2_A	696279621	869	0	0
CheckPhase3_A	696279621	845	0	0
CheckTimeout0_A	696279621	2105	0	0
CheckTimeoutSt1_A	696279621	238412	0	0
CheckTimeoutSt2_A	696279621	1997	0	0
CheckTimeoutStTrig_A	696279621	62	0	0
ErrorStAllEscAsserted_A	696279621	863	0	0
ErrorStIsTerminal_A	696279621	713	0	0
EscStateOut_A	696136492	696064516	0	0
u_state_regs_A	696279621	696143932	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	162	0	0
T9	418505	0	0	0
T11	20921	47	0	0
T12	0	36	0	0
T13	0	22	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T32	0	33	0	0
T33	0	24	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	824	0	0
T2	118994	1	0	0
T3	2648	1	0	0
T4	246283	1	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	3	0	0
T11	20921	0	0	0
T15	0	1	0	0
T17	26026	1	0	0
T18	48540	0	0	0
T20	0	17	0	0
T37	0	1	0	0
T38	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	46	0	0
T22	490430	2	0	0
T28	0	1	0	0
T42	167292	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T59	2220	0	0	0
T60	1082	0	0	0
T61	51294	0	0	0
T62	19447	0	0	0
T63	81413	0	0	0
T64	454728	0	0	0
T65	332748	0	0	0
T66	8665	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	398	0	0
T4	246283	0	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	2	0	0
T11	20921	0	0	0
T17	26026	0	0	0
T18	48540	0	0	0
T20	0	15	0	0
T22	0	1	0	0
T26	0	2	0	0
T28	0	3	0	0
T30	0	6	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T42	0	3	0	0
T67	0	1	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696137851	249546393	0	0
T1	24341	3716	0	0
T2	118994	583	0	0
T3	2648	2195	0	0
T4	246283	10565	0	0
T5	110591	109326	0	0
T6	13377	8330	0	0
T7	149782	149774	0	0
T8	371368	363058	0	0
T17	26026	8311	0	0
T18	48540	32735	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	922	0	0
T2	118994	1	0	0
T3	2648	1	0	0
T4	246283	1	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	3	0	0
T11	20921	0	0	0
T15	0	1	0	0
T17	26026	1	0	0
T18	48540	0	0	0
T19	0	1	0	0
T20	0	17	0	0
T37	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	895	0	0
T2	118994	1	0	0
T3	2648	1	0	0
T4	246283	1	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	3	0	0
T11	20921	0	0	0
T15	0	1	0	0
T17	26026	1	0	0
T18	48540	0	0	0
T19	0	1	0	0
T20	0	16	0	0
T37	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	869	0	0
T2	118994	1	0	0
T3	2648	1	0	0
T4	246283	1	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	3	0	0
T11	20921	0	0	0
T15	0	1	0	0
T17	26026	1	0	0
T18	48540	0	0	0
T19	0	1	0	0
T20	0	16	0	0
T37	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	845	0	0
T2	118994	1	0	0
T3	2648	1	0	0
T4	246283	1	0	0
T5	110591	0	0	0
T6	13377	1	0	0
T7	149782	0	0	0
T8	371368	3	0	0
T11	20921	0	0	0
T15	0	1	0	0
T17	26026	1	0	0
T18	48540	0	0	0
T19	0	1	0	0
T20	0	12	0	0
T37	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	2105	0	0
T1	24341	9	0	0
T2	118994	0	0	0
T3	2648	0	0	0
T4	246283	0	0	0
T5	110591	0	0	0
T6	13377	0	0	0
T7	149782	0	0	0
T8	371368	2	0	0
T17	26026	0	0	0
T18	48540	3	0	0
T19	0	1	0	0
T20	0	3	0	0
T22	0	11	0	0
T38	0	4	0	0
T40	0	2	0	0
T65	0	1	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	238412	0	0
T1	24341	417	0	0
T2	118994	0	0	0
T3	2648	0	0	0
T4	246283	0	0	0
T5	110591	0	0	0
T6	13377	0	0	0
T7	149782	0	0	0
T8	371368	300	0	0
T17	26026	0	0	0
T18	48540	525	0	0
T19	0	34	0	0
T20	0	541	0	0
T22	0	873	0	0
T38	0	296	0	0
T40	0	307	0	0
T65	0	160	0	0
T76	0	173	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	1997	0	0
T1	24341	9	0	0
T2	118994	0	0	0
T3	2648	0	0	0
T4	246283	0	0	0
T5	110591	0	0	0
T6	13377	0	0	0
T7	149782	0	0	0
T8	371368	2	0	0
T17	26026	0	0	0
T18	48540	3	0	0
T20	0	3	0	0
T22	0	8	0	0
T38	0	3	0	0
T40	0	2	0	0
T65	0	1	0	0
T67	0	1	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	62	0	0
T9	418505	0	0	0
T10	508023	0	0	0
T15	109378	0	0	0
T19	78272	1	0	0
T20	203271	0	0	0
T21	23107	0	0	0
T22	0	1	0	0
T29	0	2	0	0
T36	35832	0	0	0
T37	14338	0	0	0
T38	459531	1	0	0
T39	187181	0	0	0
T45	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	863	0	0
T9	418505	0	0	0
T11	20921	194	0	0
T12	0	171	0	0
T13	0	158	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T32	0	175	0	0
T33	0	165	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	713	0	0
T9	418505	0	0	0
T11	20921	164	0	0
T12	0	141	0	0
T13	0	128	0	0
T14	424842	0	0	0
T15	109378	0	0	0
T19	78272	0	0	0
T20	203271	0	0	0
T32	0	145	0	0
T33	0	135	0	0
T34	4975	0	0	0
T35	3053	0	0	0
T36	35832	0	0	0
T37	14338	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696136492	696064516	0	0
T1	24341	24259	0	0
T2	118994	118987	0	0
T3	2648	2596	0	0
T4	246283	246275	0	0
T5	110591	110582	0	0
T6	13377	13319	0	0
T7	149782	149774	0	0
T8	371368	371342	0	0
T17	26026	25957	0	0
T18	48540	48488	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696279621	696143932	0	0
T1	24341	24259	0	0
T2	118994	118987	0	0
T3	2648	2596	0	0
T4	246283	246275	0	0
T5	110591	110582	0	0
T6	13377	13319	0	0
T7	149782	149774	0	0
T8	371368	371342	0	0
T17	26026	25957	0	0
T18	48540	48488	0	0