Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	68550740	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33408078

1

T1

2118

T2

96345

T3

4119

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15365684	1			T1	858		T2	37701		T3	1555
values[0x0]	42037209	1			T1	2799		T2	133942		T3	5646
values[0x1]	44555925	1			T1	2835		T2	134560		T3	5586

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58298717	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

43660101

1

T1

2661

T2

122029

T3

5144

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	330114	1			T2	1093		T3	43		T17	1113
valid_sources[0x01]	643411	1			T2	1150		T3	54		T4	3
valid_sources[0x02]	314682	1			T2	1310		T3	54		T4	8
valid_sources[0x03]	311416	1			T2	1222		T3	64		T4	3
valid_sources[0x04]	859921	1			T2	1229		T3	64		T4	2
valid_sources[0x05]	315618	1			T2	1188		T3	43		T4	4
valid_sources[0x06]	318573	1			T2	1125		T3	37		T4	2
valid_sources[0x07]	324865	1			T2	1285		T3	52		T4	3
valid_sources[0x08]	365229	1			T2	1267		T3	42		T4	1
valid_sources[0x09]	322012	1			T2	1189		T3	59		T17	1056
valid_sources[0x0a]	567130	1			T2	1165		T3	43		T4	2
valid_sources[0x0b]	367112	1			T2	1242		T3	49		T4	3
valid_sources[0x0c]	323064	1			T2	1245		T3	41		T4	7
valid_sources[0x0d]	325862	1			T2	1099		T3	58		T4	2
valid_sources[0x0e]	328490	1			T2	1186		T3	48		T17	1125
valid_sources[0x0f]	320390	1			T2	1134		T3	37		T4	3
valid_sources[0x10]	317867	1			T2	1220		T3	36		T4	2
valid_sources[0x11]	329818	1			T2	1119		T3	46		T4	2
valid_sources[0x12]	396131	1			T2	1217		T3	72		T4	2
valid_sources[0x13]	326774	1			T2	1230		T3	54		T4	1
valid_sources[0x14]	318695	1			T2	1107		T3	67		T4	7
valid_sources[0x15]	315106	1			T2	1298		T3	57		T4	9
valid_sources[0x16]	320170	1			T2	1073		T3	47		T4	2
valid_sources[0x17]	308301	1			T2	1194		T3	58		T4	6
valid_sources[0x18]	333362	1			T2	1249		T3	39		T4	4
valid_sources[0x19]	308126	1			T2	1101		T3	53		T4	4
valid_sources[0x1a]	317403	1			T2	1174		T3	38		T4	2
valid_sources[0x1b]	316903	1			T2	1350		T3	55		T4	2
valid_sources[0x1c]	311979	1			T2	1231		T3	64		T4	4
valid_sources[0x1d]	321909	1			T2	1152		T3	65		T4	5
valid_sources[0x1e]	319307	1			T2	1316		T3	54		T4	2
valid_sources[0x1f]	485192	1			T2	1247		T3	57		T4	3
valid_sources[0x20]	332812	1			T2	1176		T3	42		T4	1
valid_sources[0x21]	313985	1			T2	1250		T3	42		T4	1
valid_sources[0x22]	317761	1			T2	1174		T3	74		T4	3
valid_sources[0x23]	320913	1			T2	1201		T3	49		T4	5
valid_sources[0x24]	983482	1			T2	1308		T3	60		T4	6
valid_sources[0x25]	328996	1			T2	1303		T3	37		T4	2
valid_sources[0x26]	328795	1			T2	1279		T3	37		T17	1121
valid_sources[0x27]	329655	1			T2	1140		T3	84		T4	2
valid_sources[0x28]	318467	1			T2	1335		T3	74		T17	1064
valid_sources[0x29]	327869	1			T2	1222		T3	53		T4	3
valid_sources[0x2a]	327907	1			T2	1210		T3	33		T4	2
valid_sources[0x2b]	636943	1			T2	1078		T3	63		T4	3
valid_sources[0x2c]	327004	1			T2	1129		T3	53		T4	6
valid_sources[0x2d]	794102	1			T2	1274		T3	55		T4	2
valid_sources[0x2e]	328424	1			T2	1170		T3	38		T4	1
valid_sources[0x2f]	323389	1			T2	1186		T3	48		T4	1
valid_sources[0x30]	320528	1			T2	1300		T3	58		T4	2
valid_sources[0x31]	327884	1			T2	1451		T3	38		T4	4
valid_sources[0x32]	797987	1			T2	1279		T3	46		T4	2
valid_sources[0x33]	1050930	1			T2	1120		T3	40		T4	1
valid_sources[0x34]	332786	1			T2	1114		T3	58		T4	4
valid_sources[0x35]	343066	1			T2	1119		T3	38		T4	2
valid_sources[0x36]	311627	1			T2	1162		T3	38		T4	3
valid_sources[0x37]	544516	1			T2	1343		T3	46		T4	2
valid_sources[0x38]	331103	1			T2	1119		T3	50		T4	5
valid_sources[0x39]	332201	1			T2	1154		T3	33		T4	3
valid_sources[0x3a]	339025	1			T2	1305		T3	55		T17	1104
valid_sources[0x3b]	319697	1			T2	1255		T3	44		T4	2
valid_sources[0x3c]	314306	1			T2	1197		T3	39		T4	3
valid_sources[0x3d]	327169	1			T2	1275		T3	27		T4	2
valid_sources[0x3e]	1243697	1			T2	1172		T3	56		T4	3
valid_sources[0x3f]	314997	1			T2	1112		T3	23		T4	3
valid_sources[0x40]	326443	1			T2	1141		T3	50		T4	3
valid_sources[0x41]	325018	1			T2	1101		T3	45		T4	3
valid_sources[0x42]	326093	1			T2	1240		T3	38		T4	1
valid_sources[0x43]	318700	1			T2	1255		T3	54		T4	5
valid_sources[0x44]	317381	1			T2	1126		T3	52		T4	2
valid_sources[0x45]	316406	1			T2	1138		T3	56		T4	7
valid_sources[0x46]	324169	1			T2	1194		T3	65		T4	5
valid_sources[0x47]	309189	1			T2	1231		T3	56		T4	3
valid_sources[0x48]	326283	1			T2	1250		T3	50		T4	6
valid_sources[0x49]	721585	1			T2	1358		T3	43		T4	2
valid_sources[0x4a]	324751	1			T2	1264		T3	57		T17	1124
valid_sources[0x4b]	313975	1			T2	1148		T3	54		T17	1064
valid_sources[0x4c]	1117082	1			T2	1145		T3	56		T4	5
valid_sources[0x4d]	751539	1			T2	1034		T3	86		T4	5
valid_sources[0x4e]	314523	1			T2	1188		T3	46		T4	3
valid_sources[0x4f]	312017	1			T2	1209		T3	49		T4	7
valid_sources[0x50]	323608	1			T2	1193		T3	43		T4	3
valid_sources[0x51]	322376	1			T2	1011		T3	44		T4	3
valid_sources[0x52]	320219	1			T2	1299		T3	49		T4	6
valid_sources[0x53]	354259	1			T2	1295		T3	60		T4	2
valid_sources[0x54]	330904	1			T2	1185		T3	45		T4	2
valid_sources[0x55]	318409	1			T2	1238		T3	52		T4	2
valid_sources[0x56]	1098216	1			T2	1298		T3	46		T4	3
valid_sources[0x57]	322223	1			T2	952		T3	59		T4	6
valid_sources[0x58]	322825	1			T2	1182		T3	46		T4	1
valid_sources[0x59]	322770	1			T2	1242		T3	73		T4	4
valid_sources[0x5a]	322846	1			T2	1313		T3	38		T4	1
valid_sources[0x5b]	319180	1			T2	1251		T3	45		T4	1
valid_sources[0x5c]	318372	1			T2	1146		T3	46		T4	3
valid_sources[0x5d]	340207	1			T2	1032		T3	37		T4	2
valid_sources[0x5e]	327482	1			T2	1153		T3	49		T4	4
valid_sources[0x5f]	327060	1			T2	1395		T3	45		T4	2
valid_sources[0x60]	319553	1			T2	1122		T3	67		T17	1104
valid_sources[0x61]	316567	1			T2	1209		T3	60		T4	2
valid_sources[0x62]	589343	1			T2	1230		T3	45		T4	2
valid_sources[0x63]	311365	1			T2	1117		T3	56		T4	4
valid_sources[0x64]	320171	1			T2	1301		T3	46		T4	1
valid_sources[0x65]	960247	1			T2	1105		T3	66		T4	3
valid_sources[0x66]	316421	1			T2	1135		T3	30		T17	1072
valid_sources[0x67]	367002	1			T2	1225		T3	42		T4	6
valid_sources[0x68]	326216	1			T2	1289		T3	50		T4	4
valid_sources[0x69]	692332	1			T2	1232		T3	46		T4	1
valid_sources[0x6a]	310475	1			T2	1272		T3	38		T4	1
valid_sources[0x6b]	698510	1			T2	1248		T3	41		T4	3
valid_sources[0x6c]	322129	1			T2	1163		T3	59		T4	1
valid_sources[0x6d]	331508	1			T2	1108		T3	40		T4	1
valid_sources[0x6e]	593697	1			T2	1128		T3	57		T4	3
valid_sources[0x6f]	564098	1			T2	1260		T3	59		T4	1
valid_sources[0x70]	318710	1			T2	1054		T3	32		T4	4
valid_sources[0x71]	324758	1			T2	1204		T3	53		T4	3
valid_sources[0x72]	331312	1			T2	1182		T3	68		T4	3
valid_sources[0x73]	318990	1			T2	1017		T3	52		T4	1
valid_sources[0x74]	576258	1			T2	1085		T3	50		T4	3
valid_sources[0x75]	312717	1			T2	1162		T3	64		T4	3
valid_sources[0x76]	329977	1			T2	1311		T3	61		T4	1
valid_sources[0x77]	333382	1			T2	1263		T3	49		T4	4
valid_sources[0x78]	328131	1			T2	1179		T3	45		T4	2
valid_sources[0x79]	331560	1			T2	1292		T3	56		T4	2
valid_sources[0x7a]	329380	1			T2	1112		T3	61		T4	2
valid_sources[0x7b]	317517	1			T2	1225		T3	26		T4	2
valid_sources[0x7c]	316637	1			T2	1161		T3	58		T4	1
valid_sources[0x7d]	318842	1			T2	1102		T3	53		T4	4
valid_sources[0x7e]	363741	1			T2	1139		T3	60		T4	6
valid_sources[0x7f]	316748	1			T2	1279		T3	52		T4	4
valid_sources[0x80]	320432	1			T2	1188		T3	80		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7696328

1

T1

413

T2

18980

T3

774

values[0x0]

all_enables

biggest_size

16189830

1

T1

1065

T2

49414

T3

2120

values[0x1]

all_enables

biggest_size

9521920

1

T1

640

T2

27951

T3

1225