Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T195,T196
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14423	0	0
DisabledNoTrigBkwd_A	2147483647	784071	0	0
DisabledNoTrigFwd_A	2147483647	1572963113	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14423	0	0
T40	190134	0	0	0
T46	51053	0	0	0
T73	331479	0	0	0
T84	3538	623	0	0
T85	186248	0	0	0
T86	440080	0	0	0
T87	374730	0	0	0
T88	30811	0	0	0
T89	924181	0	0	0
T90	366826	0	0	0
T94	301339	0	0	0
T110	23485	0	0	0
T194	3893	884	0	0
T195	0	244	0	0
T196	0	486	0	0
T197	1143	410	0	0
T198	0	657	0	0
T199	0	895	0	0
T200	0	761	0	0
T201	0	393	0	0
T202	0	330	0	0
T203	0	742	0	0
T204	0	1165	0	0
T205	0	445	0	0
T206	0	1173	0	0
T207	0	2262	0	0
T208	0	618	0	0
T209	0	596	0	0
T210	0	111	0	0
T211	0	355	0	0
T212	0	1273	0	0
T213	51406	0	0	0
T214	157878	0	0	0
T215	10670	0	0	0
T216	413478	0	0	0
T217	141437	0	0	0
T218	37335	0	0	0
T219	814452	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	784071	0	0
T2	420189	544	0	0
T3	342663	16	0	0
T4	81816	0	0	0
T5	13888	6	0	0
T6	558708	727	0	0
T7	842000	17	0	0
T8	738444	452	0	0
T9	0	10	0	0
T13	414665	0	0	0
T14	426328	1576	0	0
T15	0	10	0	0
T16	0	721	0	0
T17	1602988	1802	0	0
T18	139288	8	0	0
T19	1400144	2812	0	0
T20	0	52	0	0
T21	0	1479	0	0
T23	0	2101	0	0
T25	0	1530	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T34	0	209	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1572963113	0	0
T1	67604	38228	0	0
T2	560252	419704	0	0
T3	456884	230200	0	0
T4	81816	31104	0	0
T5	13888	6326	0	0
T6	558708	284462	0	0
T7	842000	622862	0	0
T17	1602988	1564513	0	0
T18	139288	106366	0	0
T19	1400144	1001543	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T84,T200,T201
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696304396	2107	0	0
DisabledNoTrigBkwd_A	696304396	222076	0	0
DisabledNoTrigFwd_A	696304396	370259385	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	2107	0	0
T40	190134	0	0	0
T73	331479	0	0	0
T84	3538	623	0	0
T85	186248	0	0	0
T86	440080	0	0	0
T87	374730	0	0	0
T88	30811	0	0	0
T89	924181	0	0	0
T90	366826	0	0	0
T200	0	761	0	0
T201	0	393	0	0
T202	0	330	0	0
T213	51406	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	222076	0	0
T2	140063	2	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	4	0	0
T6	139677	727	0	0
T7	210500	10	0	0
T8	184611	0	0	0
T15	0	10	0	0
T17	400747	434	0	0
T18	34822	8	0	0
T19	350036	2661	0	0
T31	0	1	0	0
T32	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	370259385	0	0
T1	16901	2871	0	0
T2	140063	138355	0	0
T3	114221	105449	0	0
T4	20454	7776	0	0
T5	3472	582	0	0
T6	139677	3318	0	0
T7	210500	198274	0	0
T17	400747	139774	0	0
T18	34822	2086	0	0
T19	350036	17131	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T2,T5,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T198,T199
1	1	Covered	T2,T5,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T17,T9

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696304396	8190	0	0
DisabledNoTrigBkwd_A	696304396	163694	0	0
DisabledNoTrigFwd_A	696304396	400505284	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	8190	0	0
T46	51053	0	0	0
T94	301339	0	0	0
T110	23485	0	0	0
T197	1143	410	0	0
T198	0	657	0	0
T199	0	895	0	0
T204	0	1165	0	0
T206	0	1173	0	0
T207	0	2262	0	0
T211	0	355	0	0
T212	0	1273	0	0
T214	157878	0	0	0
T215	10670	0	0	0
T216	413478	0	0	0
T217	141437	0	0	0
T218	37335	0	0	0
T219	814452	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	163694	0	0
T4	20454	0	0	0
T5	3472	2	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T9	0	6	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T16	0	499	0	0
T17	400747	719	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	52	0	0
T21	0	1479	0	0
T23	0	2101	0	0
T25	0	1530	0	0
T33	0	2	0	0
T34	0	209	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	400505284	0	0
T1	16901	16824	0	0
T2	140063	138591	0	0
T3	114221	5514	0	0
T4	20454	7776	0	0
T5	3472	1745	0	0
T6	139677	139350	0	0
T7	210500	210483	0	0
T17	400747	619272	0	0
T18	34822	34760	0	0
T19	350036	347766	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T196
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696304396	1370	0	0
DisabledNoTrigBkwd_A	696304396	199095	0	0
DisabledNoTrigFwd_A	696304396	378947528	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1370	0	0
T24	531313	0	0	0
T26	116592	0	0	0
T35	101308	0	0	0
T59	78880	0	0	0
T60	43026	0	0	0
T61	30018	0	0	0
T62	5593	0	0	0
T63	8697	0	0	0
T64	338538	0	0	0
T194	3893	884	0	0
T196	0	486	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	199095	0	0
T2	140063	542	0	0
T3	114221	16	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	7	0	0
T8	184611	452	0	0
T9	0	4	0	0
T14	0	1576	0	0
T16	0	222	0	0
T17	400747	649	0	0
T18	34822	0	0	0
T19	350036	151	0	0
T33	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	378947528	0	0
T1	16901	1709	0	0
T2	140063	3280	0	0
T3	114221	5518	0	0
T4	20454	7776	0	0
T5	3472	590	0	0
T6	139677	2397	0	0
T7	210500	209962	0	0
T17	400747	542019	0	0
T18	34822	34760	0	0
T19	350036	286634	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195,T203,T205
1	1	Covered	T2,T3,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T17,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	696304396	2756	0	0
DisabledNoTrigBkwd_A	696304396	199206	0	0
DisabledNoTrigFwd_A	696304396	423250916	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	2756	0	0
T69	863707	0	0	0
T93	234605	0	0	0
T195	1007	244	0	0
T203	0	742	0	0
T205	0	445	0	0
T208	0	618	0	0
T209	0	596	0	0
T210	0	111	0	0
T220	2914	0	0	0
T221	75974	0	0	0
T222	573453	0	0	0
T223	165372	0	0	0
T224	39546	0	0	0
T225	177565	0	0	0
T226	70038	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	199206	0	0
T2	140063	2	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	1217	0	0
T8	184611	0	0	0
T9	0	1	0	0
T14	0	1648	0	0
T15	0	2096	0	0
T16	0	591	0	0
T17	400747	398	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	1427	0	0
T23	0	2348	0	0
T54	0	22	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	423250916	0	0
T1	16901	16824	0	0
T2	140063	139478	0	0
T3	114221	113719	0	0
T4	20454	7776	0	0
T5	3472	3409	0	0
T6	139677	139397	0	0
T7	210500	4143	0	0
T17	400747	263448	0	0
T18	34822	34760	0	0
T19	350036	350012	0	0