Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T18
1	0	1	Covered	T2,T3,T17
1	1	0	Covered	T1,T5,T7
1	1	1	Covered	T1,T5,T7

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T7
0	1	Covered	T20,T21,T22
1	0	Covered	T5,T23,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T7
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T23,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Not Covered
1	1	Covered	T20,T21,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T2,T5,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T18,T7

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T17
1	Covered	T2,T3,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T17,T6,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T5,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T5,T17

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T5
Phase1St	198	Covered	T2,T3,T5
Phase2St	215	Covered	T2,T3,T5
Phase3St	233	Covered	T2,T3,T5
TerminalSt	249	Covered	T2,T3,T5
TimeoutSt	159	Covered	T1,T5,T7

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T4,T11,T12
IdleSt->Phase0St	152	Covered	T2,T3,T5
IdleSt->TimeoutSt	159	Covered	T1,T5,T7
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T16,T23,T25
Phase0St->Phase1St	198	Covered	T2,T3,T5
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T23,T25,T24
Phase1St->Phase2St	215	Covered	T2,T3,T5
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T15,T23,T20
Phase2St->Phase3St	233	Covered	T2,T3,T5
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T16,T24,T26
Phase3St->TerminalSt	249	Covered	T2,T3,T5
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T5,T17
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T5,T7
TimeoutSt->Phase0St	172	Covered	T23,T20,T21

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T23,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T16,T23,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T25,T24
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T23,T20
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T24,T26
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	842	0	0
CheckAccumTrig0_A	2147483647	2289	0	0
CheckAccumTrig1_A	2147483647	116	0	0
CheckClr_A	2147483647	1026	0	0
CheckEn_A	2147483647	1199875888	0	0
CheckPhase0_A	2147483647	2558	0	0
CheckPhase1_A	2147483647	2509	0	0
CheckPhase2_A	2147483647	2471	0	0
CheckPhase3_A	2147483647	2435	0	0
CheckTimeout0_A	2147483647	6691	0	0
CheckTimeoutSt1_A	2147483647	550625	0	0
CheckTimeoutSt2_A	2147483647	6384	0	0
CheckTimeoutStTrig_A	2147483647	188	0	0
ErrorStAllEscAsserted_A	2147483647	4285	0	0
ErrorStIsTerminal_A	2147483647	3565	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	842	0	0
T4	81816	121	0	0
T6	558708	0	0	0
T7	842000	0	0	0
T8	738444	0	0	0
T11	0	136	0	0
T12	0	321	0	0
T13	1658660	0	0	0
T14	1705312	0	0	0
T17	1602988	0	0	0
T18	139288	0	0	0
T19	1400144	0	0	0
T28	0	135	0	0
T29	0	129	0	0
T30	108768	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2289	0	0
T2	420189	3	0	0
T3	342663	1	0	0
T4	81816	0	0	0
T5	13888	2	0	0
T6	558708	1	0	0
T7	842000	2	0	0
T8	738444	1	0	0
T9	0	2	0	0
T13	414665	0	0	0
T14	426328	1	0	0
T15	0	1	0	0
T16	0	6	0	0
T17	1602988	11	0	0
T18	139288	1	0	0
T19	1400144	4	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	11	0	0
T25	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	116	0	0
T20	340353	0	0	0
T21	543292	0	0	0
T23	445433	1	0	0
T24	1593939	7	0	0
T25	295258	0	0	0
T26	349776	0	0	0
T27	389544	0	0	0
T34	153265	0	0	0
T35	303924	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	97049	0	0	0
T55	19357	0	0	0
T56	804009	0	0	0
T57	315470	0	0	0
T58	16182	0	0	0
T59	236640	0	0	0
T60	129078	0	0	0
T61	90054	0	0	0
T62	16779	0	0	0
T63	26091	0	0	0
T64	1015614	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1026	0	0
T2	140063	1	0	0
T3	114221	0	0	0
T4	40908	0	0	0
T5	6944	1	0	0
T6	558708	0	0	0
T7	842000	0	0	0
T8	738444	0	0	0
T13	1243995	0	0	0
T14	1278984	0	0	0
T15	0	1	0	0
T16	0	13	0	0
T17	1602988	1	0	0
T18	139288	0	0	0
T19	1400144	0	0	0
T20	0	7	0	0
T21	0	5	0	0
T23	0	15	0	0
T24	0	15	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0
T30	54384	0	0	0
T31	42840	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T56	0	1	0	0
T58	0	4	0	0
T64	0	1	0	0
T65	0	5	0	0
T66	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1199875888	0	0
T1	67604	38226	0	0
T2	560252	151403	0	0
T3	456884	230200	0	0
T4	1248	1020	0	0
T5	13888	6324	0	0
T6	558708	284461	0	0
T7	842000	539079	0	0
T17	1602988	1562885	0	0
T18	139288	106363	0	0
T19	1400144	1001543	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2558	0	0
T2	420189	3	0	0
T3	342663	1	0	0
T4	81816	0	0	0
T5	13888	2	0	0
T6	558708	1	0	0
T7	842000	2	0	0
T8	738444	1	0	0
T9	0	2	0	0
T13	414665	0	0	0
T14	426328	1	0	0
T15	0	1	0	0
T16	0	6	0	0
T17	1602988	11	0	0
T18	139288	1	0	0
T19	1400144	4	0	0
T20	0	2	0	0
T21	0	3	0	0
T23	0	10	0	0
T25	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2509	0	0
T2	420189	3	0	0
T3	342663	1	0	0
T4	81816	0	0	0
T5	13888	2	0	0
T6	558708	1	0	0
T7	842000	2	0	0
T8	738444	1	0	0
T9	0	2	0	0
T13	414665	0	0	0
T14	426328	1	0	0
T15	0	1	0	0
T16	0	6	0	0
T17	1602988	11	0	0
T18	139288	1	0	0
T19	1400144	4	0	0
T20	0	2	0	0
T21	0	3	0	0
T23	0	9	0	0
T25	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2471	0	0
T2	420189	4	0	0
T3	342663	1	0	0
T4	81816	0	0	0
T5	13888	2	0	0
T6	558708	1	0	0
T7	842000	4	0	0
T8	738444	1	0	0
T9	0	3	0	0
T13	414665	0	0	0
T14	426328	2	0	0
T15	0	1	0	0
T16	0	27	0	0
T17	1602988	17	0	0
T18	139288	1	0	0
T19	1400144	4	0	0
T20	0	5	0	0
T21	0	3	0	0
T23	0	11	0	0
T25	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2435	0	0
T2	420189	4	0	0
T3	342663	1	0	0
T4	81816	0	0	0
T5	13888	2	0	0
T6	558708	1	0	0
T7	842000	4	0	0
T8	738444	1	0	0
T9	0	3	0	0
T13	414665	0	0	0
T14	426328	2	0	0
T15	0	1	0	0
T16	0	26	0	0
T17	1602988	17	0	0
T18	139288	1	0	0
T19	1400144	4	0	0
T20	0	5	0	0
T21	0	3	0	0
T23	0	11	0	0
T25	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6691	0	0
T1	33802	8	0	0
T2	280126	0	0	0
T3	228442	0	0	0
T4	40908	0	0	0
T5	6944	1	0	0
T6	279354	0	0	0
T7	631500	1	0	0
T8	184611	0	0	0
T9	1268920	0	0	0
T10	687499	0	0	0
T15	220966	0	0	0
T16	642031	13	0	0
T17	801494	0	0	0
T18	69644	0	0	0
T19	1050108	53	0	0
T20	0	21	0	0
T21	0	9	0	0
T22	0	9	0	0
T23	0	10	0	0
T24	0	3	0	0
T25	0	1	0	0
T26	0	36	0	0
T30	54384	7	0	0
T31	42840	0	0	0
T32	18216	0	0	0
T33	12599	2	0	0
T56	0	1	0	0
T61	0	12	0	0
T67	74798	11	0	0
T68	55710	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	550625	0	0
T1	33802	1307	0	0
T2	280126	0	0	0
T3	228442	0	0	0
T4	40908	0	0	0
T5	6944	105	0	0
T6	279354	0	0	0
T7	631500	184	0	0
T8	184611	0	0	0
T9	1268920	0	0	0
T10	687499	0	0	0
T15	220966	0	0	0
T16	642031	896	0	0
T17	801494	0	0	0
T18	69644	0	0	0
T19	1050108	3256	0	0
T20	0	3728	0	0
T21	0	1905	0	0
T22	0	2219	0	0
T23	0	592	0	0
T24	0	10	0	0
T25	0	190	0	0
T26	0	1614	0	0
T30	54384	1358	0	0
T31	42840	0	0	0
T32	18216	0	0	0
T33	12599	383	0	0
T56	0	84	0	0
T61	0	1096	0	0
T67	74798	2200	0	0
T68	55710	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6384	0	0
T1	33802	8	0	0
T2	280126	0	0	0
T3	228442	0	0	0
T4	40908	0	0	0
T5	6944	1	0	0
T6	279354	0	0	0
T7	631500	1	0	0
T8	184611	0	0	0
T9	1268920	0	0	0
T10	687499	0	0	0
T15	220966	0	0	0
T16	642031	13	0	0
T17	801494	0	0	0
T18	69644	0	0	0
T19	1050108	53	0	0
T20	0	19	0	0
T21	0	5	0	0
T22	0	8	0	0
T23	0	9	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	35	0	0
T30	54384	7	0	0
T31	42840	0	0	0
T32	18216	0	0	0
T33	12599	2	0	0
T35	0	2	0	0
T56	0	1	0	0
T61	0	12	0	0
T63	0	4	0	0
T67	74798	11	0	0
T68	55710	0	0	0
T69	0	327	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	188	0	0
T20	340353	1	0	0
T21	1086584	4	0	0
T22	0	1	0	0
T25	295258	0	0	0
T34	306530	0	0	0
T40	190134	1	0	0
T43	0	2	0	0
T47	0	1	0	0
T50	0	2	0	0
T54	97049	0	0	0
T55	38714	0	0	0
T56	1608018	0	0	0
T57	630940	0	0	0
T58	32364	0	0	0
T65	171878	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	301378	3	0	0
T73	331479	5	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	4	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	285953	0	0	0
T84	3538	0	0	0
T85	186248	0	0	0
T86	440080	0	0	0
T87	374730	0	0	0
T88	30811	0	0	0
T89	924181	0	0	0
T90	366826	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4285	0	0
T4	81816	681	0	0
T6	558708	0	0	0
T7	842000	0	0	0
T8	738444	0	0	0
T11	0	691	0	0
T12	0	1459	0	0
T13	1658660	0	0	0
T14	1705312	0	0	0
T17	1602988	0	0	0
T18	139288	0	0	0
T19	1400144	0	0	0
T28	0	689	0	0
T29	0	765	0	0
T30	108768	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3565	0	0
T4	81816	561	0	0
T6	558708	0	0	0
T7	842000	0	0	0
T8	738444	0	0	0
T11	0	571	0	0
T12	0	1219	0	0
T13	1658660	0	0	0
T14	1705312	0	0	0
T17	1602988	0	0	0
T18	139288	0	0	0
T19	1400144	0	0	0
T28	0	569	0	0
T29	0	645	0	0
T30	108768	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	67604	67296	0	0
T2	560252	560232	0	0
T3	456884	456844	0	0
T4	252	28	0	0
T5	13888	13636	0	0
T6	558708	558672	0	0
T7	842000	841932	0	0
T17	1602988	1602956	0	0
T18	139288	139040	0	0
T19	1400144	1400048	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	67604	67296	0	0
T2	560252	560232	0	0
T3	456884	456844	0	0
T4	81816	31104	0	0
T5	13888	13636	0	0
T6	558708	558672	0	0
T7	842000	841932	0	0
T17	1602988	1602956	0	0
T18	139288	139040	0	0
T19	1400144	1400048	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T12
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T18
1	0	1	Covered	T3,T17,T7
1	1	0	Covered	T1,T7,T16
1	1	1	Covered	T1,T19,T30

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T30
0	1	Covered	T72,T73,T77
1	0	Covered	T24,T36,T37

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T30
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T24,T36,T37

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T30
1	0	Not Covered
1	1	Covered	T72,T73,T77

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T17,T18
1	Covered	T5,T17,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T17
1	Covered	T2,T18,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T17
1	Covered	T2,T7,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T17
1	Covered	T17,T6,T31

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T5,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T17,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T5,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T5,T17,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T5,T17
Phase1St	198	Covered	T2,T5,T17
Phase2St	215	Covered	T2,T5,T17
Phase3St	233	Covered	T2,T5,T17
TerminalSt	249	Covered	T2,T5,T17
TimeoutSt	159	Covered	T1,T19,T30

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T11,T12
IdleSt->Phase0St	152	Covered	T2,T5,T17
IdleSt->TimeoutSt	159	Covered	T1,T19,T30
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T16,T25,T91
Phase0St->Phase1St	198	Covered	T2,T5,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T25,T24,T26
Phase1St->Phase2St	215	Covered	T2,T5,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T15,T24,T35
Phase2St->Phase3St	233	Covered	T2,T5,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T16,T26,T92
Phase3St->TerminalSt	249	Covered	T2,T5,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T17,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T19,T30
TimeoutSt->Phase0St	172	Covered	T24,T36,T37

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T30
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T36,T37
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T30
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T30
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T16,T91,T43
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T5,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T5,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T24,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T5,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T5,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T24,T35
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T5,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T5,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T26,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T5,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T5,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T31,T32
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T5,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696304396	185	0	0
CheckAccumTrig0_A	696304396	840	0	0
CheckAccumTrig1_A	696304396	47	0	0
CheckClr_A	696304396	392	0	0
CheckEn_A	696185672	267033213	0	0
CheckPhase0_A	696304396	913	0	0
CheckPhase1_A	696304396	892	0	0
CheckPhase2_A	696304396	874	0	0
CheckPhase3_A	696304396	863	0	0
CheckTimeout0_A	696304396	1921	0	0
CheckTimeoutSt1_A	696304396	174098	0	0
CheckTimeoutSt2_A	696304396	1831	0	0
CheckTimeoutStTrig_A	696304396	43	0	0
ErrorStAllEscAsserted_A	696304396	1048	0	0
ErrorStIsTerminal_A	696304396	868	0	0
EscStateOut_A	696184753	696115299	0	0
u_state_regs_A	696304396	696158922	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	185	0	0
T4	20454	27	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T11	0	47	0	0
T12	0	44	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T28	0	32	0	0
T29	0	35	0	0
T30	27192	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	840	0	0
T2	140063	2	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	1	0	0
T7	210500	1	0	0
T8	184611	0	0	0
T15	0	1	0	0
T17	400747	3	0	0
T18	34822	1	0	0
T19	350036	3	0	0
T31	0	1	0	0
T32	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	47	0	0
T24	531313	6	0	0
T26	116592	0	0	0
T27	129848	0	0	0
T35	101308	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	78880	0	0	0
T60	43026	0	0	0
T61	30018	0	0	0
T62	5593	0	0	0
T63	8697	0	0	0
T64	338538	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	392	0	0
T2	140063	1	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T15	0	1	0	0
T16	0	11	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T21	0	3	0	0
T23	0	1	0	0
T24	0	8	0	0
T25	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T65	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696185672	267033213	0	0
T1	16901	2871	0	0
T2	140063	8931	0	0
T3	114221	105449	0	0
T4	312	255	0	0
T5	3472	582	0	0
T6	139677	3318	0	0
T7	210500	198274	0	0
T17	400747	138151	0	0
T18	34822	2086	0	0
T19	350036	17131	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	913	0	0
T2	140063	2	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	1	0	0
T7	210500	1	0	0
T8	184611	0	0	0
T15	0	1	0	0
T17	400747	3	0	0
T18	34822	1	0	0
T19	350036	3	0	0
T31	0	1	0	0
T32	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	892	0	0
T2	140063	2	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	1	0	0
T7	210500	1	0	0
T8	184611	0	0	0
T15	0	1	0	0
T17	400747	3	0	0
T18	34822	1	0	0
T19	350036	3	0	0
T31	0	1	0	0
T32	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	874	0	0
T2	140063	2	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	1	0	0
T7	210500	1	0	0
T8	184611	0	0	0
T16	0	17	0	0
T17	400747	3	0	0
T18	34822	1	0	0
T19	350036	3	0	0
T31	0	1	0	0
T32	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	863	0	0
T2	140063	2	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	1	0	0
T7	210500	1	0	0
T8	184611	0	0	0
T16	0	16	0	0
T17	400747	3	0	0
T18	34822	1	0	0
T19	350036	3	0	0
T31	0	1	0	0
T32	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1921	0	0
T1	16901	3	0	0
T2	140063	0	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T16	0	4	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	26	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	2	0	0
T23	0	2	0	0
T25	0	1	0	0
T30	0	1	0	0
T67	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	174098	0	0
T1	16901	674	0	0
T2	140063	0	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T16	0	129	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	1712	0	0
T20	0	272	0	0
T21	0	31	0	0
T22	0	580	0	0
T23	0	192	0	0
T25	0	190	0	0
T30	0	216	0	0
T67	0	1191	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1831	0	0
T1	16901	3	0	0
T2	140063	0	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T16	0	4	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	26	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	2	0	0
T23	0	2	0	0
T25	0	1	0	0
T30	0	1	0	0
T67	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	43	0	0
T40	190134	0	0	0
T47	0	1	0	0
T50	0	2	0	0
T72	301378	2	0	0
T73	331479	2	0	0
T77	0	1	0	0
T78	0	3	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T84	3538	0	0	0
T85	186248	0	0	0
T86	440080	0	0	0
T87	374730	0	0	0
T88	30811	0	0	0
T89	924181	0	0	0
T90	366826	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1048	0	0
T4	20454	169	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T11	0	181	0	0
T12	0	345	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T28	0	157	0	0
T29	0	196	0	0
T30	27192	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	868	0	0
T4	20454	139	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T11	0	151	0	0
T12	0	285	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T28	0	127	0	0
T29	0	166	0	0
T30	27192	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696184753	696115299	0	0
T1	16901	16824	0	0
T2	140063	140058	0	0
T3	114221	114211	0	0
T4	63	7	0	0
T5	3472	3409	0	0
T6	139677	139668	0	0
T7	210500	210483	0	0
T17	400747	400739	0	0
T18	34822	34760	0	0
T19	350036	350012	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	696158922	0	0
T1	16901	16824	0	0
T2	140063	140058	0	0
T3	114221	114211	0	0
T4	20454	7776	0	0
T5	3472	3409	0	0
T6	139677	139668	0	0
T7	210500	210483	0	0
T17	400747	400739	0	0
T18	34822	34760	0	0
T19	350036	350012	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T12
1	0	Covered	T5,T17,T30
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T17,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T17,T30

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T17,T9

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T19,T30
1	0	1	Covered	T2,T17,T19
1	1	0	Covered	T1,T7,T19
1	1	1	Covered	T30,T16,T33

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T16,T33
0	1	Covered	T20,T21,T22
1	0	Covered	T24,T39,T46

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T30,T16,T33
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T24,T39,T46

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T30,T16,T33
1	0	Not Covered
1	1	Covered	T20,T21,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T9,T16
1	Covered	T5,T17,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T17,T16
1	Covered	T9,T23,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T17,T9
1	Covered	T17,T16,T23

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T17,T9
1	Covered	T16,T23,T25

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T17,T16,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T5,T17,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T17,T9,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T5,T17,T9

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T5,T17,T9
Phase1St	198	Covered	T5,T17,T9
Phase2St	215	Covered	T5,T17,T9
Phase3St	233	Covered	T5,T17,T9
TerminalSt	249	Covered	T5,T17,T9
TimeoutSt	159	Covered	T30,T16,T33

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T11,T12
IdleSt->Phase0St	152	Covered	T5,T17,T9
IdleSt->TimeoutSt	159	Covered	T30,T16,T33
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T23,T27,T50
Phase0St->Phase1St	198	Covered	T5,T17,T9
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T23,T93,T73
Phase1St->Phase2St	215	Covered	T5,T17,T9
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T66,T39,T76
Phase2St->Phase3St	233	Covered	T5,T17,T9
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T24,T40,T94
Phase3St->TerminalSt	249	Covered	T5,T17,T9
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T5,T17,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T30,T16,T33
TimeoutSt->Phase0St	172	Covered	T20,T21,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T17,T9
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T30,T16,T33
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T30,T16,T33
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T30,T16,T33
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T23,T27,T50
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T5,T17,T9
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T5,T17,T9
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T93,T95
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T5,T17,T9
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T5,T17,T9
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T66,T39,T76
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T5,T17,T9
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T5,T17,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T40,T94
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T5,T17,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T5,T17,T9
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T33,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T17,T9
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696304396	215	0	0
CheckAccumTrig0_A	696304396	504	0	0
CheckAccumTrig1_A	696304396	18	0	0
CheckClr_A	696304396	225	0	0
CheckEn_A	696185672	301839439	0	0
CheckPhase0_A	696304396	561	0	0
CheckPhase1_A	696304396	553	0	0
CheckPhase2_A	696304396	546	0	0
CheckPhase3_A	696304396	536	0	0
CheckTimeout0_A	696304396	1583	0	0
CheckTimeoutSt1_A	696304396	118418	0	0
CheckTimeoutSt2_A	696304396	1517	0	0
CheckTimeoutStTrig_A	696304396	48	0	0
ErrorStAllEscAsserted_A	696304396	1068	0	0
ErrorStIsTerminal_A	696304396	888	0	0
EscStateOut_A	696184753	696115299	0	0
u_state_regs_A	696304396	696158922	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	215	0	0
T4	20454	23	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T11	0	26	0	0
T12	0	86	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T28	0	36	0	0
T29	0	44	0	0
T30	27192	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	504	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T9	0	1	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T16	0	3	0	0
T17	400747	3	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	11	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	18	0	0
T24	531313	1	0	0
T26	116592	0	0	0
T27	129848	0	0	0
T35	101308	0	0	0
T39	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T59	78880	0	0	0
T60	43026	0	0	0
T61	30018	0	0	0
T62	5593	0	0	0
T63	8697	0	0	0
T64	338538	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	225	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T21	0	1	0	0
T23	0	8	0	0
T24	0	3	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T56	0	1	0	0
T58	0	3	0	0
T64	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696185672	301839439	0	0
T1	16901	16823	0	0
T2	140063	138591	0	0
T3	114221	5514	0	0
T4	312	255	0	0
T5	3472	1744	0	0
T6	139677	139350	0	0
T7	210500	210483	0	0
T17	400747	619269	0	0
T18	34822	34759	0	0
T19	350036	347766	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	561	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T9	0	1	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T16	0	3	0	0
T17	400747	3	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	2	0	0
T21	0	3	0	0
T23	0	10	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	553	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T9	0	1	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T16	0	3	0	0
T17	400747	3	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	2	0	0
T21	0	3	0	0
T23	0	9	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	546	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T9	0	1	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T16	0	3	0	0
T17	400747	3	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	2	0	0
T21	0	3	0	0
T23	0	9	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	536	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T9	0	1	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T16	0	3	0	0
T17	400747	3	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	2	0	0
T21	0	3	0	0
T23	0	9	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1583	0	0
T9	634460	0	0	0
T10	687499	0	0	0
T15	110483	0	0	0
T16	642031	7	0	0
T20	0	1	0	0
T21	0	3	0	0
T22	0	1	0	0
T23	0	4	0	0
T24	0	1	0	0
T26	0	32	0	0
T30	27192	4	0	0
T31	21420	0	0	0
T32	9108	0	0	0
T33	12599	1	0	0
T67	74798	5	0	0
T68	55710	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	118418	0	0
T9	634460	0	0	0
T10	687499	0	0	0
T15	110483	0	0	0
T16	642031	637	0	0
T20	0	225	0	0
T21	0	579	0	0
T22	0	214	0	0
T23	0	160	0	0
T24	0	3	0	0
T26	0	1433	0	0
T30	27192	769	0	0
T31	21420	0	0	0
T32	9108	0	0	0
T33	12599	125	0	0
T67	74798	1009	0	0
T68	55710	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1517	0	0
T9	634460	0	0	0
T10	687499	0	0	0
T15	110483	0	0	0
T16	642031	7	0	0
T21	0	1	0	0
T23	0	4	0	0
T26	0	32	0	0
T30	27192	4	0	0
T31	21420	0	0	0
T32	9108	0	0	0
T33	12599	1	0	0
T35	0	2	0	0
T63	0	4	0	0
T67	74798	5	0	0
T68	55710	0	0	0
T69	0	327	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	48	0	0
T20	340353	1	0	0
T21	543292	2	0	0
T22	0	1	0	0
T25	295258	0	0	0
T34	153265	0	0	0
T43	0	1	0	0
T54	97049	0	0	0
T55	19357	0	0	0
T56	804009	0	0	0
T57	315470	0	0	0
T58	16182	0	0	0
T65	85939	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1068	0	0
T4	20454	176	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T11	0	167	0	0
T12	0	389	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T28	0	170	0	0
T29	0	166	0	0
T30	27192	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	888	0	0
T4	20454	146	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T11	0	137	0	0
T12	0	329	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T28	0	140	0	0
T29	0	136	0	0
T30	27192	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696184753	696115299	0	0
T1	16901	16824	0	0
T2	140063	140058	0	0
T3	114221	114211	0	0
T4	63	7	0	0
T5	3472	3409	0	0
T6	139677	139668	0	0
T7	210500	210483	0	0
T17	400747	400739	0	0
T18	34822	34760	0	0
T19	350036	350012	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	696158922	0	0
T1	16901	16824	0	0
T2	140063	140058	0	0
T3	114221	114211	0	0
T4	20454	7776	0	0
T5	3472	3409	0	0
T6	139677	139668	0	0
T7	210500	210483	0	0
T17	400747	400739	0	0
T18	34822	34760	0	0
T19	350036	350012	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T7
1	0	1	Covered	T2,T17,T19
1	1	0	Covered	T16,T67,T23
1	1	1	Covered	T1,T5,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T19
0	1	Covered	T21,T72,T40
1	0	Covered	T5,T23,T35

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T5,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T23,T35

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Not Covered
1	1	Covered	T21,T72,T40

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T7
1	Covered	T2,T8,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T7,T16,T54

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T17,T7
1	Covered	T3,T17,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T17,T14,T9

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T17,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T17,T19,T8

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T17
Phase1St	198	Covered	T2,T3,T17
Phase2St	215	Covered	T2,T3,T17
Phase3St	233	Covered	T2,T3,T17
TerminalSt	249	Covered	T2,T3,T17
TimeoutSt	159	Covered	T1,T5,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T11,T12
IdleSt->Phase0St	152	Covered	T2,T3,T17
IdleSt->TimeoutSt	159	Covered	T1,T5,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T23,T96,T97
Phase0St->Phase1St	198	Covered	T2,T3,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T95,T98,T99
Phase1St->Phase2St	215	Covered	T2,T3,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T23,T20,T72
Phase2St->Phase3St	233	Covered	T2,T3,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T35,T100,T101
Phase3St->TerminalSt	249	Covered	T2,T3,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T17,T7,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T5,T19
TimeoutSt->Phase0St	172	Covered	T23,T21,T35

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T23,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T96,T102
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T95,T98,T99
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T20,T72
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T100,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T16,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696304396	220	0	0
CheckAccumTrig0_A	696304396	486	0	0
CheckAccumTrig1_A	696304396	21	0	0
CheckClr_A	696304396	215	0	0
CheckEn_A	696185672	312270379	0	0
CheckPhase0_A	696304396	553	0	0
CheckPhase1_A	696304396	542	0	0
CheckPhase2_A	696304396	534	0	0
CheckPhase3_A	696304396	525	0	0
CheckTimeout0_A	696304396	1693	0	0
CheckTimeoutSt1_A	696304396	131096	0	0
CheckTimeoutSt2_A	696304396	1621	0	0
CheckTimeoutStTrig_A	696304396	50	0	0
ErrorStAllEscAsserted_A	696304396	1099	0	0
ErrorStIsTerminal_A	696304396	919	0	0
EscStateOut_A	696184753	696115299	0	0
u_state_regs_A	696304396	696158922	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	220	0	0
T4	20454	36	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T11	0	40	0	0
T12	0	98	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T28	0	27	0	0
T29	0	19	0	0
T30	27192	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	486	0	0
T2	140063	1	0	0
T3	114221	1	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	1	0	0
T8	184611	1	0	0
T9	0	1	0	0
T14	0	1	0	0
T16	0	3	0	0
T17	400747	5	0	0
T18	34822	0	0	0
T19	350036	1	0	0
T33	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	21	0	0
T20	340353	0	0	0
T21	543292	0	0	0
T23	445433	1	0	0
T25	295258	0	0	0
T34	153265	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T54	97049	0	0	0
T55	19357	0	0	0
T56	804009	0	0	0
T57	315470	0	0	0
T58	16182	0	0	0
T72	0	1	0	0
T78	0	2	0	0
T97	0	2	0	0
T103	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	215	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T16	0	2	0	0
T17	400747	1	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	7	0	0
T21	0	1	0	0
T23	0	6	0	0
T24	0	4	0	0
T30	27192	0	0	0
T31	21420	0	0	0
T35	0	1	0	0
T58	0	1	0	0
T66	0	2	0	0
T69	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696185672	312270379	0	0
T1	16901	1709	0	0
T2	140063	3280	0	0
T3	114221	5518	0	0
T4	312	255	0	0
T5	3472	590	0	0
T6	139677	2397	0	0
T7	210500	126179	0	0
T17	400747	542017	0	0
T18	34822	34759	0	0
T19	350036	286634	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	553	0	0
T2	140063	1	0	0
T3	114221	1	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	1	0	0
T8	184611	1	0	0
T9	0	1	0	0
T14	0	1	0	0
T16	0	3	0	0
T17	400747	5	0	0
T18	34822	0	0	0
T19	350036	1	0	0
T33	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	542	0	0
T2	140063	1	0	0
T3	114221	1	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	1	0	0
T8	184611	1	0	0
T9	0	1	0	0
T14	0	1	0	0
T16	0	3	0	0
T17	400747	5	0	0
T18	34822	0	0	0
T19	350036	1	0	0
T33	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	534	0	0
T2	140063	1	0	0
T3	114221	1	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	1	0	0
T8	184611	1	0	0
T9	0	1	0	0
T14	0	1	0	0
T16	0	3	0	0
T17	400747	5	0	0
T18	34822	0	0	0
T19	350036	1	0	0
T33	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	525	0	0
T2	140063	1	0	0
T3	114221	1	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	1	0	0
T8	184611	1	0	0
T9	0	1	0	0
T14	0	1	0	0
T16	0	3	0	0
T17	400747	5	0	0
T18	34822	0	0	0
T19	350036	1	0	0
T33	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1693	0	0
T1	16901	5	0	0
T2	140063	0	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T16	0	1	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	27	0	0
T20	0	5	0	0
T21	0	4	0	0
T23	0	4	0	0
T26	0	2	0	0
T30	0	2	0	0
T61	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	131096	0	0
T1	16901	633	0	0
T2	140063	0	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	105	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T16	0	12	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	1544	0	0
T20	0	573	0	0
T21	0	1229	0	0
T23	0	240	0	0
T26	0	137	0	0
T30	0	373	0	0
T61	0	574	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1621	0	0
T1	16901	5	0	0
T2	140063	0	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	1	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T16	0	1	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	27	0	0
T20	0	5	0	0
T21	0	2	0	0
T23	0	3	0	0
T26	0	2	0	0
T30	0	2	0	0
T61	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	50	0	0
T21	543292	2	0	0
T22	58757	0	0	0
T34	153265	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T55	19357	0	0	0
T56	804009	0	0	0
T57	315470	0	0	0
T58	16182	0	0	0
T65	85939	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T83	285953	0	0	0
T104	513749	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1099	0	0
T4	20454	163	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T11	0	178	0	0
T12	0	388	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T28	0	179	0	0
T29	0	191	0	0
T30	27192	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	919	0	0
T4	20454	133	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T11	0	148	0	0
T12	0	328	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T28	0	149	0	0
T29	0	161	0	0
T30	27192	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696184753	696115299	0	0
T1	16901	16824	0	0
T2	140063	140058	0	0
T3	114221	114211	0	0
T4	63	7	0	0
T5	3472	3409	0	0
T6	139677	139668	0	0
T7	210500	210483	0	0
T17	400747	400739	0	0
T18	34822	34760	0	0
T19	350036	350012	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	696158922	0	0
T1	16901	16824	0	0
T2	140063	140058	0	0
T3	114221	114211	0	0
T4	20454	7776	0	0
T5	3472	3409	0	0
T6	139677	139668	0	0
T7	210500	210483	0	0
T17	400747	400739	0	0
T18	34822	34760	0	0
T19	350036	350012	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T17,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T17,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T17,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T31,T16
1	0	1	Covered	T3,T17,T7
1	1	0	Covered	T1,T5,T19
1	1	1	Covered	T7,T16,T33

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T16,T33
0	1	Covered	T20,T35,T69
1	0	Covered	T24,T26,T35

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T7,T16,T33
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T24,T26,T35

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T16,T33
1	0	Not Covered
1	1	Covered	T20,T35,T69

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T7,T14
1	Covered	T2,T17,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T17,T7
1	Covered	T7,T54,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T17,T7
1	Covered	T14,T9,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T17,T7
1	Covered	T17,T7,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T17,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T14,T9,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T17,T7,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T2,T17,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T17,T7
Phase1St	198	Covered	T2,T17,T7
Phase2St	215	Covered	T2,T17,T7
Phase3St	233	Covered	T2,T17,T7
TerminalSt	249	Covered	T2,T17,T7
TimeoutSt	159	Covered	T7,T16,T33

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T11,T12
IdleSt->Phase0St	152	Covered	T2,T17,T7
IdleSt->TimeoutSt	159	Covered	T7,T16,T33
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T43,T105,T106
Phase0St->Phase1St	198	Covered	T2,T17,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T69,T107,T108
Phase1St->Phase2St	215	Covered	T2,T17,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T14,T35,T74
Phase2St->Phase3St	233	Covered	T2,T17,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T83,T26,T109
Phase3St->TerminalSt	249	Covered	T2,T17,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T17,T7,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T7,T16,T33
TimeoutSt->Phase0St	172	Covered	T20,T24,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T17,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T16,T33
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T24,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T16,T33
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T7,T16,T33
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T43,T105,T106
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T17,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T17,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T69,T107,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T17,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T17,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T35,T74
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T17,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T17,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T83,T26,T109
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T17,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T17,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T20,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T17,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696304396	222	0	0
CheckAccumTrig0_A	696304396	459	0	0
CheckAccumTrig1_A	696304396	30	0	0
CheckClr_A	696304396	194	0	0
CheckEn_A	696185672	318732857	0	0
CheckPhase0_A	696304396	531	0	0
CheckPhase1_A	696304396	522	0	0
CheckPhase2_A	696304396	517	0	0
CheckPhase3_A	696304396	511	0	0
CheckTimeout0_A	696304396	1494	0	0
CheckTimeoutSt1_A	696304396	127013	0	0
CheckTimeoutSt2_A	696304396	1415	0	0
CheckTimeoutStTrig_A	696304396	47	0	0
ErrorStAllEscAsserted_A	696304396	1070	0	0
ErrorStIsTerminal_A	696304396	890	0	0
EscStateOut_A	696184753	696115299	0	0
u_state_regs_A	696304396	696158922	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	222	0	0
T4	20454	35	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T11	0	23	0	0
T12	0	93	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T28	0	40	0	0
T29	0	31	0	0
T30	27192	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	459	0	0
T2	140063	1	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	2	0	0
T8	184611	0	0	0
T9	0	1	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	4	0	0
T17	400747	6	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	2	0	0
T23	0	2	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	30	0	0
T24	531313	1	0	0
T26	116592	1	0	0
T27	129848	0	0	0
T35	101308	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T59	78880	0	0	0
T60	43026	0	0	0
T61	30018	0	0	0
T62	5593	0	0	0
T63	8697	0	0	0
T64	338538	0	0	0
T72	0	1	0	0
T94	0	2	0	0
T100	0	2	0	0
T105	0	1	0	0
T110	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	194	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T13	414665	0	0	0
T14	426328	1	0	0
T17	400747	3	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T24	0	4	0	0
T26	0	1	0	0
T30	27192	0	0	0
T31	21420	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T83	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696185672	318732857	0	0
T1	16901	16823	0	0
T2	140063	601	0	0
T3	114221	113719	0	0
T4	312	255	0	0
T5	3472	3408	0	0
T6	139677	139396	0	0
T7	210500	4143	0	0
T17	400747	263448	0	0
T18	34822	34759	0	0
T19	350036	350012	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	531	0	0
T2	140063	1	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	2	0	0
T8	184611	0	0	0
T9	0	1	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	4	0	0
T17	400747	6	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	3	0	0
T23	0	2	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	522	0	0
T2	140063	1	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	2	0	0
T8	184611	0	0	0
T9	0	1	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	4	0	0
T17	400747	6	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	3	0	0
T23	0	2	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	517	0	0
T2	140063	1	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	2	0	0
T8	184611	0	0	0
T9	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	4	0	0
T17	400747	6	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	3	0	0
T23	0	2	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	511	0	0
T2	140063	1	0	0
T3	114221	0	0	0
T4	20454	0	0	0
T5	3472	0	0	0
T6	139677	0	0	0
T7	210500	2	0	0
T8	184611	0	0	0
T9	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	4	0	0
T17	400747	6	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T20	0	3	0	0
T23	0	2	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1494	0	0
T7	210500	1	0	0
T8	184611	0	0	0
T9	634460	0	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T15	110483	0	0	0
T16	0	1	0	0
T19	350036	0	0	0
T20	0	13	0	0
T21	0	1	0	0
T22	0	6	0	0
T24	0	2	0	0
T26	0	2	0	0
T30	27192	0	0	0
T31	21420	0	0	0
T32	9108	0	0	0
T33	0	1	0	0
T56	0	1	0	0
T61	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	127013	0	0
T7	210500	184	0	0
T8	184611	0	0	0
T9	634460	0	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T15	110483	0	0	0
T16	0	118	0	0
T19	350036	0	0	0
T20	0	2658	0	0
T21	0	66	0	0
T22	0	1425	0	0
T24	0	7	0	0
T26	0	44	0	0
T30	27192	0	0	0
T31	21420	0	0	0
T32	9108	0	0	0
T33	0	258	0	0
T56	0	84	0	0
T61	0	522	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1415	0	0
T7	210500	1	0	0
T8	184611	0	0	0
T9	634460	0	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T15	110483	0	0	0
T16	0	1	0	0
T19	350036	0	0	0
T20	0	12	0	0
T21	0	1	0	0
T22	0	6	0	0
T24	0	1	0	0
T26	0	1	0	0
T30	27192	0	0	0
T31	21420	0	0	0
T32	9108	0	0	0
T33	0	1	0	0
T56	0	1	0	0
T61	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	47	0	0
T20	340353	1	0	0
T21	543292	0	0	0
T25	295258	0	0	0
T34	153265	0	0	0
T35	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	97049	0	0	0
T55	19357	0	0	0
T56	804009	0	0	0
T57	315470	0	0	0
T58	16182	0	0	0
T65	85939	0	0	0
T69	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	1070	0	0
T4	20454	173	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T11	0	165	0	0
T12	0	337	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T28	0	183	0	0
T29	0	212	0	0
T30	27192	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	890	0	0
T4	20454	143	0	0
T6	139677	0	0	0
T7	210500	0	0	0
T8	184611	0	0	0
T11	0	135	0	0
T12	0	277	0	0
T13	414665	0	0	0
T14	426328	0	0	0
T17	400747	0	0	0
T18	34822	0	0	0
T19	350036	0	0	0
T28	0	153	0	0
T29	0	182	0	0
T30	27192	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696184753	696115299	0	0
T1	16901	16824	0	0
T2	140063	140058	0	0
T3	114221	114211	0	0
T4	63	7	0	0
T5	3472	3409	0	0
T6	139677	139668	0	0
T7	210500	210483	0	0
T17	400747	400739	0	0
T18	34822	34760	0	0
T19	350036	350012	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696304396	696158922	0	0
T1	16901	16824	0	0
T2	140063	140058	0	0
T3	114221	114211	0	0
T4	20454	7776	0	0
T5	3472	3409	0	0
T6	139677	139668	0	0
T7	210500	210483	0	0
T17	400747	400739	0	0
T18	34822	34760	0	0
T19	350036	350012	0	0