Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66169424	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32070643

1

T1

100669

T2

884

T3

3612

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14936797	1			T1	39723		T2	443		T3	1501
values[0x0]	40599306	1			T1	137416		T2	1113		T3	4953
values[0x1]	42703964	1			T1	139342		T2	1057		T3	4941

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56465707	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41774360

1

T1

127191

T2

1102

T3

4589

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	307538	1			T1	1222		T2	2		T3	70
valid_sources[0x01]	311972	1			T1	1114		T2	16		T3	58
valid_sources[0x02]	305882	1			T1	1104		T2	10		T3	27
valid_sources[0x03]	314496	1			T1	1361		T3	53		T5	24
valid_sources[0x04]	316732	1			T1	1004		T2	31		T3	14
valid_sources[0x05]	320460	1			T1	1326		T3	50		T5	33
valid_sources[0x06]	324767	1			T1	1432		T2	27		T3	86
valid_sources[0x07]	308247	1			T1	1305		T2	4		T3	52
valid_sources[0x08]	311755	1			T1	1315		T3	49		T5	41
valid_sources[0x09]	317932	1			T1	1289		T2	17		T3	34
valid_sources[0x0a]	311355	1			T1	1193		T2	7		T3	47
valid_sources[0x0b]	309169	1			T1	1217		T2	2		T3	11
valid_sources[0x0c]	314951	1			T1	1202		T2	2		T3	22
valid_sources[0x0d]	545110	1			T1	1241		T3	27		T5	40
valid_sources[0x0e]	323210	1			T1	1164		T2	12		T3	68
valid_sources[0x0f]	664614	1			T1	1324		T3	31		T5	32
valid_sources[0x10]	1193687	1			T1	1178		T2	5		T3	48
valid_sources[0x11]	794766	1			T1	1160		T3	12		T5	37
valid_sources[0x12]	316138	1			T1	1320		T2	22		T3	40
valid_sources[0x13]	313105	1			T1	1218		T2	2		T3	55
valid_sources[0x14]	544938	1			T1	1258		T2	11		T3	35
valid_sources[0x15]	321750	1			T1	1214		T2	20		T3	33
valid_sources[0x16]	308085	1			T1	1156		T3	49		T5	41
valid_sources[0x17]	311349	1			T1	1228		T2	7		T3	36
valid_sources[0x18]	323675	1			T1	1355		T2	1		T3	60
valid_sources[0x19]	313194	1			T1	1161		T2	8		T3	80
valid_sources[0x1a]	311712	1			T1	1320		T2	46		T3	9
valid_sources[0x1b]	315665	1			T1	1382		T3	40		T5	27
valid_sources[0x1c]	307285	1			T1	1182		T3	46		T5	37
valid_sources[0x1d]	307189	1			T1	1291		T3	39		T5	42
valid_sources[0x1e]	318899	1			T1	1446		T2	10		T3	66
valid_sources[0x1f]	414507	1			T1	1283		T2	27		T3	37
valid_sources[0x20]	753665	1			T1	1167		T3	21		T5	37
valid_sources[0x21]	307516	1			T1	1071		T2	46		T3	57
valid_sources[0x22]	310207	1			T1	1203		T2	37		T3	66
valid_sources[0x23]	306827	1			T1	1164		T3	17		T5	16
valid_sources[0x24]	313084	1			T1	1123		T2	5		T3	60
valid_sources[0x25]	310616	1			T1	1113		T3	38		T5	32
valid_sources[0x26]	750202	1			T1	1149		T2	3		T3	30
valid_sources[0x27]	318574	1			T1	1474		T3	88		T5	21
valid_sources[0x28]	335961	1			T1	1280		T2	7		T3	30
valid_sources[0x29]	775850	1			T1	1345		T3	9		T5	47
valid_sources[0x2a]	314933	1			T1	1341		T2	21		T3	30
valid_sources[0x2b]	310470	1			T1	1238		T2	11		T3	45
valid_sources[0x2c]	316914	1			T1	1102		T2	6		T3	90
valid_sources[0x2d]	321803	1			T1	1367		T3	45		T5	40
valid_sources[0x2e]	636006	1			T1	1226		T3	16		T5	22
valid_sources[0x2f]	720979	1			T1	1305		T3	59		T5	30
valid_sources[0x30]	307577	1			T1	1202		T3	66		T5	33
valid_sources[0x31]	773535	1			T1	1303		T3	38		T5	28
valid_sources[0x32]	318917	1			T1	1357		T2	13		T3	44
valid_sources[0x33]	332786	1			T1	1270		T3	20		T5	68
valid_sources[0x34]	307156	1			T1	1263		T2	12		T3	15
valid_sources[0x35]	312289	1			T1	1138		T2	11		T3	66
valid_sources[0x36]	313833	1			T1	1143		T2	22		T3	72
valid_sources[0x37]	309445	1			T1	1151		T2	8		T3	73
valid_sources[0x38]	880192	1			T1	1195		T2	13		T3	65
valid_sources[0x39]	312889	1			T1	1147		T3	24		T5	26
valid_sources[0x3a]	314443	1			T1	1353		T2	13		T3	104
valid_sources[0x3b]	313412	1			T1	1133		T2	16		T3	80
valid_sources[0x3c]	314214	1			T1	1288		T2	11		T3	53
valid_sources[0x3d]	340096	1			T1	1273		T2	1		T3	49
valid_sources[0x3e]	311954	1			T1	1482		T3	45		T5	36
valid_sources[0x3f]	310777	1			T1	1250		T2	26		T3	42
valid_sources[0x40]	312500	1			T1	1374		T3	72		T5	21
valid_sources[0x41]	309930	1			T1	1253		T3	39		T5	31
valid_sources[0x42]	319241	1			T1	1239		T3	45		T5	27
valid_sources[0x43]	309830	1			T1	1331		T3	29		T5	23
valid_sources[0x44]	312158	1			T1	1154		T2	12		T3	65
valid_sources[0x45]	778723	1			T1	1486		T2	1		T3	46
valid_sources[0x46]	312635	1			T1	1113		T2	10		T3	70
valid_sources[0x47]	521206	1			T1	1213		T2	13		T3	35
valid_sources[0x48]	593157	1			T1	1127		T2	35		T3	46
valid_sources[0x49]	310472	1			T1	1316		T3	22		T5	16
valid_sources[0x4a]	310214	1			T1	1445		T2	10		T3	79
valid_sources[0x4b]	989174	1			T1	1250		T2	17		T3	48
valid_sources[0x4c]	317091	1			T1	1236		T2	4		T3	69
valid_sources[0x4d]	306639	1			T1	1138		T2	15		T3	38
valid_sources[0x4e]	604418	1			T1	1264		T2	5		T3	27
valid_sources[0x4f]	788715	1			T1	1213		T2	25		T3	12
valid_sources[0x50]	309987	1			T1	1191		T2	4		T3	32
valid_sources[0x51]	327595	1			T1	1158		T2	15		T3	45
valid_sources[0x52]	314972	1			T1	1203		T2	14		T3	54
valid_sources[0x53]	620019	1			T1	1052		T3	29		T5	37
valid_sources[0x54]	320061	1			T1	1282		T2	9		T3	12
valid_sources[0x55]	313256	1			T1	1204		T3	17		T5	30
valid_sources[0x56]	312468	1			T1	1277		T3	72		T5	24
valid_sources[0x57]	309805	1			T1	1030		T2	3		T3	37
valid_sources[0x58]	317257	1			T1	1393		T2	5		T3	12
valid_sources[0x59]	328787	1			T1	1193		T2	33		T3	42
valid_sources[0x5a]	306073	1			T1	1234		T2	5		T3	25
valid_sources[0x5b]	326730	1			T1	1192		T3	47		T5	48
valid_sources[0x5c]	312457	1			T1	1075		T2	4		T3	30
valid_sources[0x5d]	312458	1			T1	1283		T2	25		T3	51
valid_sources[0x5e]	1113558	1			T1	1361		T2	22		T3	72
valid_sources[0x5f]	312347	1			T1	1347		T2	8		T3	48
valid_sources[0x60]	313028	1			T1	1310		T2	2		T3	27
valid_sources[0x61]	351458	1			T1	1269		T3	69		T5	28
valid_sources[0x62]	688803	1			T1	1284		T2	9		T3	36
valid_sources[0x63]	313960	1			T1	1259		T3	33		T5	44
valid_sources[0x64]	314945	1			T1	1362		T2	14		T3	66
valid_sources[0x65]	306506	1			T1	1263		T3	70		T5	33
valid_sources[0x66]	306874	1			T1	1134		T3	24		T5	19
valid_sources[0x67]	312451	1			T1	1115		T3	32		T5	29
valid_sources[0x68]	330590	1			T1	1111		T3	75		T5	30
valid_sources[0x69]	308652	1			T1	1195		T2	22		T3	41
valid_sources[0x6a]	320595	1			T1	1287		T3	41		T5	19
valid_sources[0x6b]	307522	1			T1	1186		T2	11		T3	12
valid_sources[0x6c]	314812	1			T1	1332		T2	32		T3	54
valid_sources[0x6d]	773904	1			T1	1433		T3	21		T5	37
valid_sources[0x6e]	309770	1			T1	1250		T3	24		T5	56
valid_sources[0x6f]	322458	1			T1	981		T2	10		T3	17
valid_sources[0x70]	313715	1			T1	1335		T3	43		T5	39
valid_sources[0x71]	313061	1			T1	1311		T2	24		T3	45
valid_sources[0x72]	758975	1			T1	1057		T3	64		T5	36
valid_sources[0x73]	308290	1			T1	1126		T3	51		T5	26
valid_sources[0x74]	315237	1			T1	1291		T2	32		T3	66
valid_sources[0x75]	562111	1			T1	1326		T3	32		T5	36
valid_sources[0x76]	315970	1			T1	1246		T3	39		T5	38
valid_sources[0x77]	310111	1			T1	1194		T2	23		T3	11
valid_sources[0x78]	314393	1			T1	1260		T2	24		T3	59
valid_sources[0x79]	311788	1			T1	1296		T2	13		T3	50
valid_sources[0x7a]	313640	1			T1	1266		T2	10		T3	54
valid_sources[0x7b]	323800	1			T1	1129		T2	6		T3	52
valid_sources[0x7c]	316633	1			T1	1250		T2	6		T3	10
valid_sources[0x7d]	1135908	1			T1	1081		T2	38		T3	33
valid_sources[0x7e]	309209	1			T1	1272		T2	19		T3	34
valid_sources[0x7f]	311843	1			T1	1293		T2	22		T3	58
valid_sources[0x80]	313325	1			T1	1281		T2	12		T3	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7407161

1

T1

19924

T2

222

T3

716

values[0x0]

all_enables

biggest_size

15562012

1

T1

51269

T2

429

T3

1835

values[0x1]

all_enables

biggest_size

9101470

1

T1

29476

T2

233

T3

1061