Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T18,T63
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12068	0	0
DisabledNoTrigBkwd_A	2147483647	806630	0	0
DisabledNoTrigFwd_A	2147483647	1614818785	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12068	0	0
T6	55086	0	0	0
T7	582634	0	0	0
T8	1078712	0	0	0
T9	1486222	0	0	0
T10	575565	0	0	0
T14	539186	0	0	0
T15	21250	0	0	0
T16	886	184	0	0
T17	41059	0	0	0
T18	1978	213	0	0
T20	891870	0	0	0
T63	2983	565	0	0
T64	31422	0	0	0
T65	84882	0	0	0
T66	9476	0	0	0
T67	328680	0	0	0
T68	403534	0	0	0
T82	291991	0	0	0
T83	112385	0	0	0
T84	418956	0	0	0
T85	130301	0	0	0
T191	0	216	0	0
T192	0	812	0	0
T193	0	813	0	0
T194	0	1636	0	0
T195	0	787	0	0
T196	0	338	0	0
T197	0	161	0	0
T198	0	682	0	0
T199	0	291	0	0
T200	0	444	0	0
T201	0	333	0	0
T202	0	1166	0	0
T203	0	230	0	0
T204	0	1092	0	0
T205	0	571	0	0
T206	0	947	0	0
T207	0	587	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	806630	0	0
T1	861858	4752	0	0
T2	60939	13	0	0
T3	410904	9	0	0
T4	1057972	2204	0	0
T5	104748	0	0	0
T6	27543	0	0	0
T7	291317	4739	0	0
T8	2157424	13501	0	0
T9	743111	7	0	0
T14	1078372	4041	0	0
T16	3544	8	0	0
T17	164236	47	0	0
T18	3956	3	0	0
T20	445935	7073	0	0
T21	0	364	0	0
T23	0	8	0	0
T40	0	3	0	0
T41	0	38	0	0
T42	0	12	0	0
T43	0	15	0	0
T44	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1614818785	0	0
T1	1149144	312927	0	0
T2	81252	39150	0	0
T3	547872	411472	0	0
T4	1057972	786956	0	0
T5	139664	97321	0	0
T8	2157424	1105570	0	0
T14	1078372	1454295	0	0
T16	3544	2416	0	0
T17	164236	71432	0	0
T18	3956	2416	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T63,T194,T200
1	1	Covered	T1,T2,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	708898917	3822	0	0
DisabledNoTrigBkwd_A	708898917	246248	0	0
DisabledNoTrigFwd_A	708898917	362939089	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	3822	0	0
T63	2983	565	0	0
T64	31422	0	0	0
T65	84882	0	0	0
T66	9476	0	0	0
T67	328680	0	0	0
T68	403534	0	0	0
T82	291991	0	0	0
T83	112385	0	0	0
T84	418956	0	0	0
T85	130301	0	0	0
T194	0	1636	0	0
T200	0	444	0	0
T203	0	230	0	0
T206	0	947	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	246248	0	0
T1	287286	1750	0	0
T2	20313	0	0	0
T3	136968	0	0	0
T4	264493	18	0	0
T5	34916	0	0	0
T8	539356	0	0	0
T14	269593	902	0	0
T16	886	0	0	0
T17	41059	16	0	0
T18	989	0	0	0
T20	0	2503	0	0
T40	0	3	0	0
T41	0	24	0	0
T42	0	1	0	0
T43	0	15	0	0
T44	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	362939089	0	0
T1	287286	5401	0	0
T2	20313	6494	0	0
T3	136968	136962	0	0
T4	264493	258928	0	0
T5	34916	32709	0	0
T8	539356	538161	0	0
T14	269593	432782	0	0
T16	886	598	0	0
T17	41059	3083	0	0
T18	989	598	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T191,T192
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	708898917	3720	0	0
DisabledNoTrigBkwd_A	708898917	197897	0	0
DisabledNoTrigFwd_A	708898917	420750837	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	3720	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	0	0	0
T9	743111	0	0	0
T14	269593	0	0	0
T15	10625	0	0	0
T16	886	184	0	0
T17	41059	0	0	0
T18	989	0	0	0
T20	445935	0	0	0
T191	0	216	0	0
T192	0	812	0	0
T195	0	787	0	0
T197	0	161	0	0
T198	0	682	0	0
T199	0	291	0	0
T207	0	587	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	197897	0	0
T1	287286	1199	0	0
T2	20313	6	0	0
T3	136968	9	0	0
T4	264493	0	0	0
T5	34916	0	0	0
T7	0	2403	0	0
T8	539356	2891	0	0
T9	0	3	0	0
T14	269593	130	0	0
T16	886	8	0	0
T17	41059	28	0	0
T18	989	0	0	0
T20	0	1696	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	420750837	0	0
T1	287286	18231	0	0
T2	20313	5911	0	0
T3	136968	586	0	0
T4	264493	264487	0	0
T5	34916	29075	0	0
T8	539356	14426	0	0
T14	269593	247915	0	0
T16	886	602	0	0
T17	41059	29446	0	0
T18	989	602	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T16
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T4,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T196,T201
1	1	Covered	T5,T4,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	708898917	1976	0	0
DisabledNoTrigBkwd_A	708898917	168874	0	0
DisabledNoTrigFwd_A	708898917	432082755	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	1976	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	0	0	0
T9	743111	0	0	0
T10	575565	0	0	0
T14	269593	0	0	0
T15	10625	0	0	0
T18	989	213	0	0
T20	445935	0	0	0
T60	387105	0	0	0
T196	0	338	0	0
T201	0	333	0	0
T204	0	1092	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	168874	0	0
T4	264493	13	0	0
T6	27543	0	0	0
T7	291317	839	0	0
T8	539356	0	0	0
T9	743111	0	0	0
T14	269593	2954	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	3	0	0
T20	445935	2577	0	0
T21	0	364	0	0
T23	0	8	0	0
T41	0	7	0	0
T42	0	11	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	432082755	0	0
T1	287286	287278	0	0
T2	20313	20220	0	0
T3	136968	136962	0	0
T4	264493	261458	0	0
T5	34916	30786	0	0
T8	539356	539350	0	0
T14	269593	525683	0	0
T16	886	606	0	0
T17	41059	16059	0	0
T18	989	606	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T193,T202,T205
1	1	Covered	T1,T2,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	708898917	2550	0	0
DisabledNoTrigBkwd_A	708898917	193611	0	0
DisabledNoTrigFwd_A	708898917	399046104	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	2550	0	0
T102	246456	0	0	0
T193	3788	813	0	0
T202	0	1166	0	0
T205	0	571	0	0
T208	103849	0	0	0
T209	10119	0	0	0
T210	64594	0	0	0
T211	52422	0	0	0
T212	47243	0	0	0
T213	37768	0	0	0
T214	189572	0	0	0
T215	17454	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	193611	0	0
T1	287286	1803	0	0
T2	20313	7	0	0
T3	136968	0	0	0
T4	264493	2173	0	0
T5	34916	0	0	0
T7	0	1497	0	0
T8	539356	10610	0	0
T9	0	4	0	0
T14	269593	55	0	0
T16	886	0	0	0
T17	41059	2	0	0
T18	989	0	0	0
T20	0	297	0	0
T41	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	399046104	0	0
T1	287286	2017	0	0
T2	20313	6525	0	0
T3	136968	136962	0	0
T4	264493	2083	0	0
T5	34916	4751	0	0
T8	539356	13633	0	0
T14	269593	247915	0	0
T16	886	610	0	0
T17	41059	22844	0	0
T18	989	610	0	0