Module Definition
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Module : prim_alert_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alerts[0].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[1].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[2].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[3].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[4].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[5].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[6].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[7].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[8].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[9].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[10].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[11].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[12].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[13].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[14].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[15].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[16].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[17].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[18].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[19].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[20].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[21].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[22].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[23].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[24].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[25].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[26].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[27].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[28].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[29].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[30].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[31].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[32].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[33].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[34].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[35].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[36].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[37].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[38].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[39].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[40].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[41].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[42].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[43].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[44].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[45].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[46].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[47].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[48].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[49].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[50].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[51].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[52].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[53].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[54].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[55].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[56].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[57].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[58].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[59].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[60].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[61].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[62].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[63].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[64].u_alert_receiver 100.00 100.00



Module Instance : tb.dut.gen_alerts[0].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[1].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[2].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[3].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[4].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[5].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[6].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[7].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[8].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[9].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[10].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[11].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[12].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[13].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[14].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[15].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[16].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[17].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[18].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[19].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[20].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[21].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[22].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[23].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[24].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[25].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[26].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[27].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[28].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[29].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[30].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[31].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[32].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[33].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[34].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[35].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[36].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[37].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[38].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[39].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[40].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[41].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[42].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[43].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[44].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[45].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[46].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[47].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[48].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[49].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[50].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[51].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[52].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[53].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[54].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[55].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[56].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[57].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[58].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[59].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[60].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[61].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[62].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[63].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[64].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T4,T8 Yes T1,T4,T8 INPUT
ping_ok_o Yes Yes T1,T4,T8 Yes T1,T4,T8 OUTPUT
integ_fail_o Yes Yes T1,T17,T8 Yes T1,T17,T8 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T4,T8 Yes T1,T8,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T8,T6 Yes T1,T4,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[0].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T1,T17,T14 Yes T1,T17,T14 OUTPUT
alert_o Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T8,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T6,T15 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T5,T4 Yes T1,T5,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[1].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T17,T8,T69 Yes T17,T8,T69 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T1,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T6,T15 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[2].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T1,T17,T20 Yes T1,T17,T20 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T6,T15,T48 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T48 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[3].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T4,T6 Yes T1,T4,T6 INPUT
ping_ok_o Yes Yes T1,T4,T6 Yes T1,T4,T6 OUTPUT
integ_fail_o Yes Yes T1,T14,T42 Yes T1,T14,T42 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T4,T6 Yes T1,T6,T7 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T6,T7 Yes T1,T4,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[4].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T6,T15 Yes T8,T6,T15 INPUT
ping_ok_o Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
integ_fail_o Yes Yes T1,T69,T41 Yes T1,T69,T41 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[5].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T4,T8 Yes T1,T4,T8 INPUT
ping_ok_o Yes Yes T1,T4,T8 Yes T1,T4,T8 OUTPUT
integ_fail_o Yes Yes T1,T14,T20 Yes T1,T14,T20 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T4,T8 Yes T1,T8,T14 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T8,T14 Yes T1,T4,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[6].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T14,T6,T15 Yes T14,T6,T15 INPUT
ping_ok_o Yes Yes T14,T6,T15 Yes T14,T6,T15 OUTPUT
integ_fail_o Yes Yes T1,T20,T23 Yes T1,T20,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T14,T6,T15 Yes T14,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T6,T15 Yes T14,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[7].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T1,T14,T20 Yes T1,T14,T20 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[8].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T4,T6 Yes T1,T4,T6 INPUT
ping_ok_o Yes Yes T1,T4,T6 Yes T1,T4,T6 OUTPUT
integ_fail_o Yes Yes T14,T20,T42 Yes T14,T20,T42 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T4,T6 Yes T6,T15,T69 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T69 Yes T1,T4,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[9].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T1,T69,T41 Yes T1,T69,T41 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T8,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T6,T15 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[10].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T21 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T3,T8,T14 Yes T3,T8,T14 INPUT
ping_ok_o Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
integ_fail_o Yes Yes T2,T17,T8 Yes T2,T17,T8 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T8,T14 Yes T8,T14,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T14,T6 Yes T3,T8,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[11].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T14 Yes T1,T8,T14 INPUT
ping_ok_o Yes Yes T1,T8,T14 Yes T1,T8,T14 OUTPUT
integ_fail_o Yes Yes T1,T8,T42 Yes T1,T8,T42 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T14 Yes T14,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T6,T15 Yes T1,T8,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[12].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T4,T8 Yes T1,T4,T8 INPUT
ping_ok_o Yes Yes T1,T4,T8 Yes T1,T4,T8 OUTPUT
integ_fail_o Yes Yes T1,T8,T20 Yes T1,T8,T20 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T4,T8 Yes T1,T4,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T4,T6 Yes T1,T4,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[13].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
ping_ok_o Yes Yes T1,T4,T6 Yes T1,T4,T6 OUTPUT
integ_fail_o Yes Yes T2,T8,T14 Yes T2,T8,T14 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T3,T4 Yes T4,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T4,T6,T15 Yes T1,T3,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[14].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T3,T6,T7 Yes T3,T6,T7 INPUT
ping_ok_o Yes Yes T6,T7,T15 Yes T6,T7,T15 OUTPUT
integ_fail_o Yes Yes T1,T20,T66 Yes T1,T20,T66 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T6,T7 Yes T3,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T6,T15 Yes T3,T6,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[15].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T14,T6 Yes T8,T14,T6 INPUT
ping_ok_o Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
integ_fail_o Yes Yes T8,T14,T41 Yes T8,T14,T41 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T14,T6 Yes T14,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T6,T15 Yes T8,T14,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[16].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T1,T8,T41 Yes T1,T8,T41 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[17].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T14 Yes T1,T8,T14 INPUT
ping_ok_o Yes Yes T1,T8,T14 Yes T1,T8,T14 OUTPUT
integ_fail_o Yes Yes T2,T8,T69 Yes T2,T8,T69 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T14 Yes T1,T14,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T14,T6 Yes T1,T8,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[18].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T4,T8 Yes T1,T4,T8 INPUT
ping_ok_o Yes Yes T1,T4,T8 Yes T1,T4,T8 OUTPUT
integ_fail_o Yes Yes T8,T14,T42 Yes T8,T14,T42 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T4,T8 Yes T1,T4,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T4,T6 Yes T1,T4,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[19].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T21 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T3,T8 Yes T1,T3,T8 INPUT
ping_ok_o Yes Yes T1,T8,T14 Yes T1,T8,T14 OUTPUT
integ_fail_o Yes Yes T1,T20,T69 Yes T1,T20,T69 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T3,T8 Yes T8,T14,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T14,T6 Yes T1,T3,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[20].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T21 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T8,T14 Yes T4,T8,T14 INPUT
ping_ok_o Yes Yes T4,T8,T14 Yes T4,T8,T14 OUTPUT
integ_fail_o Yes Yes T1,T2,T8 Yes T1,T2,T8 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T8,T14 Yes T8,T14,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T14,T6 Yes T4,T8,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[21].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T14 Yes T1,T8,T14 INPUT
ping_ok_o Yes Yes T1,T8,T14 Yes T1,T8,T14 OUTPUT
integ_fail_o Yes Yes T14,T20,T42 Yes T14,T20,T42 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T14 Yes T8,T14,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T14,T6 Yes T1,T8,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[22].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T21 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T3,T4,T8 Yes T3,T4,T8 INPUT
ping_ok_o Yes Yes T4,T8,T14 Yes T4,T8,T14 OUTPUT
integ_fail_o Yes Yes T2,T8,T69 Yes T2,T8,T69 OUTPUT
alert_o Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T4,T8 Yes T8,T14,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T14,T6 Yes T3,T4,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[23].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T14,T6 Yes T8,T14,T6 INPUT
ping_ok_o Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
integ_fail_o Yes Yes T17,T42,T49 Yes T17,T42,T49 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T14,T6 Yes T14,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T6,T15 Yes T8,T14,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[24].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T4,T8 Yes T1,T4,T8 INPUT
ping_ok_o Yes Yes T1,T4,T8 Yes T1,T4,T8 OUTPUT
integ_fail_o Yes Yes T1,T8,T69 Yes T1,T8,T69 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T4,T8 Yes T6,T15,T42 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T42 Yes T1,T4,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[25].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T6,T15 Yes T8,T6,T15 INPUT
ping_ok_o Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
integ_fail_o Yes Yes T8,T20,T69 Yes T8,T20,T69 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[26].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T4,T8 Yes T1,T4,T8 INPUT
ping_ok_o Yes Yes T1,T4,T8 Yes T1,T4,T8 OUTPUT
integ_fail_o Yes Yes T69,T41,T42 Yes T69,T41,T42 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T4,T8 Yes T6,T15,T68 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T68 Yes T1,T4,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[27].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T6,T7 Yes T8,T6,T7 INPUT
ping_ok_o Yes Yes T8,T6,T7 Yes T8,T6,T7 OUTPUT
integ_fail_o Yes Yes T8,T41,T47 Yes T8,T41,T47 OUTPUT
alert_o Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T6,T7 Yes T8,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T6,T15 Yes T8,T6,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T5,T4 Yes T1,T5,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[28].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T14 Yes T1,T8,T14 INPUT
ping_ok_o Yes Yes T1,T8,T14 Yes T1,T8,T14 OUTPUT
integ_fail_o Yes Yes T1,T8,T14 Yes T1,T8,T14 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T14 Yes T8,T14,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T14,T6 Yes T1,T8,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[29].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T3,T8,T6 Yes T3,T8,T6 INPUT
ping_ok_o Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
integ_fail_o Yes Yes T1,T14,T20 Yes T1,T14,T20 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T8,T6 Yes T6,T15,T69 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T69 Yes T3,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[30].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T6,T15,T217 Yes T6,T15,T217 INPUT
ping_ok_o Yes Yes T6,T15,T23 Yes T6,T15,T23 OUTPUT
integ_fail_o Yes Yes T20,T23,T21 Yes T20,T23,T21 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T15,T217 Yes T6,T15,T217 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T217 Yes T6,T15,T217 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[31].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T21 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T20,T69,T23 Yes T20,T69,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[32].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T6,T15 Yes T1,T6,T15 INPUT
ping_ok_o Yes Yes T1,T6,T15 Yes T1,T6,T15 OUTPUT
integ_fail_o Yes Yes T2,T14,T41 Yes T2,T14,T41 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T6,T15 Yes T6,T15,T69 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T69 Yes T1,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[33].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T6,T7 Yes T8,T6,T7 INPUT
ping_ok_o Yes Yes T8,T6,T7 Yes T8,T6,T7 OUTPUT
integ_fail_o Yes Yes T1,T20,T69 Yes T1,T20,T69 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T6,T7 Yes T6,T15,T44 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T44 Yes T8,T6,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[34].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T21 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T6,T15 Yes T8,T6,T15 INPUT
ping_ok_o Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
integ_fail_o Yes Yes T1,T17,T14 Yes T1,T17,T14 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T6,T15 Yes T6,T15,T48 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T48 Yes T8,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[35].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T6,T15 Yes T1,T6,T15 INPUT
ping_ok_o Yes Yes T1,T6,T15 Yes T1,T6,T15 OUTPUT
integ_fail_o Yes Yes T8,T14,T20 Yes T8,T14,T20 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T6,T15 Yes T6,T15,T48 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T48 Yes T1,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[36].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T1,T8,T14 Yes T1,T8,T14 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T8,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T6,T15 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[37].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T3,T8,T14 Yes T3,T8,T14 INPUT
ping_ok_o Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
integ_fail_o Yes Yes T1,T8,T23 Yes T1,T8,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T8,T14 Yes T14,T6,T7 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T6,T7 Yes T3,T8,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[38].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T8,T20,T69 Yes T8,T20,T69 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T6,T15,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T23 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[39].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T14 Yes T1,T8,T14 INPUT
ping_ok_o Yes Yes T1,T8,T14 Yes T1,T8,T14 OUTPUT
integ_fail_o Yes Yes T14,T69,T41 Yes T14,T69,T41 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T14 Yes T14,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T6,T15 Yes T1,T8,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[40].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T4,T8 Yes T1,T4,T8 INPUT
ping_ok_o Yes Yes T1,T4,T8 Yes T1,T4,T8 OUTPUT
integ_fail_o Yes Yes T1,T8,T20 Yes T1,T8,T20 OUTPUT
alert_o Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T4,T8 Yes T1,T14,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T14,T6 Yes T1,T4,T8 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T5,T4 Yes T1,T5,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[41].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T1,T69,T42 Yes T1,T69,T42 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[42].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T8,T42,T49 Yes T8,T42,T49 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T6,T15,T44 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T44 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[43].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T14,T6 Yes T8,T14,T6 INPUT
ping_ok_o Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
integ_fail_o Yes Yes T20,T23,T21 Yes T20,T23,T21 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[44].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T14,T6 Yes T8,T14,T6 INPUT
ping_ok_o Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
integ_fail_o Yes Yes T1,T20,T42 Yes T1,T20,T42 OUTPUT
alert_o Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T5,T4 Yes T1,T5,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[45].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T14,T6,T15 Yes T14,T6,T15 INPUT
ping_ok_o Yes Yes T14,T6,T15 Yes T14,T6,T15 OUTPUT
integ_fail_o Yes Yes T1,T17,T8 Yes T1,T17,T8 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T14,T6,T15 Yes T14,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T6,T15 Yes T14,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[46].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T6,T15 Yes T8,T6,T15 INPUT
ping_ok_o Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
integ_fail_o Yes Yes T8,T42,T23 Yes T8,T42,T23 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[47].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T3,T8,T14 Yes T3,T8,T14 INPUT
ping_ok_o Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
integ_fail_o Yes Yes T42,T23,T47 Yes T42,T23,T47 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T8,T14 Yes T14,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T6,T15 Yes T3,T8,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[48].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T14 Yes T1,T8,T14 INPUT
ping_ok_o Yes Yes T1,T8,T14 Yes T1,T8,T14 OUTPUT
integ_fail_o Yes Yes T2,T8,T20 Yes T2,T8,T20 OUTPUT
alert_o Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T14 Yes T14,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T6,T15 Yes T1,T8,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[49].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T3,T8,T14 Yes T3,T8,T14 INPUT
ping_ok_o Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
integ_fail_o Yes Yes T17,T8,T14 Yes T17,T8,T14 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T8,T14 Yes T14,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T6,T15 Yes T3,T8,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[50].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T3,T8,T6 Yes T3,T8,T6 INPUT
ping_ok_o Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
integ_fail_o Yes Yes T1,T20,T21 Yes T1,T20,T21 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T8,T6 Yes T6,T15,T69 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T69 Yes T3,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[51].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T6,T15,T217 Yes T6,T15,T217 INPUT
ping_ok_o Yes Yes T6,T15,T218 Yes T6,T15,T218 OUTPUT
integ_fail_o Yes Yes T1,T17,T20 Yes T1,T17,T20 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T15,T217 Yes T6,T15,T217 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T217 Yes T6,T15,T217 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[52].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T14,T6 Yes T8,T14,T6 INPUT
ping_ok_o Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
integ_fail_o Yes Yes T1,T69,T45 Yes T1,T69,T45 OUTPUT
alert_o Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T14,T6 Yes T14,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T6,T15 Yes T8,T14,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[53].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T3,T8,T6 Yes T3,T8,T6 INPUT
ping_ok_o Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
integ_fail_o Yes Yes T1,T69,T42 Yes T1,T69,T42 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T8,T6 Yes T3,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T6,T15 Yes T3,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[54].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T8,T14,T20 Yes T8,T14,T20 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T8,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T6,T15 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[55].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T3,T6,T15 Yes T3,T6,T15 INPUT
ping_ok_o Yes Yes T6,T15,T60 Yes T6,T15,T60 OUTPUT
integ_fail_o Yes Yes T17,T14,T69 Yes T17,T14,T69 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T6,T15 Yes T3,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T3,T6,T15 Yes T3,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[56].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T6,T9 Yes T1,T6,T9 INPUT
ping_ok_o Yes Yes T1,T6,T15 Yes T1,T6,T15 OUTPUT
integ_fail_o Yes Yes T14,T20,T69 Yes T14,T20,T69 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T6,T9 Yes T6,T15,T48 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T48 Yes T1,T6,T9 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[57].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T8,T14 Yes T4,T8,T14 INPUT
ping_ok_o Yes Yes T4,T8,T14 Yes T4,T8,T14 OUTPUT
integ_fail_o Yes Yes T1,T8,T20 Yes T1,T8,T20 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T8,T14 Yes T8,T14,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T14,T6 Yes T4,T8,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[58].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T6,T9 Yes T1,T6,T9 INPUT
ping_ok_o Yes Yes T1,T6,T15 Yes T1,T6,T15 OUTPUT
integ_fail_o Yes Yes T8,T14,T69 Yes T8,T14,T69 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T6,T9 Yes T1,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T6,T15 Yes T1,T6,T9 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[59].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T6,T15 Yes T8,T6,T15 INPUT
ping_ok_o Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
integ_fail_o Yes Yes T8,T14,T21 Yes T8,T14,T21 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[60].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T3,T8,T6 Yes T3,T8,T6 INPUT
ping_ok_o Yes Yes T8,T6,T15 Yes T8,T6,T15 OUTPUT
integ_fail_o Yes Yes T1,T8,T20 Yes T1,T8,T20 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T3,T8,T6 Yes T6,T15,T69 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T69 Yes T3,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[61].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T6,T7,T15 Yes T6,T7,T15 INPUT
ping_ok_o Yes Yes T6,T7,T15 Yes T6,T7,T15 OUTPUT
integ_fail_o Yes Yes T1,T2,T17 Yes T1,T2,T17 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T7,T15 Yes T6,T15,T49 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T49 Yes T6,T7,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[62].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T14,T6 Yes T8,T14,T6 INPUT
ping_ok_o Yes Yes T8,T14,T6 Yes T8,T14,T6 OUTPUT
integ_fail_o Yes Yes T69,T41,T45 Yes T69,T41,T45 OUTPUT
alert_o Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T14,T6 Yes T14,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T6,T15 Yes T8,T14,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[63].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T6,T15,T23 Yes T6,T15,T23 INPUT
ping_ok_o Yes Yes T6,T15,T23 Yes T6,T15,T23 OUTPUT
integ_fail_o Yes Yes T8,T41,T23 Yes T8,T41,T23 OUTPUT
alert_o Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T5,T4 Yes T1,T5,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T15,T23 Yes T6,T15,T68 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T68 Yes T6,T15,T23 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T5,T4 Yes T1,T5,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[64].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T6,T20 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T14,T20,T60 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T8,T6 Yes T1,T8,T6 INPUT
ping_ok_o Yes Yes T1,T8,T6 Yes T1,T8,T6 OUTPUT
integ_fail_o Yes Yes T2,T8,T20 Yes T2,T8,T20 OUTPUT
alert_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T8,T6 Yes T6,T15,T24 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T15,T24 Yes T1,T8,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT

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