Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T19
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T2,T5,T8
1	1	1	Covered	T2,T5,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T17
0	1	Covered	T17,T14,T20
1	0	Covered	T8,T14,T21

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T17
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T14,T21

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T17
1	0	Covered	T22
1	1	Covered	T17,T14,T20

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T17,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T16

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T2,T5,T17

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T2,T5,T17
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T1,T14,T23
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T14,T24,T25
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T14,T20,T26
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T21,T27,T28
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T5
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T5,T8
TimeoutSt->Phase0St	172	Covered	T17,T8,T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T8,T14
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T14,T23
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T14,T24,T25
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T20,T26
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T27,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	789	0	0
CheckAccumTrig0_A	2147483647	2397	0	0
CheckAccumTrig1_A	2147483647	121	0	0
CheckClr_A	2147483647	1129	0	0
CheckEn_A	2147483647	1229619601	0	0
CheckPhase0_A	2147483647	2693	0	0
CheckPhase1_A	2147483647	2640	0	0
CheckPhase2_A	2147483647	2600	0	0
CheckPhase3_A	2147483647	2563	0	0
CheckTimeout0_A	2147483647	4133	0	0
CheckTimeoutSt1_A	2147483647	443011	0	0
CheckTimeoutSt2_A	2147483647	3772	0	0
CheckTimeoutStTrig_A	2147483647	234	0	0
ErrorStAllEscAsserted_A	2147483647	4367	0	0
ErrorStIsTerminal_A	2147483647	3647	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	789	0	0
T11	235236	155	0	0
T12	0	250	0	0
T13	0	129	0	0
T29	0	112	0	0
T30	0	143	0	0
T31	3344928	0	0	0
T32	484128	0	0	0
T33	81948	0	0	0
T34	966920	0	0	0
T35	3123832	0	0	0
T36	1105736	0	0	0
T37	2290836	0	0	0
T38	1432956	0	0	0
T39	1301096	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2397	0	0
T1	861858	4	0	0
T2	60939	2	0	0
T3	410904	1	0	0
T4	1057972	2	0	0
T5	104748	0	0	0
T6	27543	0	0	0
T7	291317	2	0	0
T8	2157424	0	0	0
T9	743111	1	0	0
T10	0	1	0	0
T14	1078372	32	0	0
T16	3544	1	0	0
T17	164236	2	0	0
T18	3956	1	0	0
T20	445935	11	0	0
T21	0	8	0	0
T23	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	121	0	0
T6	55086	0	0	0
T7	582634	0	0	0
T8	539356	1	0	0
T9	1486222	0	0	0
T10	1151130	0	0	0
T14	539186	1	0	0
T15	21250	0	0	0
T19	0	1	0	0
T20	891870	0	0	0
T21	0	2	0	0
T24	0	3	0	0
T25	0	2	0	0
T26	589932	2	0	0
T31	0	2	0	0
T40	40967	0	0	0
T47	0	1	0	0
T48	234004	2	0	0
T49	106696	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	774210	0	0	0
T61	200916	0	0	0
T62	846124	0	0	0
T63	2983	0	0	0
T64	31422	0	0	0
T65	84882	0	0	0
T66	9476	0	0	0
T67	328680	0	0	0
T68	403534	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1129	0	0
T1	574572	4	0	0
T2	60939	2	0	0
T3	410904	0	0	0
T4	793479	0	0	0
T5	104748	3	0	0
T6	55086	0	0	0
T7	291317	0	0	0
T8	1618068	0	0	0
T9	743111	0	0	0
T10	575565	0	0	0
T14	1078372	21	0	0
T15	10625	0	0	0
T16	2658	0	0	0
T17	123177	0	0	0
T18	2967	0	0	0
T20	445935	3	0	0
T21	0	9	0	0
T23	0	2	0	0
T26	0	13	0	0
T27	0	1	0	0
T40	40967	0	0	0
T42	0	4	0	0
T44	0	1	0	0
T45	0	2	0	0
T47	0	4	0	0
T48	0	11	0	0
T49	0	9	0	0
T50	0	2	0	0
T60	387105	0	0	0
T61	100458	0	0	0
T62	0	1	0	0
T64	0	2	0	0
T67	0	6	0	0
T68	0	1	0	0
T69	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1229619601	0	0
T1	1149144	312927	0	0
T2	81252	39149	0	0
T3	547872	411472	0	0
T4	1057972	273965	0	0
T5	139664	97318	0	0
T8	2157424	1105570	0	0
T14	1078372	2168143	0	0
T16	3544	2416	0	0
T17	164236	52940	0	0
T18	3956	2416	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2693	0	0
T1	861858	6	0	0
T2	60939	4	0	0
T3	410904	1	0	0
T4	1057972	3	0	0
T5	104748	3	0	0
T6	27543	0	0	0
T7	291317	3	0	0
T8	2157424	2	0	0
T9	743111	2	0	0
T14	1078372	43	0	0
T16	3544	1	0	0
T17	164236	4	0	0
T18	3956	1	0	0
T20	445935	16	0	0
T23	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T70	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2640	0	0
T1	861858	4	0	0
T2	60939	4	0	0
T3	410904	1	0	0
T4	1057972	3	0	0
T5	104748	3	0	0
T6	27543	0	0	0
T7	291317	3	0	0
T8	2157424	2	0	0
T9	743111	2	0	0
T14	1078372	42	0	0
T16	3544	1	0	0
T17	164236	4	0	0
T18	3956	1	0	0
T20	445935	16	0	0
T23	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T70	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2600	0	0
T1	861858	4	0	0
T2	60939	4	0	0
T3	410904	1	0	0
T4	1057972	3	0	0
T5	104748	3	0	0
T6	27543	0	0	0
T7	291317	3	0	0
T8	2157424	2	0	0
T9	743111	2	0	0
T14	1078372	41	0	0
T16	3544	1	0	0
T17	164236	4	0	0
T18	3956	1	0	0
T20	445935	15	0	0
T23	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T70	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2563	0	0
T1	861858	4	0	0
T2	60939	4	0	0
T3	410904	1	0	0
T4	1057972	3	0	0
T5	104748	3	0	0
T6	27543	0	0	0
T7	291317	3	0	0
T8	2157424	2	0	0
T9	743111	2	0	0
T14	1078372	41	0	0
T16	3544	1	0	0
T17	164236	4	0	0
T18	3956	1	0	0
T20	445935	15	0	0
T23	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T70	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4133	0	0
T2	20313	1	0	0
T3	136968	0	0	0
T4	1057972	0	0	0
T5	139664	12	0	0
T6	110172	0	0	0
T7	873951	0	0	0
T8	2157424	2	0	0
T14	1078372	14	0	0
T16	3544	0	0	0
T17	164236	1	0	0
T18	3956	0	0	0
T20	1337805	58	0	0
T21	0	14	0	0
T26	0	3	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T45	0	2	0	0
T48	0	11	0	0
T64	0	2	0	0
T66	0	1	0	0
T70	0	5	0	0
T71	0	1	0	0
T72	0	20	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	443011	0	0
T2	20313	108	0	0
T3	136968	0	0	0
T4	1057972	0	0	0
T5	139664	1044	0	0
T6	110172	0	0	0
T7	873951	0	0	0
T8	2157424	138	0	0
T14	1078372	2595	0	0
T16	3544	0	0	0
T17	164236	645	0	0
T18	3956	0	0	0
T20	1337805	9654	0	0
T21	0	1931	0	0
T26	0	515	0	0
T40	0	360	0	0
T41	0	1016	0	0
T42	0	153	0	0
T45	0	330	0	0
T48	0	881	0	0
T64	0	760	0	0
T66	0	209	0	0
T70	0	864	0	0
T71	0	207	0	0
T72	0	4822	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3772	0	0
T2	20313	1	0	0
T3	136968	0	0	0
T4	1057972	0	0	0
T5	139664	9	0	0
T6	110172	0	0	0
T7	873951	0	0	0
T8	2157424	1	0	0
T14	1078372	7	0	0
T16	3544	0	0	0
T17	164236	0	0	0
T18	3956	0	0	0
T20	1337805	56	0	0
T21	0	10	0	0
T24	0	3	0	0
T26	0	3	0	0
T40	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T48	0	10	0	0
T64	0	1	0	0
T67	0	2	0	0
T68	0	6	0	0
T70	0	4	0	0
T71	0	1	0	0
T72	0	20	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	234	0	0
T6	55086	0	0	0
T7	582634	0	0	0
T9	1486222	0	0	0
T10	1151130	0	0	0
T14	539186	3	0	0
T15	21250	0	0	0
T17	41059	1	0	0
T20	891870	1	0	0
T24	0	1	0	0
T26	0	4	0	0
T40	40967	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T50	16055	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T60	387105	0	0	0
T61	100458	0	0	0
T64	31422	1	0	0
T65	84882	0	0	0
T66	9476	1	0	0
T67	328680	0	0	0
T68	403534	1	0	0
T73	0	3	0	0
T74	0	6	0	0
T75	0	3	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	291991	0	0	0
T83	112385	0	0	0
T84	418956	0	0	0
T85	130301	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4367	0	0
T11	235236	743	0	0
T12	0	1460	0	0
T13	0	721	0	0
T29	0	730	0	0
T30	0	713	0	0
T31	3344928	0	0	0
T32	484128	0	0	0
T33	81948	0	0	0
T34	966920	0	0	0
T35	3123832	0	0	0
T36	1105736	0	0	0
T37	2290836	0	0	0
T38	1432956	0	0	0
T39	1301096	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3647	0	0
T11	235236	623	0	0
T12	0	1220	0	0
T13	0	601	0	0
T29	0	610	0	0
T30	0	593	0	0
T31	3344928	0	0	0
T32	484128	0	0	0
T33	81948	0	0	0
T34	966920	0	0	0
T35	3123832	0	0	0
T36	1105736	0	0	0
T37	2290836	0	0	0
T38	1432956	0	0	0
T39	1301096	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1149144	1149112	0	0
T2	81252	80880	0	0
T3	547872	547848	0	0
T4	1057972	1057948	0	0
T5	139664	139376	0	0
T8	2157424	2157400	0	0
T14	1078372	1078020	0	0
T16	3544	3252	0	0
T17	164236	163932	0	0
T18	3956	3656	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1149144	1149112	0	0
T2	81252	80880	0	0
T3	547872	547848	0	0
T4	1057972	1057948	0	0
T5	139664	139376	0	0
T8	2157424	2157400	0	0
T14	1078372	1078020	0	0
T16	3544	3252	0	0
T17	164236	163932	0	0
T18	3956	3656	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T8
1	0	1	Covered	T1,T4,T8
1	1	0	Covered	T5,T8,T14
1	1	1	Covered	T2,T5,T8

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T8
0	1	Covered	T14,T20,T45
1	0	Covered	T14,T21,T47

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T5,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T14,T21,T47

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Not Covered
1	1	Covered	T14,T20,T45

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T14
1	Covered	T4,T14,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T14
1	Covered	T17,T14,T41

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T14,T20,T42

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T14
1	Covered	T1,T14,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T17,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T17,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T17
Phase1St	198	Covered	T1,T4,T17
Phase2St	215	Covered	T1,T4,T17
Phase3St	233	Covered	T1,T4,T17
TerminalSt	249	Covered	T1,T4,T17
TimeoutSt	159	Covered	T2,T5,T8

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T4,T17
IdleSt->TimeoutSt	159	Covered	T2,T5,T8
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T1,T23,T76
Phase0St->Phase1St	198	Covered	T1,T4,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T24,T28,T34
Phase1St->Phase2St	215	Covered	T1,T4,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T20,T26,T86
Phase2St->Phase3St	233	Covered	T1,T4,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T32,T87,T19
Phase3St->TerminalSt	249	Covered	T1,T4,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T14,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T5,T8
TimeoutSt->Phase0St	172	Covered	T14,T20,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T8
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T20,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T23,T76
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T28,T34
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T20,T26,T86
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T87,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T14,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	708898917	209	0	0
CheckAccumTrig0_A	708898917	810	0	0
CheckAccumTrig1_A	708898917	58	0	0
CheckClr_A	708898917	388	0	0
CheckEn_A	708710723	277185889	0	0
CheckPhase0_A	708898917	899	0	0
CheckPhase1_A	708898917	875	0	0
CheckPhase2_A	708898917	863	0	0
CheckPhase3_A	708898917	848	0	0
CheckTimeout0_A	708898917	1071	0	0
CheckTimeoutSt1_A	708898917	112394	0	0
CheckTimeoutSt2_A	708898917	956	0	0
CheckTimeoutStTrig_A	708898917	56	0	0
ErrorStAllEscAsserted_A	708898917	1092	0	0
ErrorStIsTerminal_A	708898917	912	0	0
EscStateOut_A	708709218	708639442	0	0
u_state_regs_A	708898917	708751681	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	209	0	0
T11	58809	45	0	0
T12	0	79	0	0
T13	0	25	0	0
T29	0	15	0	0
T30	0	45	0	0
T31	836232	0	0	0
T32	121032	0	0	0
T33	20487	0	0	0
T34	241730	0	0	0
T35	780958	0	0	0
T36	276434	0	0	0
T37	572709	0	0	0
T38	358239	0	0	0
T39	325274	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	810	0	0
T1	287286	3	0	0
T2	20313	0	0	0
T3	136968	0	0	0
T4	264493	1	0	0
T5	34916	0	0	0
T8	539356	0	0	0
T14	269593	11	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	4	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	58	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T9	743111	0	0	0
T10	575565	0	0	0
T14	269593	1	0	0
T15	10625	0	0	0
T20	445935	0	0	0
T21	0	1	0	0
T24	0	3	0	0
T26	0	2	0	0
T40	40967	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T60	387105	0	0	0
T61	100458	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	388	0	0
T1	287286	2	0	0
T2	20313	0	0	0
T3	136968	0	0	0
T4	264493	0	0	0
T5	34916	0	0	0
T8	539356	0	0	0
T14	269593	3	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T20	0	2	0	0
T23	0	2	0	0
T26	0	8	0	0
T42	0	1	0	0
T47	0	4	0	0
T48	0	7	0	0
T49	0	2	0	0
T64	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708710723	277185889	0	0
T1	287286	5401	0	0
T2	20313	6494	0	0
T3	136968	136962	0	0
T4	264493	5323	0	0
T5	34916	32708	0	0
T8	539356	538161	0	0
T14	269593	235501	0	0
T16	886	598	0	0
T17	41059	3083	0	0
T18	989	598	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	899	0	0
T1	287286	2	0	0
T2	20313	0	0	0
T3	136968	0	0	0
T4	264493	1	0	0
T5	34916	0	0	0
T8	539356	0	0	0
T14	269593	13	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	5	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	875	0	0
T1	287286	2	0	0
T2	20313	0	0	0
T3	136968	0	0	0
T4	264493	1	0	0
T5	34916	0	0	0
T8	539356	0	0	0
T14	269593	13	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	5	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	863	0	0
T1	287286	2	0	0
T2	20313	0	0	0
T3	136968	0	0	0
T4	264493	1	0	0
T5	34916	0	0	0
T8	539356	0	0	0
T14	269593	13	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	4	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	848	0	0
T1	287286	2	0	0
T2	20313	0	0	0
T3	136968	0	0	0
T4	264493	1	0	0
T5	34916	0	0	0
T8	539356	0	0	0
T14	269593	13	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	4	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	1071	0	0
T2	20313	1	0	0
T3	136968	0	0	0
T4	264493	0	0	0
T5	34916	2	0	0
T6	27543	0	0	0
T8	539356	1	0	0
T14	269593	5	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T20	0	1	0	0
T21	0	3	0	0
T40	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	12	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	112394	0	0
T2	20313	108	0	0
T3	136968	0	0	0
T4	264493	0	0	0
T5	34916	153	0	0
T6	27543	0	0	0
T8	539356	136	0	0
T14	269593	201	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T20	0	72	0	0
T21	0	204	0	0
T40	0	360	0	0
T70	0	163	0	0
T71	0	207	0	0
T72	0	2957	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	956	0	0
T2	20313	1	0	0
T3	136968	0	0	0
T4	264493	0	0	0
T5	34916	2	0	0
T6	27543	0	0	0
T8	539356	1	0	0
T14	269593	3	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T21	0	2	0	0
T40	0	1	0	0
T46	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	12	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	56	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T9	743111	0	0	0
T10	575565	0	0	0
T14	269593	1	0	0
T15	10625	0	0	0
T20	445935	1	0	0
T26	0	3	0	0
T40	40967	0	0	0
T45	0	1	0	0
T51	0	2	0	0
T60	387105	0	0	0
T61	100458	0	0	0
T68	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	1092	0	0
T11	58809	172	0	0
T12	0	353	0	0
T13	0	181	0	0
T29	0	204	0	0
T30	0	182	0	0
T31	836232	0	0	0
T32	121032	0	0	0
T33	20487	0	0	0
T34	241730	0	0	0
T35	780958	0	0	0
T36	276434	0	0	0
T37	572709	0	0	0
T38	358239	0	0	0
T39	325274	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	912	0	0
T11	58809	142	0	0
T12	0	293	0	0
T13	0	151	0	0
T29	0	174	0	0
T30	0	152	0	0
T31	836232	0	0	0
T32	121032	0	0	0
T33	20487	0	0	0
T34	241730	0	0	0
T35	780958	0	0	0
T36	276434	0	0	0
T37	572709	0	0	0
T38	358239	0	0	0
T39	325274	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708709218	708639442	0	0
T1	287286	287278	0	0
T2	20313	20220	0	0
T3	136968	136962	0	0
T4	264493	264487	0	0
T5	34916	34844	0	0
T8	539356	539350	0	0
T14	269593	269505	0	0
T16	886	813	0	0
T17	41059	40983	0	0
T18	989	914	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	708751681	0	0
T1	287286	287278	0	0
T2	20313	20220	0	0
T3	136968	136962	0	0
T4	264493	264487	0	0
T5	34916	34844	0	0
T8	539356	539350	0	0
T14	269593	269505	0	0
T16	886	813	0	0
T17	41059	40983	0	0
T18	989	914	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T4,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T4,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T4,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T18,T14

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T17,T14
1	0	1	Covered	T4,T18,T14
1	1	0	Covered	T2,T5,T8
1	1	1	Covered	T5,T17,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T17,T14
0	1	Covered	T17,T14,T41
1	0	Covered	T48,T50,T25

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T17,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T48,T50,T25

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T17,T14
1	0	Not Covered
1	1	Covered	T17,T14,T41

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T14
1	Covered	T18,T14,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T18
1	Covered	T14,T20,T42

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T18,T14
1	Covered	T4,T20,T41

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T18,T14
1	Covered	T17,T14,T48

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T18,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T17,T18,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T18,T14,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T17,T18,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T17,T18
Phase1St	198	Covered	T4,T17,T18
Phase2St	215	Covered	T4,T17,T18
Phase3St	233	Covered	T4,T17,T18
TerminalSt	249	Covered	T4,T17,T18
TimeoutSt	159	Covered	T5,T17,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T4,T18,T14
IdleSt->TimeoutSt	159	Covered	T5,T17,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T68,T76,T77
Phase0St->Phase1St	198	Covered	T4,T17,T18
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T32,T76,T88
Phase1St->Phase2St	215	Covered	T4,T17,T18
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T14,T89,T90
Phase2St->Phase3St	233	Covered	T4,T17,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T21,T91,T92
Phase3St->TerminalSt	249	Covered	T4,T17,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T14,T20,T42
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T14,T20
TimeoutSt->Phase0St	172	Covered	T17,T14,T41

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T18,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T17,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T14,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T17,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T68,T76,T77
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T17,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T17,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T76,T88
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T17,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T17,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T89,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T17,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T17,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T91,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T17,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T17,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T20,T42
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T17,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	708898917	172	0	0
CheckAccumTrig0_A	708898917	492	0	0
CheckAccumTrig1_A	708898917	20	0	0
CheckClr_A	708898917	224	0	0
CheckEn_A	708710723	333543184	0	0
CheckPhase0_A	708898917	566	0	0
CheckPhase1_A	708898917	556	0	0
CheckPhase2_A	708898917	546	0	0
CheckPhase3_A	708898917	539	0	0
CheckTimeout0_A	708898917	1074	0	0
CheckTimeoutSt1_A	708898917	117727	0	0
CheckTimeoutSt2_A	708898917	988	0	0
CheckTimeoutStTrig_A	708898917	65	0	0
ErrorStAllEscAsserted_A	708898917	1085	0	0
ErrorStIsTerminal_A	708898917	905	0	0
EscStateOut_A	708709218	708639442	0	0
u_state_regs_A	708898917	708751681	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	172	0	0
T11	58809	22	0	0
T12	0	61	0	0
T13	0	30	0	0
T29	0	30	0	0
T30	0	29	0	0
T31	836232	0	0	0
T32	121032	0	0	0
T33	20487	0	0	0
T34	241730	0	0	0
T35	780958	0	0	0
T36	276434	0	0	0
T37	572709	0	0	0
T38	358239	0	0	0
T39	325274	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	492	0	0
T4	264493	1	0	0
T6	27543	0	0	0
T7	291317	1	0	0
T8	539356	0	0	0
T9	743111	0	0	0
T14	269593	11	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	1	0	0
T20	445935	4	0	0
T21	0	8	0	0
T23	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	20	0	0
T25	0	1	0	0
T26	589932	0	0	0
T48	234004	1	0	0
T49	106696	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T62	846124	0	0	0
T63	2983	0	0	0
T64	31422	0	0	0
T65	84882	0	0	0
T66	9476	0	0	0
T67	328680	0	0	0
T68	403534	0	0	0
T91	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	224	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T9	743111	0	0	0
T10	575565	0	0	0
T14	269593	7	0	0
T15	10625	0	0	0
T20	445935	1	0	0
T21	0	6	0	0
T40	40967	0	0	0
T42	0	1	0	0
T48	0	1	0	0
T49	0	4	0	0
T50	0	2	0	0
T60	387105	0	0	0
T61	100458	0	0	0
T64	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708710723	333543184	0	0
T1	287286	287278	0	0
T2	20313	20219	0	0
T3	136968	136962	0	0
T4	264493	2072	0	0
T5	34916	30785	0	0
T8	539356	539350	0	0
T14	269593	495206	0	0
T16	886	606	0	0
T17	41059	13844	0	0
T18	989	606	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	566	0	0
T4	264493	1	0	0
T6	27543	0	0	0
T7	291317	1	0	0
T8	539356	0	0	0
T9	743111	0	0	0
T14	269593	13	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	1	0	0
T20	445935	4	0	0
T23	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T70	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	556	0	0
T4	264493	1	0	0
T6	27543	0	0	0
T7	291317	1	0	0
T8	539356	0	0	0
T9	743111	0	0	0
T14	269593	13	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	1	0	0
T20	445935	4	0	0
T23	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T70	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	546	0	0
T4	264493	1	0	0
T6	27543	0	0	0
T7	291317	1	0	0
T8	539356	0	0	0
T9	743111	0	0	0
T14	269593	12	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	1	0	0
T20	445935	4	0	0
T23	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T70	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	539	0	0
T4	264493	1	0	0
T6	27543	0	0	0
T7	291317	1	0	0
T8	539356	0	0	0
T9	743111	0	0	0
T14	269593	12	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	1	0	0
T20	445935	4	0	0
T23	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T70	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	1074	0	0
T4	264493	0	0	0
T5	34916	1	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	0	0	0
T14	269593	4	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	445935	3	0	0
T21	0	4	0	0
T41	0	1	0	0
T45	0	1	0	0
T48	0	2	0	0
T70	0	1	0	0
T72	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	117727	0	0
T4	264493	0	0	0
T5	34916	122	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	0	0	0
T14	269593	1474	0	0
T16	886	0	0	0
T17	41059	645	0	0
T18	989	0	0	0
T20	445935	404	0	0
T21	0	588	0	0
T41	0	851	0	0
T45	0	157	0	0
T48	0	52	0	0
T70	0	191	0	0
T72	0	1664	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	988	0	0
T4	264493	0	0	0
T5	34916	1	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	0	0	0
T14	269593	2	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T20	445935	3	0	0
T21	0	3	0	0
T24	0	2	0	0
T26	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T68	0	5	0	0
T72	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	65	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	0	0	0
T9	743111	0	0	0
T10	575565	0	0	0
T14	269593	2	0	0
T15	10625	0	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	445935	0	0	0
T26	0	1	0	0
T31	0	1	0	0
T41	0	1	0	0
T70	0	1	0	0
T73	0	1	0	0
T74	0	5	0	0
T75	0	2	0	0
T98	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	1085	0	0
T11	58809	186	0	0
T12	0	377	0	0
T13	0	172	0	0
T29	0	194	0	0
T30	0	156	0	0
T31	836232	0	0	0
T32	121032	0	0	0
T33	20487	0	0	0
T34	241730	0	0	0
T35	780958	0	0	0
T36	276434	0	0	0
T37	572709	0	0	0
T38	358239	0	0	0
T39	325274	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	905	0	0
T11	58809	156	0	0
T12	0	317	0	0
T13	0	142	0	0
T29	0	164	0	0
T30	0	126	0	0
T31	836232	0	0	0
T32	121032	0	0	0
T33	20487	0	0	0
T34	241730	0	0	0
T35	780958	0	0	0
T36	276434	0	0	0
T37	572709	0	0	0
T38	358239	0	0	0
T39	325274	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708709218	708639442	0	0
T1	287286	287278	0	0
T2	20313	20220	0	0
T3	136968	136962	0	0
T4	264493	264487	0	0
T5	34916	34844	0	0
T8	539356	539350	0	0
T14	269593	269505	0	0
T16	886	813	0	0
T17	41059	40983	0	0
T18	989	914	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	708751681	0	0
T1	287286	287278	0	0
T2	20313	20220	0	0
T3	136968	136962	0	0
T4	264493	264487	0	0
T5	34916	34844	0	0
T8	539356	539350	0	0
T14	269593	269505	0	0
T16	886	813	0	0
T17	41059	40983	0	0
T18	989	914	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T19
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T3,T16,T14
1	1	0	Covered	T5,T14,T20
1	1	1	Covered	T5,T8,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T20
0	1	Covered	T64,T66,T24
1	0	Covered	T8,T21,T25

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T8,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T8,T21,T25

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T20
1	0	Not Covered
1	1	Covered	T64,T66,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T1,T16,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T2,T3,T8

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T14,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T14,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T16,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T5,T8,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T5,T8,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T14,T25,T58
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T14,T25,T57
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T37,T99,T57
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T100,T101
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T14,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T20,T72
TimeoutSt->Phase0St	172	Covered	T8,T21,T64

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T8,T21,T64
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T20,T72
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T14,T25,T58
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T14,T25,T57
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T37,T99,T57
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T100,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T14,T69
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	708898917	209	0	0
CheckAccumTrig0_A	708898917	545	0	0
CheckAccumTrig1_A	708898917	26	0	0
CheckClr_A	708898917	256	0	0
CheckEn_A	708710723	299475005	0	0
CheckPhase0_A	708898917	621	0	0
CheckPhase1_A	708898917	612	0	0
CheckPhase2_A	708898917	602	0	0
CheckPhase3_A	708898917	600	0	0
CheckTimeout0_A	708898917	937	0	0
CheckTimeoutSt1_A	708898917	107602	0	0
CheckTimeoutSt2_A	708898917	850	0	0
CheckTimeoutStTrig_A	708898917	61	0	0
ErrorStAllEscAsserted_A	708898917	1121	0	0
ErrorStIsTerminal_A	708898917	941	0	0
EscStateOut_A	708709218	708639442	0	0
u_state_regs_A	708898917	708751681	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	209	0	0
T11	58809	61	0	0
T12	0	43	0	0
T13	0	39	0	0
T29	0	36	0	0
T30	0	30	0	0
T31	836232	0	0	0
T32	121032	0	0	0
T33	20487	0	0	0
T34	241730	0	0	0
T35	780958	0	0	0
T36	276434	0	0	0
T37	572709	0	0	0
T38	358239	0	0	0
T39	325274	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	545	0	0
T1	287286	1	0	0
T2	20313	2	0	0
T3	136968	1	0	0
T4	264493	0	0	0
T5	34916	0	0	0
T7	0	1	0	0
T8	539356	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	269593	10	0	0
T16	886	1	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	26	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	1	0	0
T9	743111	0	0	0
T10	575565	0	0	0
T14	269593	0	0	0
T15	10625	0	0	0
T19	0	1	0	0
T20	445935	0	0	0
T21	0	1	0	0
T25	0	1	0	0
T31	0	2	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	387105	0	0	0
T61	100458	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	256	0	0
T2	20313	1	0	0
T3	136968	0	0	0
T4	264493	0	0	0
T5	34916	0	0	0
T6	27543	0	0	0
T8	539356	0	0	0
T14	269593	6	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T21	0	2	0	0
T26	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T48	0	1	0	0
T62	0	1	0	0
T69	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708710723	299475005	0	0
T1	287286	18231	0	0
T2	20313	5911	0	0
T3	136968	586	0	0
T4	264493	264487	0	0
T5	34916	29074	0	0
T8	539356	14426	0	0
T14	269593	692784	0	0
T16	886	602	0	0
T17	41059	21598	0	0
T18	989	602	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	621	0	0
T1	287286	1	0	0
T2	20313	2	0	0
T3	136968	1	0	0
T4	264493	0	0	0
T5	34916	0	0	0
T7	0	1	0	0
T8	539356	1	0	0
T9	0	1	0	0
T14	269593	9	0	0
T16	886	1	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	612	0	0
T1	287286	1	0	0
T2	20313	2	0	0
T3	136968	1	0	0
T4	264493	0	0	0
T5	34916	0	0	0
T7	0	1	0	0
T8	539356	1	0	0
T9	0	1	0	0
T14	269593	8	0	0
T16	886	1	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	602	0	0
T1	287286	1	0	0
T2	20313	2	0	0
T3	136968	1	0	0
T4	264493	0	0	0
T5	34916	0	0	0
T7	0	1	0	0
T8	539356	1	0	0
T9	0	1	0	0
T14	269593	8	0	0
T16	886	1	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	600	0	0
T1	287286	1	0	0
T2	20313	2	0	0
T3	136968	1	0	0
T4	264493	0	0	0
T5	34916	0	0	0
T7	0	1	0	0
T8	539356	1	0	0
T9	0	1	0	0
T14	269593	8	0	0
T16	886	1	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	937	0	0
T4	264493	0	0	0
T5	34916	1	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	1	0	0
T14	269593	0	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T20	445935	22	0	0
T21	0	6	0	0
T26	0	1	0	0
T48	0	7	0	0
T64	0	2	0	0
T66	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	107602	0	0
T4	264493	0	0	0
T5	34916	130	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	2	0	0
T14	269593	0	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T20	445935	3940	0	0
T21	0	1032	0	0
T26	0	31	0	0
T48	0	656	0	0
T64	0	760	0	0
T66	0	209	0	0
T70	0	163	0	0
T72	0	201	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	850	0	0
T4	264493	0	0	0
T5	34916	1	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	0	0	0
T14	269593	0	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T20	445935	22	0	0
T21	0	5	0	0
T24	0	1	0	0
T26	0	1	0	0
T48	0	7	0	0
T64	0	1	0	0
T67	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	61	0	0
T24	0	1	0	0
T50	16055	0	0	0
T53	0	1	0	0
T64	31422	1	0	0
T65	84882	0	0	0
T66	9476	1	0	0
T67	328680	0	0	0
T68	403534	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	291991	0	0	0
T83	112385	0	0	0
T84	418956	0	0	0
T85	130301	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	1121	0	0
T11	58809	212	0	0
T12	0	377	0	0
T13	0	179	0	0
T29	0	161	0	0
T30	0	192	0	0
T31	836232	0	0	0
T32	121032	0	0	0
T33	20487	0	0	0
T34	241730	0	0	0
T35	780958	0	0	0
T36	276434	0	0	0
T37	572709	0	0	0
T38	358239	0	0	0
T39	325274	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	941	0	0
T11	58809	182	0	0
T12	0	317	0	0
T13	0	149	0	0
T29	0	131	0	0
T30	0	162	0	0
T31	836232	0	0	0
T32	121032	0	0	0
T33	20487	0	0	0
T34	241730	0	0	0
T35	780958	0	0	0
T36	276434	0	0	0
T37	572709	0	0	0
T38	358239	0	0	0
T39	325274	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708709218	708639442	0	0
T1	287286	287278	0	0
T2	20313	20220	0	0
T3	136968	136962	0	0
T4	264493	264487	0	0
T5	34916	34844	0	0
T8	539356	539350	0	0
T14	269593	269505	0	0
T16	886	813	0	0
T17	41059	40983	0	0
T18	989	914	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	708751681	0	0
T1	287286	287278	0	0
T2	20313	20220	0	0
T3	136968	136962	0	0
T4	264493	264487	0	0
T5	34916	34844	0	0
T8	539356	539350	0	0
T14	269593	269505	0	0
T16	886	813	0	0
T17	41059	40983	0	0
T18	989	914	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T17
1	0	1	Covered	T1,T4,T8
1	1	0	Covered	T14,T20,T41
1	1	1	Covered	T5,T14,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T14,T20
0	1	Covered	T5,T14,T41
1	0	Covered	T20,T48,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T14,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T48,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T20
1	0	Covered	T22
1	1	Covered	T5,T14,T41

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T17,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T2,T8,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T4
1	Covered	T1,T20,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T42,T21

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T5,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T5
Phase1St	198	Covered	T1,T2,T5
Phase2St	215	Covered	T1,T2,T5
Phase3St	233	Covered	T1,T2,T5
TerminalSt	249	Covered	T1,T2,T5
TimeoutSt	159	Covered	T5,T14,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T5,T14,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T74,T75,T102
Phase0St->Phase1St	198	Covered	T1,T2,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T1,T67,T37
Phase1St->Phase2St	215	Covered	T1,T2,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T89,T103,T104
Phase2St->Phase3St	233	Covered	T1,T2,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T28,T74
Phase3St->TerminalSt	249	Covered	T1,T2,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T5,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T14,T20
TimeoutSt->Phase0St	172	Covered	T5,T14,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T74,T75,T80
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T67,T37
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T89,T103,T104
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T28,T74
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	708898917	199	0	0
CheckAccumTrig0_A	708898917	550	0	0
CheckAccumTrig1_A	708898917	17	0	0
CheckClr_A	708898917	261	0	0
CheckEn_A	708710723	319415523	0	0
CheckPhase0_A	708898917	607	0	0
CheckPhase1_A	708898917	597	0	0
CheckPhase2_A	708898917	589	0	0
CheckPhase3_A	708898917	576	0	0
CheckTimeout0_A	708898917	1051	0	0
CheckTimeoutSt1_A	708898917	105288	0	0
CheckTimeoutSt2_A	708898917	978	0	0
CheckTimeoutStTrig_A	708898917	52	0	0
ErrorStAllEscAsserted_A	708898917	1069	0	0
ErrorStIsTerminal_A	708898917	889	0	0
EscStateOut_A	708709218	708639442	0	0
u_state_regs_A	708898917	708751681	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	199	0	0
T11	58809	27	0	0
T12	0	67	0	0
T13	0	35	0	0
T29	0	31	0	0
T30	0	39	0	0
T31	836232	0	0	0
T32	121032	0	0	0
T33	20487	0	0	0
T34	241730	0	0	0
T35	780958	0	0	0
T36	276434	0	0	0
T37	572709	0	0	0
T38	358239	0	0	0
T39	325274	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	550	0	0
T1	287286	3	0	0
T2	20313	2	0	0
T3	136968	0	0	0
T4	264493	1	0	0
T5	34916	0	0	0
T7	0	1	0	0
T8	539356	1	0	0
T9	0	1	0	0
T14	269593	5	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	3	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	17	0	0
T7	291317	0	0	0
T9	743111	0	0	0
T10	575565	0	0	0
T15	10625	0	0	0
T19	0	1	0	0
T20	445935	1	0	0
T40	40967	0	0	0
T41	81589	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T60	387105	0	0	0
T61	100458	0	0	0
T67	0	1	0	0
T69	231583	0	0	0
T77	0	2	0	0
T95	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	261	0	0
T1	287286	2	0	0
T2	20313	1	0	0
T3	136968	0	0	0
T4	264493	0	0	0
T5	34916	3	0	0
T8	539356	0	0	0
T14	269593	5	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T21	0	1	0	0
T26	0	3	0	0
T27	0	1	0	0
T48	0	2	0	0
T49	0	3	0	0
T67	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708710723	319415523	0	0
T1	287286	2017	0	0
T2	20313	6525	0	0
T3	136968	136962	0	0
T4	264493	2083	0	0
T5	34916	4751	0	0
T8	539356	13633	0	0
T14	269593	744652	0	0
T16	886	610	0	0
T17	41059	14415	0	0
T18	989	610	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	607	0	0
T1	287286	3	0	0
T2	20313	2	0	0
T3	136968	0	0	0
T4	264493	1	0	0
T5	34916	3	0	0
T7	0	1	0	0
T8	539356	1	0	0
T9	0	1	0	0
T14	269593	8	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	597	0	0
T1	287286	1	0	0
T2	20313	2	0	0
T3	136968	0	0	0
T4	264493	1	0	0
T5	34916	3	0	0
T7	0	1	0	0
T8	539356	1	0	0
T9	0	1	0	0
T14	269593	8	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	589	0	0
T1	287286	1	0	0
T2	20313	2	0	0
T3	136968	0	0	0
T4	264493	1	0	0
T5	34916	3	0	0
T7	0	1	0	0
T8	539356	1	0	0
T9	0	1	0	0
T14	269593	8	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	576	0	0
T1	287286	1	0	0
T2	20313	2	0	0
T3	136968	0	0	0
T4	264493	1	0	0
T5	34916	3	0	0
T7	0	1	0	0
T8	539356	1	0	0
T9	0	1	0	0
T14	269593	8	0	0
T16	886	0	0	0
T17	41059	1	0	0
T18	989	0	0	0
T20	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	1051	0	0
T4	264493	0	0	0
T5	34916	8	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	0	0	0
T14	269593	5	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T20	445935	32	0	0
T21	0	1	0	0
T26	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T48	0	2	0	0
T70	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	105288	0	0
T4	264493	0	0	0
T5	34916	639	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	0	0	0
T14	269593	920	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T20	445935	5238	0	0
T21	0	107	0	0
T26	0	484	0	0
T41	0	165	0	0
T42	0	153	0	0
T45	0	173	0	0
T48	0	173	0	0
T70	0	347	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	978	0	0
T4	264493	0	0	0
T5	34916	5	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	0	0	0
T14	269593	2	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T20	445935	31	0	0
T26	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T48	0	2	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	52	0	0
T4	264493	0	0	0
T5	34916	3	0	0
T6	27543	0	0	0
T7	291317	0	0	0
T8	539356	0	0	0
T14	269593	3	0	0
T16	886	0	0	0
T17	41059	0	0	0
T18	989	0	0	0
T20	445935	0	0	0
T21	0	1	0	0
T26	0	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T49	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T98	0	6	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	1069	0	0
T11	58809	173	0	0
T12	0	353	0	0
T13	0	189	0	0
T29	0	171	0	0
T30	0	183	0	0
T31	836232	0	0	0
T32	121032	0	0	0
T33	20487	0	0	0
T34	241730	0	0	0
T35	780958	0	0	0
T36	276434	0	0	0
T37	572709	0	0	0
T38	358239	0	0	0
T39	325274	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	889	0	0
T11	58809	143	0	0
T12	0	293	0	0
T13	0	159	0	0
T29	0	141	0	0
T30	0	153	0	0
T31	836232	0	0	0
T32	121032	0	0	0
T33	20487	0	0	0
T34	241730	0	0	0
T35	780958	0	0	0
T36	276434	0	0	0
T37	572709	0	0	0
T38	358239	0	0	0
T39	325274	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708709218	708639442	0	0
T1	287286	287278	0	0
T2	20313	20220	0	0
T3	136968	136962	0	0
T4	264493	264487	0	0
T5	34916	34844	0	0
T8	539356	539350	0	0
T14	269593	269505	0	0
T16	886	813	0	0
T17	41059	40983	0	0
T18	989	914	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708898917	708751681	0	0
T1	287286	287278	0	0
T2	20313	20220	0	0
T3	136968	136962	0	0
T4	264493	264487	0	0
T5	34916	34844	0	0
T8	539356	539350	0	0
T14	269593	269505	0	0
T16	886	813	0	0
T17	41059	40983	0	0
T18	989	914	0	0