Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T65,T66,T196
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14269	0	0
DisabledNoTrigBkwd_A	2147483647	799872	0	0
DisabledNoTrigFwd_A	2147483647	1574824495	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14269	0	0
T13	107555	0	0	0
T37	76204	0	0	0
T44	214710	0	0	0
T65	1463	586	0	0
T66	1838	199	0	0
T67	47008	0	0	0
T68	31270	0	0	0
T74	30534	0	0	0
T75	566742	0	0	0
T76	49206	0	0	0
T110	198040	0	0	0
T196	4806	1352	0	0
T197	0	432	0	0
T198	0	596	0	0
T199	0	907	0	0
T200	0	894	0	0
T201	0	1048	0	0
T202	0	602	0	0
T203	0	770	0	0
T204	0	928	0	0
T205	0	414	0	0
T206	0	238	0	0
T207	0	1121	0	0
T208	0	410	0	0
T209	0	1354	0	0
T210	0	1024	0	0
T211	0	677	0	0
T212	0	387	0	0
T213	0	330	0	0
T214	710128	0	0	0
T215	271632	0	0	0
T216	313100	0	0	0
T217	178661	0	0	0
T218	536038	0	0	0
T219	189788	0	0	0
T220	16855	0	0	0
T221	61187	0	0	0
T222	722764	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	799872	0	0
T1	53480	123	0	0
T2	132660	100	0	0
T3	51920	1	0	0
T4	777568	982	0	0
T5	84324	0	0	0
T6	1185984	2517	0	0
T7	0	2	0	0
T8	0	2233	0	0
T9	0	1	0	0
T10	0	622	0	0
T14	0	3319	0	0
T15	0	547	0	0
T16	0	323	0	0
T17	450852	90	0	0
T18	198828	3	0	0
T19	62160	5	0	0
T20	10852	2	0	0
T21	64868	0	0	0
T22	744192	5922	0	0
T23	31328	2	0	0
T25	0	22	0	0
T27	0	2484	0	0
T42	0	8	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1574824495	0	0
T1	106960	52599	0	0
T2	265320	195758	0	0
T3	103840	94476	0	0
T4	777568	404837	0	0
T5	84324	32104	0	0
T6	1185984	900054	0	0
T17	450852	341013	0	0
T18	198828	150935	0	0
T19	62160	46959	0	0
T20	10852	8466	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T199,T200
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	699378160	3007	0	0
DisabledNoTrigBkwd_A	699378160	271286	0	0
DisabledNoTrigFwd_A	699378160	330959940	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	3007	0	0
T37	38102	0	0	0
T44	107355	0	0	0
T66	919	199	0	0
T67	23504	0	0	0
T68	15635	0	0	0
T74	15267	0	0	0
T75	283371	0	0	0
T76	49206	0	0	0
T199	0	907	0	0
T200	0	894	0	0
T211	0	677	0	0
T213	0	330	0	0
T214	355064	0	0	0
T215	135816	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	271286	0	0
T1	26740	123	0	0
T2	66330	100	0	0
T3	25960	1	0	0
T4	194392	5	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	90	0	0
T18	49707	3	0	0
T19	15540	5	0	0
T20	2713	2	0	0
T22	0	5905	0	0
T23	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	330959940	0	0
T1	26740	582	0	0
T2	66330	2074	0	0
T3	25960	18767	0	0
T4	194392	192895	0	0
T5	21081	8026	0	0
T6	296496	296490	0	0
T17	112713	3048	0	0
T18	49707	2015	0	0
T19	15540	582	0	0
T20	2713	582	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T4,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T65,T197,T203
1	1	Covered	T1,T4,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T22

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	699378160	3710	0	0
DisabledNoTrigBkwd_A	699378160	174273	0	0
DisabledNoTrigFwd_A	699378160	395890985	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	3710	0	0
T37	38102	0	0	0
T44	107355	0	0	0
T65	1463	586	0	0
T66	919	0	0	0
T67	23504	0	0	0
T68	15635	0	0	0
T74	15267	0	0	0
T75	283371	0	0	0
T197	0	432	0	0
T203	0	770	0	0
T205	0	414	0	0
T207	0	1121	0	0
T212	0	387	0	0
T214	355064	0	0	0
T215	135816	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	174273	0	0
T4	194392	971	0	0
T5	21081	0	0	0
T6	296496	2517	0	0
T8	0	2230	0	0
T10	0	622	0	0
T14	0	1	0	0
T15	0	547	0	0
T16	0	2	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	2	0	0
T23	15664	0	0	0
T25	0	21	0	0
T42	0	8	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	395890985	0	0
T1	26740	24749	0	0
T2	66330	61220	0	0
T3	25960	25903	0	0
T4	194392	9163	0	0
T5	21081	8026	0	0
T6	296496	15103	0	0
T17	112713	112655	0	0
T18	49707	49640	0	0
T19	15540	15459	0	0
T20	2713	2628	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T4,T6
1	1	Covered	T4,T6,T21

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T196,T201,T204
1	1	Covered	T4,T6,T21

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T21,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T22,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	699378160	5944	0	0
DisabledNoTrigBkwd_A	699378160	155677	0	0
DisabledNoTrigFwd_A	699378160	441308089	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	5944	0	0
T13	107555	0	0	0
T110	198040	0	0	0
T196	4806	1352	0	0
T201	0	1048	0	0
T204	0	928	0	0
T206	0	238	0	0
T209	0	1354	0	0
T210	0	1024	0	0
T216	313100	0	0	0
T217	178661	0	0	0
T218	536038	0	0	0
T219	189788	0	0	0
T220	16855	0	0	0
T221	61187	0	0	0
T222	722764	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	155677	0	0
T4	194392	6	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T7	0	2	0	0
T8	0	3	0	0
T9	0	1	0	0
T14	0	3318	0	0
T16	0	321	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	15	0	0
T23	15664	0	0	0
T25	0	1	0	0
T27	0	2484	0	0
T70	0	2055	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	441308089	0	0
T1	26740	26674	0	0
T2	66330	66232	0	0
T3	25960	24903	0	0
T4	194392	193582	0	0
T5	21081	8026	0	0
T6	296496	295443	0	0
T17	112713	112655	0	0
T18	49707	49640	0	0
T19	15540	15459	0	0
T20	2713	2628	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T6,T21
1	1	Covered	T1,T4,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T198,T202,T208
1	1	Covered	T1,T4,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	699378160	1608	0	0
DisabledNoTrigBkwd_A	699378160	198636	0	0
DisabledNoTrigFwd_A	699378160	406665481	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1608	0	0
T198	2932	596	0	0
T202	0	602	0	0
T208	0	410	0	0
T223	507927	0	0	0
T224	710632	0	0	0
T225	14302	0	0	0
T226	157314	0	0	0
T227	521559	0	0	0
T228	29347	0	0	0
T229	18107	0	0	0
T230	40721	0	0	0
T231	39513	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	198636	0	0
T1	26740	12	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	1269	0	0
T5	21081	0	0	0
T6	296496	10	0	0
T8	0	19	0	0
T9	0	1	0	0
T11	0	8	0	0
T15	0	510	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T25	0	72	0	0
T42	0	28	0	0
T61	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	406665481	0	0
T1	26740	594	0	0
T2	66330	66232	0	0
T3	25960	24903	0	0
T4	194392	9197	0	0
T5	21081	8026	0	0
T6	296496	293018	0	0
T17	112713	112655	0	0
T18	49707	49640	0	0
T19	15540	15459	0	0
T20	2713	2628	0	0