Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T24
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T22
1	1	0	Covered	T1,T6,T21
1	1	1	Covered	T1,T17,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T18
0	1	Covered	T25,T26,T27
1	0	Covered	T25,T27,T28

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T17,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T25,T27,T28

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T29
1	1	Covered	T25,T26,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T22,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T19
1	Covered	T1,T3,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T5,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T2,T4,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T1,T4,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T2,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T17,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T5,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T17,T18
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T28,T30,T31
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T32,T33,T34
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T27,T35,T34
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T27,T36,T37
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T19
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T17,T18
TimeoutSt->Phase0St	172	Covered	T25,T26,T27

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T30,T38
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T34,T39
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T35,T34
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T36,T37
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1125	0	0
CheckAccumTrig0_A	2147483647	2423	0	0
CheckAccumTrig1_A	2147483647	95	0	0
CheckClr_A	2147483647	1177	0	0
CheckEn_A	2147483647	1226723049	0	0
CheckPhase0_A	2147483647	2738	0	0
CheckPhase1_A	2147483647	2692	0	0
CheckPhase2_A	2147483647	2637	0	0
CheckPhase3_A	2147483647	2583	0	0
CheckTimeout0_A	2147483647	4385	0	0
CheckTimeoutSt1_A	2147483647	498352	0	0
CheckTimeoutSt2_A	2147483647	4029	0	0
CheckTimeoutStTrig_A	2147483647	255	0	0
ErrorStAllEscAsserted_A	2147483647	5743	0	0
ErrorStIsTerminal_A	2147483647	4783	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1125	0	0
T5	84324	170	0	0
T6	1185984	0	0	0
T7	806076	0	0	0
T8	407344	0	0	0
T9	1630976	0	0	0
T12	0	285	0	0
T13	0	136	0	0
T14	445216	0	0	0
T20	10852	0	0	0
T21	129736	0	0	0
T22	1488384	0	0	0
T23	62656	0	0	0
T40	0	287	0	0
T41	0	247	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2423	0	0
T1	53480	5	0	0
T2	132660	2	0	0
T3	51920	1	0	0
T4	777568	3	0	0
T5	84324	0	0	0
T6	1185984	1	0	0
T7	0	1	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	3	0	0
T17	450852	1	0	0
T18	198828	1	0	0
T19	62160	2	0	0
T20	10852	1	0	0
T21	64868	0	0	0
T22	744192	10	0	0
T23	31328	1	0	0
T25	0	4	0	0
T27	0	4	0	0
T42	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	95	0	0
T11	2254377	0	0	0
T15	765492	0	0	0
T16	312519	0	0	0
T25	251340	2	0	0
T26	226809	0	0	0
T27	1638963	1	0	0
T28	455204	1	0	0
T30	7197	0	0	0
T35	275952	0	0	0
T38	0	1	0	0
T42	141918	0	0	0
T43	56655	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	128538	0	0	0
T61	113139	0	0	0
T62	1645668	0	0	0
T63	396640	0	0	0
T64	934771	0	0	0
T65	1463	0	0	0
T66	919	0	0	0
T67	23504	0	0	0
T68	15635	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1177	0	0
T1	26740	4	0	0
T2	66330	1	0	0
T3	25960	0	0	0
T4	194392	0	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T10	133745	1	0	0
T11	751459	0	0	0
T14	111304	1	0	0
T15	510328	1	0	0
T16	0	2	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	1	0	0
T20	2713	0	0	0
T22	372096	7	0	0
T23	15664	1	0	0
T25	167560	5	0	0
T26	151206	0	0	0
T27	0	11	0	0
T28	0	3	0	0
T36	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T63	0	2	0	0
T69	0	2	0	0
T70	0	4	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1226723049	0	0
T1	106960	52597	0	0
T2	265320	195755	0	0
T3	103840	77304	0	0
T4	777568	29888	0	0
T5	1352	1064	0	0
T6	1185984	604505	0	0
T17	450852	341010	0	0
T18	198828	150932	0	0
T19	62160	46956	0	0
T20	10852	8463	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2738	0	0
T1	53480	5	0	0
T2	132660	2	0	0
T3	51920	1	0	0
T4	777568	3	0	0
T5	84324	0	0	0
T6	1185984	1	0	0
T7	0	1	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	450852	1	0	0
T18	198828	1	0	0
T19	62160	2	0	0
T20	10852	1	0	0
T21	64868	0	0	0
T22	744192	10	0	0
T23	31328	1	0	0
T25	0	6	0	0
T26	0	1	0	0
T42	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2692	0	0
T1	53480	5	0	0
T2	132660	2	0	0
T3	51920	1	0	0
T4	777568	3	0	0
T5	84324	0	0	0
T6	1185984	1	0	0
T7	0	1	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	450852	1	0	0
T18	198828	1	0	0
T19	62160	2	0	0
T20	10852	1	0	0
T21	64868	0	0	0
T22	744192	10	0	0
T23	31328	1	0	0
T25	0	6	0	0
T26	0	1	0	0
T42	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2637	0	0
T1	53480	5	0	0
T2	132660	2	0	0
T3	51920	1	0	0
T4	777568	3	0	0
T5	84324	0	0	0
T6	1185984	1	0	0
T7	0	1	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	450852	1	0	0
T18	198828	1	0	0
T19	62160	2	0	0
T20	10852	1	0	0
T21	64868	0	0	0
T22	744192	10	0	0
T23	31328	1	0	0
T25	0	6	0	0
T26	0	1	0	0
T42	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2583	0	0
T1	53480	5	0	0
T2	132660	2	0	0
T3	51920	1	0	0
T4	777568	3	0	0
T5	84324	0	0	0
T6	1185984	1	0	0
T7	0	1	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	450852	1	0	0
T18	198828	1	0	0
T19	62160	2	0	0
T20	10852	1	0	0
T21	64868	0	0	0
T22	744192	10	0	0
T23	31328	1	0	0
T25	0	6	0	0
T26	0	1	0	0
T42	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4385	0	0
T1	53480	4	0	0
T2	132660	0	0	0
T3	51920	0	0	0
T4	388784	0	0	0
T5	42162	0	0	0
T6	592992	0	0	0
T7	403038	0	0	0
T8	203672	0	0	0
T9	815488	0	0	0
T10	267490	0	0	0
T14	222608	0	0	0
T15	510328	0	0	0
T17	225426	1	0	0
T18	99414	1	0	0
T19	31080	1	0	0
T20	5426	0	0	0
T21	64868	19	0	0
T22	744192	3	0	0
T23	31328	0	0	0
T25	167560	7	0	0
T26	0	15	0	0
T27	0	51	0	0
T28	0	375	0	0
T37	0	1	0	0
T42	0	1	0	0
T43	0	4	0	0
T61	0	5	0	0
T63	0	6	0	0
T67	0	1	0	0
T69	0	11	0	0
T72	0	4	0	0
T73	0	1	0	0
T74	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	498352	0	0
T1	53480	765	0	0
T2	132660	0	0	0
T3	51920	0	0	0
T4	388784	0	0	0
T5	42162	0	0	0
T6	592992	0	0	0
T7	403038	0	0	0
T8	203672	0	0	0
T9	815488	0	0	0
T10	267490	0	0	0
T14	222608	0	0	0
T15	510328	0	0	0
T17	225426	176	0	0
T18	99414	131	0	0
T19	31080	21	0	0
T20	5426	0	0	0
T21	64868	1753	0	0
T22	744192	968	0	0
T23	31328	0	0	0
T25	167560	734	0	0
T26	0	2188	0	0
T27	0	5970	0	0
T28	0	25103	0	0
T37	0	59	0	0
T42	0	135	0	0
T43	0	380	0	0
T61	0	329	0	0
T63	0	273	0	0
T67	0	246	0	0
T69	0	1418	0	0
T72	0	263	0	0
T73	0	540	0	0
T74	0	64	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4029	0	0
T1	53480	3	0	0
T2	132660	0	0	0
T3	51920	0	0	0
T4	388784	0	0	0
T5	42162	0	0	0
T6	592992	0	0	0
T7	403038	0	0	0
T8	203672	0	0	0
T9	815488	0	0	0
T10	267490	0	0	0
T14	222608	0	0	0
T15	510328	0	0	0
T17	225426	1	0	0
T18	99414	1	0	0
T19	31080	1	0	0
T20	5426	0	0	0
T21	64868	19	0	0
T22	744192	1	0	0
T23	31328	0	0	0
T25	167560	2	0	0
T26	0	14	0	0
T27	0	48	0	0
T28	0	371	0	0
T31	0	29	0	0
T37	0	1	0	0
T43	0	3	0	0
T45	0	11	0	0
T61	0	4	0	0
T63	0	4	0	0
T69	0	8	0	0
T72	0	4	0	0
T73	0	1	0	0
T75	0	43	0	0
T76	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	255	0	0
T1	26740	0	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T11	751459	0	0	0
T15	255164	0	0	0
T16	104173	0	0	0
T25	83780	1	0	0
T26	75603	1	0	0
T27	1638963	2	0	0
T28	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T36	12522	0	0	0
T37	0	4	0	0
T39	0	3	0	0
T42	47306	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T60	42846	0	0	0
T61	37713	0	0	0
T62	1645668	0	0	0
T63	0	2	0	0
T67	0	1	0	0
T69	154504	3	0	0
T70	224898	0	0	0
T72	6784	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	145808	0	0	0
T84	242060	0	0	0
T85	231008	0	0	0
T86	112364	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5743	0	0
T5	84324	710	0	0
T6	1185984	0	0	0
T7	806076	0	0	0
T8	407344	0	0	0
T9	1630976	0	0	0
T12	0	1460	0	0
T13	0	717	0	0
T14	445216	0	0	0
T20	10852	0	0	0
T21	129736	0	0	0
T22	1488384	0	0	0
T23	62656	0	0	0
T40	0	1433	0	0
T41	0	1423	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4783	0	0
T5	84324	590	0	0
T6	1185984	0	0	0
T7	806076	0	0	0
T8	407344	0	0	0
T9	1630976	0	0	0
T12	0	1220	0	0
T13	0	597	0	0
T14	445216	0	0	0
T20	10852	0	0	0
T21	129736	0	0	0
T22	1488384	0	0	0
T23	62656	0	0	0
T40	0	1193	0	0
T41	0	1183	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	106960	106696	0	0
T2	265320	264928	0	0
T3	103840	103612	0	0
T4	777568	777536	0	0
T5	284	0	0	0
T6	1185984	1185960	0	0
T17	450852	450620	0	0
T18	198828	198560	0	0
T19	62160	61836	0	0
T20	10852	10512	0	0
T21	0	129352	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	106960	106696	0	0
T2	265320	264928	0	0
T3	103840	103612	0	0
T4	777568	777536	0	0
T5	84324	32104	0	0
T6	1185984	1185960	0	0
T17	450852	450620	0	0
T18	198828	198560	0	0
T19	62160	61836	0	0
T20	10852	10512	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T13
1	0	Covered	T4,T6,T21
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T21

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T22

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T21
1	0	1	Covered	T4,T22,T7
1	1	0	Covered	T1,T21,T22
1	1	1	Covered	T21,T25,T26

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T25,T26
0	1	Covered	T25,T26,T28
1	0	Covered	T28,T43,T38

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T21,T25,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T43,T38

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T25,T26
1	0	Not Covered
1	1	Covered	T25,T26,T28

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T22
1	Covered	T25,T15,T42

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T22,T8
1	Covered	T6,T16,T83

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T14
1	Covered	T22,T8,T10

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T22,T8
1	Covered	T4,T14,T25

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T5,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T4,T10,T61

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T6,T10,T42

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T4,T22,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T4,T14,T25

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T6,T22
Phase1St	198	Covered	T4,T6,T22
Phase2St	215	Covered	T4,T6,T22
Phase3St	233	Covered	T4,T6,T22
TerminalSt	249	Covered	T4,T6,T22
TimeoutSt	159	Covered	T21,T25,T26

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T12,T13
IdleSt->Phase0St	152	Covered	T4,T6,T22
IdleSt->TimeoutSt	159	Covered	T21,T25,T26
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T31,T50
Phase0St->Phase1St	198	Covered	T4,T6,T22
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T33,T87,T88
Phase1St->Phase2St	215	Covered	T4,T6,T22
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T89,T90,T91
Phase2St->Phase3St	233	Covered	T4,T6,T22
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T37,T34,T92
Phase3St->TerminalSt	249	Covered	T4,T6,T22
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T22,T14,T10
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T21,T27,T69
TimeoutSt->Phase0St	172	Covered	T25,T26,T28

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T22
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T25,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T25,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T27,T69
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T50,T93
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T6,T22
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T6,T22
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T87,T88,T94
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T6,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T6,T22
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T89,T90,T91
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T6,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T6,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T37,T34,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T6,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T6,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T22,T14,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T6,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	699378160	312	0	0
CheckAccumTrig0_A	699378160	503	0	0
CheckAccumTrig1_A	699378160	17	0	0
CheckClr_A	699378160	253	0	0
CheckEn_A	699066942	325243468	0	0
CheckPhase0_A	699378160	581	0	0
CheckPhase1_A	699378160	573	0	0
CheckPhase2_A	699378160	564	0	0
CheckPhase3_A	699378160	551	0	0
CheckTimeout0_A	699378160	1214	0	0
CheckTimeoutSt1_A	699378160	127111	0	0
CheckTimeoutSt2_A	699378160	1127	0	0
CheckTimeoutStTrig_A	699378160	69	0	0
ErrorStAllEscAsserted_A	699378160	1477	0	0
ErrorStIsTerminal_A	699378160	1237	0	0
EscStateOut_A	699064235	698994223	0	0
u_state_regs_A	699378160	699206548	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	312	0	0
T5	21081	39	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T12	0	82	0	0
T13	0	31	0	0
T14	111304	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T40	0	91	0	0
T41	0	69	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	503	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	1	0	0
T8	0	1	0	0
T10	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	1	0	0
T23	15664	0	0	0
T25	0	4	0	0
T42	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	17	0	0
T28	455204	1	0	0
T30	7197	0	0	0
T35	275952	0	0	0
T38	0	1	0	0
T43	56655	2	0	0
T49	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T63	396640	0	0	0
T64	934771	0	0	0
T65	1463	0	0	0
T66	919	0	0	0
T67	23504	0	0	0
T68	15635	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	253	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T10	133745	1	0	0
T14	111304	1	0	0
T15	255164	0	0	0
T16	0	2	0	0
T22	372096	1	0	0
T23	15664	0	0	0
T25	83780	4	0	0
T26	75603	0	0	0
T27	0	1	0	0
T42	0	2	0	0
T61	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699066942	325243468	0	0
T1	26740	24748	0	0
T2	66330	61219	0	0
T3	25960	25902	0	0
T4	194392	9163	0	0
T5	338	266	0	0
T6	296496	2986	0	0
T17	112713	112654	0	0
T18	49707	49639	0	0
T19	15540	15458	0	0
T20	2713	2627	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	581	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	1	0	0
T8	0	1	0	0
T10	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	1	0	0
T23	15664	0	0	0
T25	0	5	0	0
T26	0	1	0	0
T42	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	573	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	1	0	0
T8	0	1	0	0
T10	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	1	0	0
T23	15664	0	0	0
T25	0	5	0	0
T26	0	1	0	0
T42	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	564	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	1	0	0
T8	0	1	0	0
T10	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	1	0	0
T23	15664	0	0	0
T25	0	5	0	0
T26	0	1	0	0
T42	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	551	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	1	0	0
T8	0	1	0	0
T10	0	2	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	1	0	0
T23	15664	0	0	0
T25	0	5	0	0
T26	0	1	0	0
T42	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1214	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T10	133745	0	0	0
T14	111304	0	0	0
T15	255164	0	0	0
T21	32434	10	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T25	83780	1	0	0
T26	0	1	0	0
T27	0	2	0	0
T28	0	204	0	0
T43	0	3	0	0
T63	0	2	0	0
T67	0	1	0	0
T69	0	8	0	0
T72	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	127111	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T10	133745	0	0	0
T14	111304	0	0	0
T15	255164	0	0	0
T21	32434	898	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T25	83780	1	0	0
T26	0	11	0	0
T27	0	291	0	0
T28	0	12916	0	0
T43	0	50	0	0
T63	0	94	0	0
T67	0	246	0	0
T69	0	1259	0	0
T72	0	189	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1127	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T10	133745	0	0	0
T14	111304	0	0	0
T15	255164	0	0	0
T21	32434	10	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T25	83780	0	0	0
T27	0	2	0	0
T28	0	202	0	0
T31	0	29	0	0
T43	0	1	0	0
T45	0	9	0	0
T69	0	8	0	0
T72	0	3	0	0
T75	0	1	0	0
T76	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	69	0	0
T11	751459	0	0	0
T15	255164	0	0	0
T16	104173	0	0	0
T25	83780	1	0	0
T26	75603	1	0	0
T27	546321	0	0	0
T28	0	1	0	0
T31	0	1	0	0
T37	0	4	0	0
T42	47306	0	0	0
T45	0	1	0	0
T60	42846	0	0	0
T61	37713	0	0	0
T62	548556	0	0	0
T63	0	2	0	0
T67	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1477	0	0
T5	21081	186	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T12	0	360	0	0
T13	0	174	0	0
T14	111304	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T40	0	389	0	0
T41	0	368	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1237	0	0
T5	21081	156	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T12	0	300	0	0
T13	0	144	0	0
T14	111304	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T40	0	329	0	0
T41	0	308	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699064235	698994223	0	0
T1	26740	26674	0	0
T2	66330	66232	0	0
T3	25960	25903	0	0
T4	194392	194384	0	0
T5	71	0	0	0
T6	296496	296490	0	0
T17	112713	112655	0	0
T18	49707	49640	0	0
T19	15540	15459	0	0
T20	2713	2628	0	0
T21	0	32338	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	699206548	0	0
T1	26740	26674	0	0
T2	66330	66232	0	0
T3	25960	25903	0	0
T4	194392	194384	0	0
T5	21081	8026	0	0
T6	296496	296490	0	0
T17	112713	112655	0	0
T18	49707	49640	0	0
T19	15540	15459	0	0
T20	2713	2628	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T13
1	0	Covered	T4,T21,T22
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T21,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T21,T22

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T22,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T21,T22
1	0	1	Covered	T27,T70,T86
1	1	0	Covered	T1,T6,T21
1	1	1	Covered	T21,T25,T26

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T25,T26
0	1	Covered	T27,T69,T74
1	0	Covered	T25,T28,T45

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T21,T25,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T28,T45

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T25,T26
1	0	Not Covered
1	1	Covered	T27,T69,T74

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T22,T8
1	Covered	T7,T9,T27

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T8
1	Covered	T22,T25,T27

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T22,T7
1	Covered	T14,T27,T86

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T22,T7,T9
1	Covered	T4,T8,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T5,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T4,T7,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T22,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T4,T7,T25

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T22,T7
Phase1St	198	Covered	T4,T22,T7
Phase2St	215	Covered	T4,T22,T7
Phase3St	233	Covered	T4,T22,T7
TerminalSt	249	Covered	T4,T22,T7
TimeoutSt	159	Covered	T21,T25,T26

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T12,T13
IdleSt->Phase0St	152	Covered	T4,T22,T7
IdleSt->TimeoutSt	159	Covered	T21,T25,T26
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T95,T96,T59
Phase0St->Phase1St	198	Covered	T4,T22,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T32,T34,T97
Phase1St->Phase2St	215	Covered	T4,T22,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T34,T80,T98
Phase2St->Phase3St	233	Covered	T4,T22,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T47,T99
Phase3St->TerminalSt	249	Covered	T4,T22,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T25,T27,T69
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T21,T25,T26
TimeoutSt->Phase0St	172	Covered	T25,T27,T69

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T22,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T25,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T27,T69
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T25,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T25,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T96,T59,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T22,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T22,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T34,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T22,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T22,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T34,T80,T98
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T22,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T22,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T47,T99
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T22,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T22,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T25,T69,T70
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T22,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	699378160	284	0	0
CheckAccumTrig0_A	699378160	495	0	0
CheckAccumTrig1_A	699378160	21	0	0
CheckClr_A	699378160	223	0	0
CheckEn_A	699066942	333326047	0	0
CheckPhase0_A	699378160	563	0	0
CheckPhase1_A	699378160	554	0	0
CheckPhase2_A	699378160	547	0	0
CheckPhase3_A	699378160	536	0	0
CheckTimeout0_A	699378160	1321	0	0
CheckTimeoutSt1_A	699378160	147712	0	0
CheckTimeoutSt2_A	699378160	1244	0	0
CheckTimeoutStTrig_A	699378160	55	0	0
ErrorStAllEscAsserted_A	699378160	1452	0	0
ErrorStIsTerminal_A	699378160	1212	0	0
EscStateOut_A	699064235	698994223	0	0
u_state_regs_A	699378160	699206548	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	284	0	0
T5	21081	50	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T12	0	61	0	0
T13	0	26	0	0
T14	111304	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T40	0	89	0	0
T41	0	58	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	495	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	1	0	0
T23	15664	0	0	0
T27	0	4	0	0
T70	0	3	0	0
T86	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	21	0	0
T11	751459	0	0	0
T15	255164	0	0	0
T16	104173	0	0	0
T25	83780	1	0	0
T26	75603	0	0	0
T27	546321	0	0	0
T42	47306	0	0	0
T45	0	1	0	0
T53	0	1	0	0
T60	42846	0	0	0
T61	37713	0	0	0
T62	548556	0	0	0
T79	0	1	0	0
T89	0	1	0	0
T96	0	1	0	0
T98	0	2	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	223	0	0
T11	751459	0	0	0
T15	255164	0	0	0
T16	104173	0	0	0
T25	83780	1	0	0
T26	75603	0	0	0
T27	546321	1	0	0
T28	0	3	0	0
T32	0	1	0	0
T33	0	1	0	0
T42	47306	0	0	0
T44	0	1	0	0
T45	0	3	0	0
T60	42846	0	0	0
T61	37713	0	0	0
T62	548556	0	0	0
T63	0	2	0	0
T69	0	2	0	0
T70	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699066942	333326047	0	0
T1	26740	26673	0	0
T2	66330	66231	0	0
T3	25960	24902	0	0
T4	194392	9180	0	0
T5	338	266	0	0
T6	296496	295443	0	0
T17	112713	112654	0	0
T18	49707	49639	0	0
T19	15540	15458	0	0
T20	2713	2627	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	563	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	1	0	0
T23	15664	0	0	0
T25	0	1	0	0
T27	0	5	0	0
T69	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	554	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	1	0	0
T23	15664	0	0	0
T25	0	1	0	0
T27	0	5	0	0
T69	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	547	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	1	0	0
T23	15664	0	0	0
T25	0	1	0	0
T27	0	5	0	0
T69	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	536	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	1	0	0
T23	15664	0	0	0
T25	0	1	0	0
T27	0	4	0	0
T69	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1321	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T10	133745	0	0	0
T14	111304	0	0	0
T15	255164	0	0	0
T21	32434	1	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T25	83780	2	0	0
T26	0	5	0	0
T27	0	38	0	0
T28	0	2	0	0
T37	0	1	0	0
T63	0	4	0	0
T69	0	3	0	0
T72	0	1	0	0
T74	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	147712	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T10	133745	0	0	0
T14	111304	0	0	0
T15	255164	0	0	0
T21	32434	154	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T25	83780	52	0	0
T26	0	817	0	0
T27	0	3813	0	0
T28	0	155	0	0
T37	0	59	0	0
T63	0	179	0	0
T69	0	159	0	0
T72	0	74	0	0
T74	0	64	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1244	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T10	133745	0	0	0
T14	111304	0	0	0
T15	255164	0	0	0
T21	32434	1	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T25	83780	1	0	0
T26	0	5	0	0
T27	0	37	0	0
T28	0	2	0	0
T37	0	1	0	0
T45	0	2	0	0
T63	0	4	0	0
T72	0	1	0	0
T76	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	55	0	0
T27	546321	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	6261	0	0	0
T39	0	2	0	0
T62	548556	0	0	0
T69	77252	3	0	0
T70	112449	0	0	0
T72	3392	0	0	0
T74	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	72904	0	0	0
T84	121030	0	0	0
T85	115504	0	0	0
T86	56182	0	0	0
T104	0	2	0	0
T105	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1452	0	0
T5	21081	175	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T12	0	379	0	0
T13	0	194	0	0
T14	111304	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T40	0	366	0	0
T41	0	338	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1212	0	0
T5	21081	145	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T12	0	319	0	0
T13	0	164	0	0
T14	111304	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T40	0	306	0	0
T41	0	278	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699064235	698994223	0	0
T1	26740	26674	0	0
T2	66330	66232	0	0
T3	25960	25903	0	0
T4	194392	194384	0	0
T5	71	0	0	0
T6	296496	296490	0	0
T17	112713	112655	0	0
T18	49707	49640	0	0
T19	15540	15459	0	0
T20	2713	2628	0	0
T21	0	32338	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	699206548	0	0
T1	26740	26674	0	0
T2	66330	66232	0	0
T3	25960	25903	0	0
T4	194392	194384	0	0
T5	21081	8026	0	0
T6	296496	296490	0	0
T17	112713	112655	0	0
T18	49707	49640	0	0
T19	15540	15459	0	0
T20	2713	2628	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T22
1	1	0	Covered	T22,T26,T27
1	1	1	Covered	T1,T17,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T18
0	1	Covered	T27,T43,T75
1	0	Covered	T25,T27,T44

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T17,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T27,T44

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T29
1	1	Covered	T27,T43,T75

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T22,T8

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T36,T70

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T19
1	Covered	T1,T3,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T5,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T2,T4,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T1,T4,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T2,T3,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T2,T3,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T17,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T17,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T38,T106
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T81,T39,T53
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T35,T107
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T36,T33
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T17,T18
TimeoutSt->Phase0St	172	Covered	T25,T27,T43

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T27,T43
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T38,T106
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T39,T53,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T35,T107
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T36,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	699378160	279	0	0
CheckAccumTrig0_A	699378160	896	0	0
CheckAccumTrig1_A	699378160	41	0	0
CheckClr_A	699378160	441	0	0
CheckEn_A	699066942	258765655	0	0
CheckPhase0_A	699378160	996	0	0
CheckPhase1_A	699378160	975	0	0
CheckPhase2_A	699378160	951	0	0
CheckPhase3_A	699378160	933	0	0
CheckTimeout0_A	699378160	1020	0	0
CheckTimeoutSt1_A	699378160	118832	0	0
CheckTimeoutSt2_A	699378160	904	0	0
CheckTimeoutStTrig_A	699378160	71	0	0
ErrorStAllEscAsserted_A	699378160	1435	0	0
ErrorStIsTerminal_A	699378160	1195	0	0
EscStateOut_A	699064235	698994223	0	0
u_state_regs_A	699378160	699206548	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	279	0	0
T5	21081	38	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T12	0	64	0	0
T13	0	39	0	0
T14	111304	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T40	0	66	0	0
T41	0	72	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	896	0	0
T1	26740	5	0	0
T2	66330	2	0	0
T3	25960	1	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	1	0	0
T18	49707	1	0	0
T19	15540	2	0	0
T20	2713	1	0	0
T22	0	8	0	0
T23	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	41	0	0
T11	751459	0	0	0
T15	255164	0	0	0
T16	104173	0	0	0
T25	83780	1	0	0
T26	75603	0	0	0
T27	546321	1	0	0
T42	47306	0	0	0
T44	0	1	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T60	42846	0	0	0
T61	37713	0	0	0
T62	548556	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	441	0	0
T1	26740	4	0	0
T2	66330	1	0	0
T3	25960	0	0	0
T4	194392	0	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T15	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	1	0	0
T20	2713	0	0	0
T22	0	6	0	0
T23	0	1	0	0
T27	0	9	0	0
T36	0	1	0	0
T60	0	2	0	0
T70	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699066942	258765655	0	0
T1	26740	582	0	0
T2	66330	2074	0	0
T3	25960	1598	0	0
T4	194392	2348	0	0
T5	338	266	0	0
T6	296496	296490	0	0
T17	112713	3048	0	0
T18	49707	2015	0	0
T19	15540	582	0	0
T20	2713	582	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	996	0	0
T1	26740	5	0	0
T2	66330	2	0	0
T3	25960	1	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	1	0	0
T18	49707	1	0	0
T19	15540	2	0	0
T20	2713	1	0	0
T22	0	8	0	0
T23	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	975	0	0
T1	26740	5	0	0
T2	66330	2	0	0
T3	25960	1	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	1	0	0
T18	49707	1	0	0
T19	15540	2	0	0
T20	2713	1	0	0
T22	0	8	0	0
T23	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	951	0	0
T1	26740	5	0	0
T2	66330	2	0	0
T3	25960	1	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	1	0	0
T18	49707	1	0	0
T19	15540	2	0	0
T20	2713	1	0	0
T22	0	8	0	0
T23	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	933	0	0
T1	26740	5	0	0
T2	66330	2	0	0
T3	25960	1	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	1	0	0
T18	49707	1	0	0
T19	15540	2	0	0
T20	2713	1	0	0
T22	0	8	0	0
T23	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1020	0	0
T1	26740	2	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	0	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	1	0	0
T18	49707	1	0	0
T19	15540	1	0	0
T20	2713	0	0	0
T21	0	7	0	0
T25	0	1	0	0
T27	0	2	0	0
T28	0	164	0	0
T61	0	3	0	0
T73	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	118832	0	0
T1	26740	30	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	0	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	176	0	0
T18	49707	131	0	0
T19	15540	21	0	0
T20	2713	0	0	0
T21	0	560	0	0
T25	0	1	0	0
T27	0	70	0	0
T28	0	10418	0	0
T61	0	285	0	0
T73	0	540	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	904	0	0
T1	26740	2	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	0	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	1	0	0
T18	49707	1	0	0
T19	15540	1	0	0
T20	2713	0	0	0
T21	0	7	0	0
T28	0	164	0	0
T43	0	2	0	0
T61	0	3	0	0
T73	0	1	0	0
T75	0	38	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	71	0	0
T27	546321	1	0	0
T36	6261	0	0	0
T39	0	1	0	0
T43	0	2	0	0
T62	548556	0	0	0
T69	77252	0	0	0
T70	112449	0	0	0
T72	3392	0	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	72904	0	0	0
T84	121030	0	0	0
T85	115504	0	0	0
T86	56182	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1435	0	0
T5	21081	178	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T12	0	357	0	0
T13	0	176	0	0
T14	111304	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T40	0	347	0	0
T41	0	377	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1195	0	0
T5	21081	148	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T12	0	297	0	0
T13	0	146	0	0
T14	111304	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T40	0	287	0	0
T41	0	317	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699064235	698994223	0	0
T1	26740	26674	0	0
T2	66330	66232	0	0
T3	25960	25903	0	0
T4	194392	194384	0	0
T5	71	0	0	0
T6	296496	296490	0	0
T17	112713	112655	0	0
T18	49707	49640	0	0
T19	15540	15459	0	0
T20	2713	2628	0	0
T21	0	32338	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	699206548	0	0
T1	26740	26674	0	0
T2	66330	66232	0	0
T3	25960	25903	0	0
T4	194392	194384	0	0
T5	21081	8026	0	0
T6	296496	296490	0	0
T17	112713	112655	0	0
T18	49707	49640	0	0
T19	15540	15459	0	0
T20	2713	2628	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T13
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T24
1	1	1	Covered	T1,T4,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T21
1	0	1	Covered	T9,T15,T11
1	1	0	Covered	T21,T22,T27
1	1	1	Covered	T1,T21,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T21,T22
0	1	Covered	T1,T22,T25
1	0	Covered	T25,T61,T28

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T21,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T61,T28

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T22
1	0	Not Covered
1	1	Covered	T1,T22,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T6,T8,T25

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T22
1	Covered	T1,T4,T9

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T22,T15,T42

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T42,T27

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T5,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T1,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T1,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T1,T6,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Covered	T1,T22,T25

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T6
Phase1St	198	Covered	T1,T4,T6
Phase2St	215	Covered	T1,T4,T6
Phase3St	233	Covered	T1,T4,T6
TerminalSt	249	Covered	T1,T4,T6
TimeoutSt	159	Covered	T1,T21,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T12,T13
IdleSt->Phase0St	152	Covered	T1,T4,T6
IdleSt->TimeoutSt	159	Covered	T1,T21,T22
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T109,T54
Phase0St->Phase1St	198	Covered	T1,T4,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T28,T110,T108
Phase1St->Phase2St	215	Covered	T1,T4,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T22,T28,T80
Phase2St->Phase3St	233	Covered	T1,T4,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T111,T34,T105
Phase3St->TerminalSt	249	Covered	T1,T4,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T25,T42
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T21,T22
TimeoutSt->Phase0St	172	Covered	T1,T22,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T109,T54
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T110,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T22,T28,T80
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T111,T34,T105
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T25,T42
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	699378160	250	0	0
CheckAccumTrig0_A	699378160	529	0	0
CheckAccumTrig1_A	699378160	16	0	0
CheckClr_A	699378160	260	0	0
CheckEn_A	699066942	309387879	0	0
CheckPhase0_A	699378160	598	0	0
CheckPhase1_A	699378160	590	0	0
CheckPhase2_A	699378160	575	0	0
CheckPhase3_A	699378160	563	0	0
CheckTimeout0_A	699378160	830	0	0
CheckTimeoutSt1_A	699378160	104697	0	0
CheckTimeoutSt2_A	699378160	754	0	0
CheckTimeoutStTrig_A	699378160	60	0	0
ErrorStAllEscAsserted_A	699378160	1379	0	0
ErrorStIsTerminal_A	699378160	1139	0	0
EscStateOut_A	699064235	698994223	0	0
u_state_regs_A	699378160	699206548	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	250	0	0
T5	21081	43	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T12	0	78	0	0
T13	0	40	0	0
T14	111304	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T40	0	41	0	0
T41	0	48	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	529	0	0
T1	26740	1	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T15	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T27	0	2	0	0
T42	0	3	0	0
T61	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	16	0	0
T11	751459	0	0	0
T15	255164	0	0	0
T16	104173	0	0	0
T25	83780	1	0	0
T26	75603	0	0	0
T27	546321	0	0	0
T28	0	1	0	0
T42	47306	0	0	0
T44	0	1	0	0
T52	0	2	0	0
T60	42846	0	0	0
T61	37713	1	0	0
T62	548556	0	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	260	0	0
T1	26740	1	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	0	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T22	0	1	0	0
T25	0	1	0	0
T27	0	1	0	0
T28	0	8	0	0
T42	0	2	0	0
T61	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699066942	309387879	0	0
T1	26740	594	0	0
T2	66330	66231	0	0
T3	25960	24902	0	0
T4	194392	9197	0	0
T5	338	266	0	0
T6	296496	9586	0	0
T17	112713	112654	0	0
T18	49707	49639	0	0
T19	15540	15458	0	0
T20	2713	2627	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	598	0	0
T1	26740	2	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T15	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T22	0	2	0	0
T25	0	2	0	0
T42	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	590	0	0
T1	26740	2	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T15	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T22	0	2	0	0
T25	0	2	0	0
T42	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	575	0	0
T1	26740	2	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T15	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T22	0	1	0	0
T25	0	2	0	0
T42	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	563	0	0
T1	26740	2	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	1	0	0
T5	21081	0	0	0
T6	296496	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T15	0	1	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T22	0	1	0	0
T25	0	2	0	0
T42	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	830	0	0
T1	26740	2	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	0	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	0	1	0	0
T22	0	3	0	0
T25	0	3	0	0
T26	0	9	0	0
T27	0	9	0	0
T28	0	5	0	0
T42	0	1	0	0
T43	0	1	0	0
T61	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	104697	0	0
T1	26740	735	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	0	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	0	141	0	0
T22	0	968	0	0
T25	0	680	0	0
T26	0	1360	0	0
T27	0	1796	0	0
T28	0	1614	0	0
T42	0	135	0	0
T43	0	330	0	0
T61	0	44	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	754	0	0
T1	26740	1	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	0	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	0	1	0	0
T26	0	9	0	0
T27	0	9	0	0
T28	0	3	0	0
T42	0	1	0	0
T61	0	1	0	0
T75	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	60	0	0
T1	26740	1	0	0
T2	66330	0	0	0
T3	25960	0	0	0
T4	194392	0	0	0
T5	21081	0	0	0
T6	296496	0	0	0
T17	112713	0	0	0
T18	49707	0	0	0
T19	15540	0	0	0
T20	2713	0	0	0
T22	0	2	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T63	0	1	0	0
T78	0	1	0	0
T105	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1379	0	0
T5	21081	171	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T12	0	364	0	0
T13	0	173	0	0
T14	111304	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T40	0	331	0	0
T41	0	340	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	1139	0	0
T5	21081	141	0	0
T6	296496	0	0	0
T7	201519	0	0	0
T8	101836	0	0	0
T9	407744	0	0	0
T12	0	304	0	0
T13	0	143	0	0
T14	111304	0	0	0
T20	2713	0	0	0
T21	32434	0	0	0
T22	372096	0	0	0
T23	15664	0	0	0
T40	0	271	0	0
T41	0	280	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699064235	698994223	0	0
T1	26740	26674	0	0
T2	66330	66232	0	0
T3	25960	25903	0	0
T4	194392	194384	0	0
T5	71	0	0	0
T6	296496	296490	0	0
T17	112713	112655	0	0
T18	49707	49640	0	0
T19	15540	15459	0	0
T20	2713	2628	0	0
T21	0	32338	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699378160	699206548	0	0
T1	26740	26674	0	0
T2	66330	66232	0	0
T3	25960	25903	0	0
T4	194392	194384	0	0
T5	21081	8026	0	0
T6	296496	296490	0	0
T17	112713	112655	0	0
T18	49707	49640	0	0
T19	15540	15459	0	0
T20	2713	2628	0	0