Unified Coverage Report :: Module :: prim_flop

Module : prim_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_flop_0/prim_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_wrap.u_reg.u_classa_clr_shadowed0_qe
tb.dut.u_reg_wrap.u_reg.u_classb_clr_shadowed0_qe
tb.dut.u_reg_wrap.u_reg.u_classc_clr_shadowed0_qe
tb.dut.u_reg_wrap.u_reg.u_classd_clr_shadowed0_qe
tb.dut.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_ping_timer.u_state_regs.u_state_flop
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.u_state_flop
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.u_state_flop
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.u_state_flop
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.u_state_flop

---

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classa_clr_shadowed0_qe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	100.00	96.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classb_clr_shadowed0_qe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	100.00	96.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_clr_shadowed0_qe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	100.00	96.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_clr_shadowed0_qe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	100.00	96.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_ping_timer.u_state_regs.u_state_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_state_regs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

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Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

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100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer.u_state_regs.u_state_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_state_regs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer.u_state_regs.u_state_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_state_regs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer.u_state_regs.u_state_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_state_regs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer.u_state_regs.u_state_flop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_state_regs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00				100.00