Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 64253542 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 30963761 1 T1 142268 T2 2383 T3 2199



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 14298456 1 T1 55789 T2 1143 T3 818
values[0x0] 39654986 1 T1 198768 T2 3183 T3 2972
values[0x1] 41263861 1 T1 198258 T2 3197 T3 2984



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 55132601 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 40084702 1 T1 179949 T2 2992 T3 2789



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 294969 1 T1 1693 T2 21 T3 21
valid_sources[0x01] 298628 1 T1 1637 T2 32 T3 18
valid_sources[0x02] 297804 1 T1 1796 T2 30 T3 19
valid_sources[0x03] 299681 1 T1 1783 T2 48 T3 22
valid_sources[0x04] 311616 1 T1 1792 T2 31 T3 37
valid_sources[0x05] 755089 1 T1 1820 T2 29 T3 26
valid_sources[0x06] 293779 1 T1 1799 T2 38 T3 30
valid_sources[0x07] 657826 1 T1 1728 T2 23 T3 23
valid_sources[0x08] 302616 1 T1 1951 T2 36 T3 36
valid_sources[0x09] 298611 1 T1 1830 T2 24 T3 18
valid_sources[0x0a] 301877 1 T1 1694 T2 30 T3 26
valid_sources[0x0b] 291665 1 T1 1846 T2 20 T3 31
valid_sources[0x0c] 295793 1 T1 1839 T2 20 T3 21
valid_sources[0x0d] 294749 1 T1 1736 T2 41 T3 31
valid_sources[0x0e] 304965 1 T1 1864 T2 25 T3 17
valid_sources[0x0f] 304887 1 T1 1819 T2 26 T3 31
valid_sources[0x10] 304440 1 T1 1643 T2 32 T3 30
valid_sources[0x11] 296341 1 T1 1770 T2 32 T3 33
valid_sources[0x12] 292584 1 T1 1822 T2 29 T3 31
valid_sources[0x13] 301580 1 T1 1872 T2 41 T3 20
valid_sources[0x14] 302390 1 T1 1732 T2 28 T3 18
valid_sources[0x15] 296597 1 T1 1807 T2 31 T3 23
valid_sources[0x16] 738563 1 T1 1808 T2 13 T3 20
valid_sources[0x17] 296444 1 T1 2038 T2 26 T3 30
valid_sources[0x18] 304847 1 T1 1760 T2 23 T3 35
valid_sources[0x19] 314284 1 T1 1811 T2 37 T3 25
valid_sources[0x1a] 293113 1 T1 1855 T2 31 T3 16
valid_sources[0x1b] 295596 1 T1 1909 T2 24 T3 26
valid_sources[0x1c] 292097 1 T1 1726 T2 27 T3 16
valid_sources[0x1d] 725115 1 T1 1760 T2 28 T3 25
valid_sources[0x1e] 299119 1 T1 1782 T2 22 T3 40
valid_sources[0x1f] 293697 1 T1 1715 T2 20 T3 23
valid_sources[0x20] 305108 1 T1 1658 T2 19 T3 30
valid_sources[0x21] 303009 1 T1 1753 T2 24 T3 26
valid_sources[0x22] 650258 1 T1 1857 T2 29 T3 16
valid_sources[0x23] 744118 1 T1 1770 T2 27 T3 30
valid_sources[0x24] 299224 1 T1 1722 T2 33 T3 22
valid_sources[0x25] 292893 1 T1 1855 T2 36 T3 14
valid_sources[0x26] 309993 1 T1 1696 T2 21 T3 21
valid_sources[0x27] 298479 1 T1 1868 T2 20 T3 27
valid_sources[0x28] 304699 1 T1 1756 T2 25 T3 21
valid_sources[0x29] 597619 1 T1 1946 T2 20 T3 25
valid_sources[0x2a] 318486 1 T1 1729 T2 32 T3 18
valid_sources[0x2b] 302916 1 T1 1794 T2 17 T3 24
valid_sources[0x2c] 305865 1 T1 1848 T2 18 T3 22
valid_sources[0x2d] 301613 1 T1 1692 T2 25 T3 39
valid_sources[0x2e] 301087 1 T1 1783 T2 34 T3 24
valid_sources[0x2f] 296485 1 T1 1763 T2 28 T3 29
valid_sources[0x30] 301705 1 T1 1815 T2 40 T3 17
valid_sources[0x31] 300419 1 T1 1688 T2 32 T3 31
valid_sources[0x32] 295073 1 T1 1757 T2 32 T3 12
valid_sources[0x33] 304490 1 T1 1764 T2 40 T3 33
valid_sources[0x34] 774276 1 T1 1580 T2 38 T3 26
valid_sources[0x35] 312487 1 T1 1751 T2 30 T3 34
valid_sources[0x36] 298345 1 T1 1681 T2 30 T3 19
valid_sources[0x37] 290629 1 T1 1686 T2 18 T3 41
valid_sources[0x38] 308835 1 T1 1901 T2 27 T3 27
valid_sources[0x39] 613761 1 T1 1684 T2 26 T3 30
valid_sources[0x3a] 1166878 1 T1 1807 T2 23 T3 24
valid_sources[0x3b] 303159 1 T1 1856 T2 33 T3 24
valid_sources[0x3c] 290772 1 T1 1805 T2 41 T3 30
valid_sources[0x3d] 712322 1 T1 1738 T2 39 T3 18
valid_sources[0x3e] 675405 1 T1 1800 T2 28 T3 26
valid_sources[0x3f] 301638 1 T1 1675 T2 23 T3 37
valid_sources[0x40] 293496 1 T1 1872 T2 26 T3 34
valid_sources[0x41] 736890 1 T1 1788 T2 13 T3 27
valid_sources[0x42] 575609 1 T1 1911 T2 31 T3 21
valid_sources[0x43] 324199 1 T1 1764 T2 32 T3 36
valid_sources[0x44] 312375 1 T1 1767 T2 33 T3 19
valid_sources[0x45] 301268 1 T1 1799 T2 29 T3 36
valid_sources[0x46] 307406 1 T1 1776 T2 40 T3 15
valid_sources[0x47] 297593 1 T1 1796 T2 37 T3 24
valid_sources[0x48] 301494 1 T1 1760 T2 32 T3 27
valid_sources[0x49] 304560 1 T1 1771 T2 32 T3 25
valid_sources[0x4a] 299640 1 T1 1869 T2 32 T3 34
valid_sources[0x4b] 298954 1 T1 1700 T2 33 T3 39
valid_sources[0x4c] 290677 1 T1 1695 T2 37 T3 20
valid_sources[0x4d] 326749 1 T1 1721 T2 17 T3 20
valid_sources[0x4e] 293991 1 T1 1687 T2 27 T3 26
valid_sources[0x4f] 1084284 1 T1 1689 T2 32 T3 30
valid_sources[0x50] 296939 1 T1 1672 T2 25 T3 29
valid_sources[0x51] 304409 1 T1 1768 T2 13 T3 15
valid_sources[0x52] 300471 1 T1 1740 T2 32 T3 20
valid_sources[0x53] 300325 1 T1 1736 T2 28 T3 21
valid_sources[0x54] 297781 1 T1 1817 T2 13 T3 34
valid_sources[0x55] 300945 1 T1 1597 T2 30 T3 18
valid_sources[0x56] 297312 1 T1 1847 T2 24 T3 24
valid_sources[0x57] 300505 1 T1 1891 T2 26 T3 42
valid_sources[0x58] 294122 1 T1 1899 T2 31 T3 24
valid_sources[0x59] 309230 1 T1 1767 T2 32 T3 32
valid_sources[0x5a] 303417 1 T1 1791 T2 27 T3 23
valid_sources[0x5b] 310330 1 T1 1879 T2 24 T3 29
valid_sources[0x5c] 305709 1 T1 1640 T2 37 T3 30
valid_sources[0x5d] 335059 1 T1 1689 T2 35 T3 10
valid_sources[0x5e] 294689 1 T1 1778 T2 32 T3 34
valid_sources[0x5f] 296928 1 T1 1755 T2 26 T3 22
valid_sources[0x60] 307153 1 T1 1713 T2 36 T3 37
valid_sources[0x61] 299725 1 T1 1593 T2 24 T3 32
valid_sources[0x62] 302674 1 T1 1735 T2 27 T3 17
valid_sources[0x63] 302300 1 T1 1714 T2 34 T3 14
valid_sources[0x64] 320057 1 T1 1777 T2 28 T3 14
valid_sources[0x65] 740770 1 T1 1958 T2 37 T3 29
valid_sources[0x66] 299259 1 T1 1850 T2 27 T3 22
valid_sources[0x67] 297797 1 T1 1708 T2 38 T3 28
valid_sources[0x68] 297728 1 T1 1727 T2 34 T3 20
valid_sources[0x69] 300888 1 T1 1593 T2 21 T3 16
valid_sources[0x6a] 317683 1 T1 1642 T2 23 T3 31
valid_sources[0x6b] 719043 1 T1 1617 T2 19 T3 36
valid_sources[0x6c] 314784 1 T1 1630 T2 36 T3 24
valid_sources[0x6d] 297115 1 T1 1809 T2 24 T3 16
valid_sources[0x6e] 303172 1 T1 1810 T2 33 T3 19
valid_sources[0x6f] 303525 1 T1 1562 T2 38 T3 25
valid_sources[0x70] 633467 1 T1 1847 T2 54 T3 29
valid_sources[0x71] 587471 1 T1 1738 T2 34 T3 36
valid_sources[0x72] 311034 1 T1 1917 T2 27 T3 18
valid_sources[0x73] 300818 1 T1 1769 T2 14 T3 34
valid_sources[0x74] 307228 1 T1 1774 T2 30 T3 21
valid_sources[0x75] 331940 1 T1 1765 T2 44 T3 26
valid_sources[0x76] 289644 1 T1 1744 T2 31 T3 32
valid_sources[0x77] 302280 1 T1 1718 T2 27 T3 18
valid_sources[0x78] 547760 1 T1 1877 T2 16 T3 24
valid_sources[0x79] 295915 1 T1 1701 T2 34 T3 45
valid_sources[0x7a] 744172 1 T1 1707 T2 35 T3 37
valid_sources[0x7b] 299742 1 T1 1926 T2 22 T3 33
valid_sources[0x7c] 292050 1 T1 1752 T2 34 T3 20
valid_sources[0x7d] 296252 1 T1 1741 T2 32 T3 27
valid_sources[0x7e] 340633 1 T1 1746 T2 27 T3 15
valid_sources[0x7f] 318084 1 T1 1747 T2 31 T3 27
valid_sources[0x80] 300431 1 T1 1761 T2 25 T3 30



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7088182 1 T1 27828 T2 551 T3 410
values[0x0] all_enables biggest_size 15100208 1 T1 73167 T2 1149 T3 1111
values[0x1] all_enables biggest_size 8775371 1 T1 41273 T2 683 T3 678

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%