Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T41,T42
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14761	0	0
DisabledNoTrigBkwd_A	2147483647	818613	0	0
DisabledNoTrigFwd_A	2147483647	1418639187	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14761	0	0
T14	142699	0	0	0
T15	253234	0	0	0
T16	277726	0	0	0
T17	1145066	0	0	0
T18	402522	0	0	0
T21	0	1093	0	0
T22	1802926	0	0	0
T24	122702	0	0	0
T41	1223	455	0	0
T42	6410	327	0	0
T43	64546	0	0	0
T44	114042	0	0	0
T55	154556	0	0	0
T69	0	160	0	0
T70	41404	0	0	0
T110	0	338	0	0
T192	0	280	0	0
T193	4128	526	0	0
T194	0	522	0	0
T195	0	618	0	0
T196	0	409	0	0
T197	0	1838	0	0
T198	0	799	0	0
T199	0	519	0	0
T200	0	869	0	0
T201	0	733	0	0
T202	0	858	0	0
T203	0	462	0	0
T204	0	1251	0	0
T205	0	2124	0	0
T206	0	580	0	0
T207	6732	0	0	0
T208	133964	0	0	0
T209	48614	0	0	0
T210	123800	0	0	0
T211	47665	0	0	0
T212	409118	0	0	0
T213	312126	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	818613	0	0
T1	400212	2753	0	0
T2	279462	36	0	0
T3	74100	10	0	0
T4	1565116	782	0	0
T5	1755804	3226	0	0
T6	469720	2650	0	0
T13	3066316	6164	0	0
T14	0	2116	0	0
T15	0	6518	0	0
T16	0	5078	0	0
T17	0	5126	0	0
T18	0	1199	0	0
T19	147968	53	0	0
T20	410224	22	0	0
T21	8104	40	0	0
T22	0	273	0	0
T23	190320	0	0	0
T24	0	3	0	0
T41	1223	24	0	0
T42	0	2	0	0
T43	0	80	0	0
T44	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1418639187	0	0
T1	1600848	1209917	0	0
T2	372616	262560	0	0
T3	74100	54711	0	0
T4	1565116	1171010	0	0
T5	1755804	1409693	0	0
T6	469720	238019	0	0
T13	3066316	2323955	0	0
T19	147968	93870	0	0
T20	410224	309491	0	0
T21	8104	2788	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T19
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T42,T110,T198
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T19,T20

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	655097595	3588	0	0
DisabledNoTrigBkwd_A	655097595	204858	0	0
DisabledNoTrigFwd_A	655097595	296253826	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	3588	0	0
T15	126617	0	0	0
T16	138863	0	0	0
T17	572533	0	0	0
T18	402522	0	0	0
T22	901463	0	0	0
T24	61351	0	0	0
T42	3205	327	0	0
T43	32273	0	0	0
T44	57021	0	0	0
T70	41404	0	0	0
T110	0	338	0	0
T198	0	799	0	0
T205	0	2124	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	204858	0	0
T3	18525	10	0	0
T4	391279	0	0	0
T5	438951	1155	0	0
T6	117430	0	0	0
T13	766579	2298	0	0
T16	0	50	0	0
T19	36992	9	0	0
T20	102556	22	0	0
T21	2026	0	0	0
T23	63440	0	0	0
T24	0	3	0	0
T41	1223	0	0	0
T42	0	2	0	0
T43	0	80	0	0
T44	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	296253826	0	0
T1	400212	399698	0	0
T2	93154	86623	0	0
T3	18525	615	0	0
T4	391279	391271	0	0
T5	438951	769925	0	0
T6	117430	117421	0	0
T13	766579	115376	0	0
T19	36992	21507	0	0
T20	102556	6059	0	0
T21	2026	691	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T192,T197
1	1	Covered	T1,T2,T19

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T19,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	655097595	5736	0	0
DisabledNoTrigBkwd_A	655097595	206378	0	0
DisabledNoTrigFwd_A	655097595	365650442	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	5736	0	0
T14	142699	0	0	0
T15	126617	0	0	0
T16	138863	0	0	0
T17	572533	0	0	0
T22	901463	0	0	0
T24	61351	0	0	0
T41	1223	455	0	0
T42	3205	0	0	0
T43	32273	0	0	0
T44	57021	0	0	0
T192	0	280	0	0
T197	0	1838	0	0
T199	0	519	0	0
T200	0	869	0	0
T201	0	733	0	0
T203	0	462	0	0
T206	0	580	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	206378	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	1073	0	0
T6	117430	626	0	0
T13	766579	3446	0	0
T15	0	2791	0	0
T16	0	1958	0	0
T18	0	1162	0	0
T19	36992	39	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T22	0	273	0	0
T23	63440	0	0	0
T41	0	24	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	365650442	0	0
T1	400212	399353	0	0
T2	93154	86844	0	0
T3	18525	18466	0	0
T4	391279	386276	0	0
T5	438951	101052	0	0
T6	117430	2583	0	0
T13	766579	831895	0	0
T19	36992	4009	0	0
T20	102556	98434	0	0
T21	2026	695	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T19
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T193,T195,T196
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	655097595	3662	0	0
DisabledNoTrigBkwd_A	655097595	198574	0	0
DisabledNoTrigFwd_A	655097595	375872319	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	3662	0	0
T55	154556	0	0	0
T193	4128	526	0	0
T195	0	618	0	0
T196	0	409	0	0
T202	0	858	0	0
T204	0	1251	0	0
T207	6732	0	0	0
T208	133964	0	0	0
T209	48614	0	0	0
T210	123800	0	0	0
T211	47665	0	0	0
T212	409118	0	0	0
T213	312126	0	0	0
T214	346174	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	198574	0	0
T1	400212	2753	0	0
T2	93154	32	0	0
T3	18525	0	0	0
T4	391279	782	0	0
T5	438951	540	0	0
T6	117430	0	0	0
T13	766579	171	0	0
T15	0	2097	0	0
T16	0	1068	0	0
T17	0	2775	0	0
T18	0	37	0	0
T19	36992	2	0	0
T20	102556	0	0	0
T21	2026	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	375872319	0	0
T1	400212	11718	0	0
T2	93154	3126	0	0
T3	18525	17164	0	0
T4	391279	2192	0	0
T5	438951	264074	0	0
T6	117430	117421	0	0
T13	766579	685950	0	0
T19	36992	33381	0	0
T20	102556	102499	0	0
T21	2026	699	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T69,T194
1	1	Covered	T1,T2,T19

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T19,T21

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	655097595	1775	0	0
DisabledNoTrigBkwd_A	655097595	208803	0	0
DisabledNoTrigFwd_A	655097595	380862600	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1775	0	0
T4	391279	0	0	0
T5	438951	0	0	0
T6	117430	0	0	0
T13	766579	0	0	0
T14	142699	0	0	0
T15	126617	0	0	0
T21	2026	1093	0	0
T23	63440	0	0	0
T41	1223	0	0	0
T42	3205	0	0	0
T69	0	160	0	0
T194	0	522	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	208803	0	0
T2	93154	3	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	458	0	0
T6	117430	2024	0	0
T13	766579	249	0	0
T14	0	2116	0	0
T15	0	1630	0	0
T16	0	2002	0	0
T17	0	2351	0	0
T19	36992	3	0	0
T20	102556	0	0	0
T21	2026	40	0	0
T23	63440	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	380862600	0	0
T1	400212	399148	0	0
T2	93154	85967	0	0
T3	18525	18466	0	0
T4	391279	391271	0	0
T5	438951	274642	0	0
T6	117430	594	0	0
T13	766579	690734	0	0
T19	36992	34973	0	0
T20	102556	102499	0	0
T21	2026	703	0	0