Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T19,T5
1	0	1	Covered	T1,T19,T21
1	1	0	Covered	T2,T3,T19
1	1	1	Covered	T2,T19,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T5
0	1	Covered	T5,T13,T23
1	0	Covered	T5,T13,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T19,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T13,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T5
1	0	Not Covered
1	1	Covered	T5,T13,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T2,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T5,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T19
1	Covered	T2,T3,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T5,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T19,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T19

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T2,T19,T5

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T2,T19,T5
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T6,T25,T26
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T26,T27,T28
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T19,T5,T13
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T2,T20,T29
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T19,T20
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T19,T5
TimeoutSt->Phase0St	172	Covered	T5,T13,T23

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T13,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T25,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T5,T13
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T20,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T19,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1330	0	0
CheckAccumTrig0_A	2147483647	2479	0	0
CheckAccumTrig1_A	2147483647	118	0	0
CheckClr_A	2147483647	1257	0	0
CheckEn_A	2147483647	1091409334	0	0
CheckPhase0_A	2147483647	2813	0	0
CheckPhase1_A	2147483647	2758	0	0
CheckPhase2_A	2147483647	2699	0	0
CheckPhase3_A	2147483647	2648	0	0
CheckTimeout0_A	2147483647	6425	0	0
CheckTimeoutSt1_A	2147483647	681852	0	0
CheckTimeoutSt2_A	2147483647	6057	0	0
CheckTimeoutStTrig_A	2147483647	248	0	0
ErrorStAllEscAsserted_A	2147483647	6588	0	0
ErrorStIsTerminal_A	2147483647	5508	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1330	0	0
T10	161920	237	0	0
T11	0	323	0	0
T12	0	282	0	0
T30	0	329	0	0
T31	0	159	0	0
T32	93536	0	0	0
T33	280168	0	0	0
T34	398688	0	0	0
T35	378696	0	0	0
T36	16104	0	0	0
T37	1659644	0	0	0
T38	444324	0	0	0
T39	167880	0	0	0
T40	785504	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2479	0	0
T1	400212	1	0	0
T2	279462	10	0	0
T3	74100	1	0	0
T4	1565116	1	0	0
T5	1755804	41	0	0
T6	469720	13	0	0
T13	3066316	28	0	0
T14	0	1	0	0
T15	0	3	0	0
T16	0	4	0	0
T17	0	4	0	0
T18	0	15	0	0
T19	147968	7	0	0
T20	410224	5	0	0
T21	8104	1	0	0
T22	0	2	0	0
T23	190320	0	0	0
T24	0	1	0	0
T41	1223	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118	0	0
T5	438951	1	0	0
T13	1533158	6	0	0
T14	285398	0	0	0
T15	253234	0	0	0
T16	277726	0	0	0
T23	126880	0	0	0
T24	61351	1	0	0
T27	0	2	0	0
T41	2446	0	0	0
T42	6410	0	0	0
T43	64546	0	0	0
T44	57021	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	498299	3	0	0
T50	565726	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	3	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	72524	0	0	0
T63	762167	0	0	0
T64	631883	0	0	0
T65	810904	0	0	0
T66	35269	0	0	0
T67	106260	0	0	0
T68	389238	0	0	0
T69	896	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1257	0	0
T2	186308	8	0	0
T3	37050	0	0	0
T4	1565116	0	0	0
T5	1755804	31	0	0
T6	469720	11	0	0
T13	3066316	15	0	0
T14	285398	0	0	0
T17	0	1	0	0
T18	0	12	0	0
T19	147968	4	0	0
T20	410224	4	0	0
T21	8104	0	0	0
T22	0	3	0	0
T23	253760	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T26	0	19	0	0
T27	0	6	0	0
T29	0	2	0	0
T41	2446	0	0	0
T70	0	4	0	0
T71	0	4	0	0
T72	0	3	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1091409334	0	0
T1	1600848	1209917	0	0
T2	372616	186180	0	0
T3	74100	54708	0	0
T4	1565116	1171010	0	0
T5	1755804	592199	0	0
T6	469720	238019	0	0
T13	3066316	2582256	0	0
T19	147968	43957	0	0
T20	410224	309488	0	0
T21	8104	2788	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2813	0	0
T1	400212	1	0	0
T2	279462	10	0	0
T3	74100	1	0	0
T4	1565116	1	0	0
T5	1755804	45	0	0
T6	469720	12	0	0
T13	3066316	37	0	0
T15	0	3	0	0
T16	0	4	0	0
T17	0	4	0	0
T18	0	7	0	0
T19	147968	7	0	0
T20	410224	5	0	0
T21	8104	1	0	0
T22	0	2	0	0
T23	190320	1	0	0
T24	0	2	0	0
T41	1223	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2758	0	0
T1	400212	1	0	0
T2	279462	10	0	0
T3	74100	1	0	0
T4	1565116	1	0	0
T5	1755804	45	0	0
T6	469720	11	0	0
T13	3066316	37	0	0
T15	0	3	0	0
T16	0	4	0	0
T17	0	3	0	0
T18	0	7	0	0
T19	147968	7	0	0
T20	410224	5	0	0
T21	8104	1	0	0
T22	0	2	0	0
T23	190320	1	0	0
T24	0	2	0	0
T41	1223	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2699	0	0
T1	400212	1	0	0
T2	279462	10	0	0
T3	74100	1	0	0
T4	1565116	1	0	0
T5	1755804	42	0	0
T6	469720	10	0	0
T13	3066316	36	0	0
T15	0	3	0	0
T16	0	4	0	0
T17	0	3	0	0
T18	0	7	0	0
T19	147968	6	0	0
T20	410224	5	0	0
T21	8104	1	0	0
T22	0	2	0	0
T23	190320	1	0	0
T24	0	2	0	0
T41	1223	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2648	0	0
T1	400212	1	0	0
T2	186308	8	0	0
T3	55575	1	0	0
T4	1565116	1	0	0
T5	1755804	37	0	0
T6	469720	2	0	0
T13	3066316	29	0	0
T14	142699	0	0	0
T15	0	2	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	0	7	0	0
T19	147968	5	0	0
T20	410224	4	0	0
T21	8104	0	0	0
T22	0	2	0	0
T23	190320	1	0	0
T24	0	2	0	0
T41	2446	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T70	0	5	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6425	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	782558	0	0	0
T5	1316853	5	0	0
T6	352290	3	0	0
T13	3066316	14	0	0
T14	428097	0	0	0
T15	253234	2	0	0
T16	277726	0	0	0
T18	0	7	0	0
T19	73984	2	0	0
T20	205112	0	0	0
T21	4052	0	0	0
T22	0	417	0	0
T23	253760	12	0	0
T24	61351	1	0	0
T26	0	22	0	0
T27	0	5	0	0
T41	3669	0	0	0
T42	6410	0	0	0
T43	64546	0	0	0
T44	57021	0	0	0
T45	0	1	0	0
T70	0	5	0	0
T71	0	2	0	0
T75	0	2	0	0
T77	0	2	0	0
T78	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	681852	0	0
T2	93154	202	0	0
T3	18525	0	0	0
T4	782558	0	0	0
T5	1316853	1005	0	0
T6	352290	130	0	0
T13	3066316	774	0	0
T14	428097	0	0	0
T15	253234	203	0	0
T16	277726	0	0	0
T18	0	1083	0	0
T19	73984	95	0	0
T20	205112	0	0	0
T21	4052	0	0	0
T22	0	17020	0	0
T23	253760	1436	0	0
T24	61351	0	0	0
T26	0	2537	0	0
T27	0	179	0	0
T41	3669	0	0	0
T42	6410	0	0	0
T43	64546	0	0	0
T44	57021	0	0	0
T45	0	125	0	0
T70	0	544	0	0
T71	0	205	0	0
T75	0	189	0	0
T77	0	256	0	0
T78	0	270	0	0
T79	0	58	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6057	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	782558	0	0	0
T5	1316853	1	0	0
T6	352290	3	0	0
T13	3066316	5	0	0
T14	428097	0	0	0
T15	253234	2	0	0
T16	277726	0	0	0
T18	0	5	0	0
T19	73984	2	0	0
T20	205112	0	0	0
T21	4052	0	0	0
T22	0	417	0	0
T23	253760	11	0	0
T24	61351	0	0	0
T26	0	18	0	0
T27	0	4	0	0
T32	0	4	0	0
T35	0	1	0	0
T41	3669	0	0	0
T42	6410	0	0	0
T43	64546	0	0	0
T44	57021	0	0	0
T45	0	1	0	0
T70	0	3	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	10	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	248	0	0
T5	877902	3	0	0
T6	234860	0	0	0
T13	1533158	3	0	0
T14	428097	0	0	0
T15	379851	0	0	0
T16	416589	0	0	0
T17	572533	0	0	0
T18	0	1	0	0
T23	190320	1	0	0
T24	61351	0	0	0
T26	346896	2	0	0
T27	525554	0	0	0
T28	383288	0	0	0
T35	0	1	0	0
T41	3669	0	0	0
T42	9615	0	0	0
T43	96819	0	0	0
T44	57021	0	0	0
T46	0	4	0	0
T62	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	21958	0	0	0
T79	27558	0	0	0
T81	0	1	0	0
T82	0	5	0	0
T83	0	2	0	0
T84	0	3	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	134948	0	0	0
T91	25124	0	0	0
T92	170467	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6588	0	0
T10	161920	1495	0	0
T11	0	1500	0	0
T12	0	1431	0	0
T30	0	1431	0	0
T31	0	731	0	0
T32	93536	0	0	0
T33	280168	0	0	0
T34	398688	0	0	0
T35	378696	0	0	0
T36	16104	0	0	0
T37	1659644	0	0	0
T38	444324	0	0	0
T39	167880	0	0	0
T40	785504	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5508	0	0
T10	161920	1255	0	0
T11	0	1260	0	0
T12	0	1191	0	0
T30	0	1191	0	0
T31	0	611	0	0
T32	93536	0	0	0
T33	280168	0	0	0
T34	398688	0	0	0
T35	378696	0	0	0
T36	16104	0	0	0
T37	1659644	0	0	0
T38	444324	0	0	0
T39	167880	0	0	0
T40	785504	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1600848	1600816	0	0
T2	372616	372312	0	0
T3	74100	73864	0	0
T4	1565116	1565084	0	0
T5	1755804	1755768	0	0
T6	469720	469684	0	0
T13	3066316	3066008	0	0
T19	147968	147596	0	0
T20	410224	409996	0	0
T21	8104	7716	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1600848	1600816	0	0
T2	372616	372312	0	0
T3	74100	73864	0	0
T4	1565116	1565084	0	0
T5	1755804	1755768	0	0
T6	469720	469684	0	0
T13	3066316	3066008	0	0
T19	147968	147596	0	0
T20	410224	409996	0	0
T21	8104	7716	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T19,T20

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T19,T5
1	0	1	Covered	T1,T19,T5
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T2,T19,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T5
0	1	Covered	T5,T13,T18
1	0	Covered	T13,T24,T27

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T19,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T13,T24,T27

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T5
1	0	Not Covered
1	1	Covered	T5,T13,T18

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T19,T20
1	Covered	T19,T13,T42

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T19,T20
1	Covered	T20,T13,T24

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T19,T20,T5
1	Covered	T3,T19,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T19,T20
1	Covered	T19,T5,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T19,T20,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T19,T5,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T19,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T20,T5,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T19,T20
Phase1St	198	Covered	T3,T19,T20
Phase2St	215	Covered	T3,T19,T20
Phase3St	233	Covered	T3,T19,T20
TerminalSt	249	Covered	T3,T19,T20
TimeoutSt	159	Covered	T2,T19,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T3,T19,T20
IdleSt->TimeoutSt	159	Covered	T2,T19,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T26,T28,T81
Phase0St->Phase1St	198	Covered	T3,T19,T20
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T27,T81,T93
Phase1St->Phase2St	215	Covered	T3,T19,T20
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T19,T5,T13
Phase2St->Phase3St	233	Covered	T3,T19,T20
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T20,T29,T93
Phase3St->TerminalSt	249	Covered	T3,T19,T20
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T19,T20,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T19,T13
TimeoutSt->Phase0St	172	Covered	T5,T13,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T13,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T28,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T19,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T19,T20,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T81,T93
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T19,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T19,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T5,T13
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T19,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T19,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T29,T93
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T19,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T19,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T20,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T19,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	655097595	331	0	0
CheckAccumTrig0_A	655097595	921	0	0
CheckAccumTrig1_A	655097595	52	0	0
CheckClr_A	655097595	493	0	0
CheckEn_A	654280250	229764528	0	0
CheckPhase0_A	655097595	1028	0	0
CheckPhase1_A	655097595	1003	0	0
CheckPhase2_A	655097595	976	0	0
CheckPhase3_A	655097595	958	0	0
CheckTimeout0_A	655097595	1620	0	0
CheckTimeoutSt1_A	655097595	168874	0	0
CheckTimeoutSt2_A	655097595	1502	0	0
CheckTimeoutStTrig_A	655097595	65	0	0
ErrorStAllEscAsserted_A	655097595	1680	0	0
ErrorStIsTerminal_A	655097595	1410	0	0
EscStateOut_A	654278676	654205473	0	0
u_state_regs_A	655097595	654909513	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	331	0	0
T10	40480	54	0	0
T11	0	83	0	0
T12	0	71	0	0
T30	0	77	0	0
T31	0	46	0	0
T32	23384	0	0	0
T33	70042	0	0	0
T34	99672	0	0	0
T35	94674	0	0	0
T36	4026	0	0	0
T37	414911	0	0	0
T38	111081	0	0	0
T39	41970	0	0	0
T40	196376	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	921	0	0
T3	18525	1	0	0
T4	391279	0	0	0
T5	438951	29	0	0
T6	117430	0	0	0
T13	766579	8	0	0
T16	0	1	0	0
T19	36992	4	0	0
T20	102556	5	0	0
T21	2026	0	0	0
T23	63440	0	0	0
T24	0	1	0	0
T41	1223	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	52	0	0
T13	766579	6	0	0
T14	142699	0	0	0
T15	126617	0	0	0
T16	138863	0	0	0
T23	63440	0	0	0
T24	61351	1	0	0
T27	0	2	0	0
T41	1223	0	0	0
T42	3205	0	0	0
T43	32273	0	0	0
T44	57021	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	493	0	0
T4	391279	0	0	0
T5	438951	26	0	0
T6	117430	0	0	0
T13	766579	11	0	0
T14	142699	0	0	0
T18	0	4	0	0
T19	36992	3	0	0
T20	102556	4	0	0
T21	2026	0	0	0
T22	0	3	0	0
T23	63440	0	0	0
T24	0	1	0	0
T29	0	1	0	0
T41	1223	0	0	0
T72	0	3	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654280250	229764528	0	0
T1	400212	399698	0	0
T2	93154	86622	0	0
T3	18525	615	0	0
T4	391279	391271	0	0
T5	438951	55180	0	0
T6	117430	117421	0	0
T13	766579	115375	0	0
T19	36992	582	0	0
T20	102556	6059	0	0
T21	2026	691	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1028	0	0
T3	18525	1	0	0
T4	391279	0	0	0
T5	438951	31	0	0
T6	117430	0	0	0
T13	766579	17	0	0
T16	0	1	0	0
T19	36992	4	0	0
T20	102556	5	0	0
T21	2026	0	0	0
T23	63440	0	0	0
T24	0	2	0	0
T41	1223	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1003	0	0
T3	18525	1	0	0
T4	391279	0	0	0
T5	438951	31	0	0
T6	117430	0	0	0
T13	766579	17	0	0
T16	0	1	0	0
T19	36992	4	0	0
T20	102556	5	0	0
T21	2026	0	0	0
T23	63440	0	0	0
T24	0	2	0	0
T41	1223	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	976	0	0
T3	18525	1	0	0
T4	391279	0	0	0
T5	438951	28	0	0
T6	117430	0	0	0
T13	766579	16	0	0
T16	0	1	0	0
T19	36992	3	0	0
T20	102556	5	0	0
T21	2026	0	0	0
T23	63440	0	0	0
T24	0	2	0	0
T41	1223	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	958	0	0
T3	18525	1	0	0
T4	391279	0	0	0
T5	438951	28	0	0
T6	117430	0	0	0
T13	766579	16	0	0
T16	0	1	0	0
T19	36992	3	0	0
T20	102556	4	0	0
T21	2026	0	0	0
T23	63440	0	0	0
T24	0	2	0	0
T41	1223	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1620	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	2	0	0
T6	117430	0	0	0
T13	766579	10	0	0
T18	0	1	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T23	63440	5	0	0
T24	0	1	0	0
T26	0	2	0	0
T27	0	3	0	0
T70	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	168874	0	0
T2	93154	202	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	504	0	0
T6	117430	0	0	0
T13	766579	373	0	0
T18	0	85	0	0
T19	36992	52	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T23	63440	629	0	0
T26	0	180	0	0
T27	0	46	0	0
T70	0	403	0	0
T79	0	58	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1502	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	0	0	0
T6	117430	0	0	0
T13	766579	1	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T23	63440	5	0	0
T26	0	1	0	0
T27	0	1	0	0
T32	0	1	0	0
T76	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	65	0	0
T5	438951	2	0	0
T6	117430	0	0	0
T13	766579	3	0	0
T14	142699	0	0	0
T15	126617	0	0	0
T16	138863	0	0	0
T18	0	1	0	0
T23	63440	0	0	0
T26	0	1	0	0
T41	1223	0	0	0
T42	3205	0	0	0
T43	32273	0	0	0
T70	0	1	0	0
T76	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1680	0	0
T10	40480	374	0	0
T11	0	395	0	0
T12	0	371	0	0
T30	0	346	0	0
T31	0	194	0	0
T32	23384	0	0	0
T33	70042	0	0	0
T34	99672	0	0	0
T35	94674	0	0	0
T36	4026	0	0	0
T37	414911	0	0	0
T38	111081	0	0	0
T39	41970	0	0	0
T40	196376	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1410	0	0
T10	40480	314	0	0
T11	0	335	0	0
T12	0	311	0	0
T30	0	286	0	0
T31	0	164	0	0
T32	23384	0	0	0
T33	70042	0	0	0
T34	99672	0	0	0
T35	94674	0	0	0
T36	4026	0	0	0
T37	414911	0	0	0
T38	111081	0	0	0
T39	41970	0	0	0
T40	196376	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654278676	654205473	0	0
T1	400212	400204	0	0
T2	93154	93078	0	0
T3	18525	18466	0	0
T4	391279	391271	0	0
T5	438951	438942	0	0
T6	117430	117421	0	0
T13	766579	766502	0	0
T19	36992	36899	0	0
T20	102556	102499	0	0
T21	2026	1929	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	654909513	0	0
T1	400212	400204	0	0
T2	93154	93078	0	0
T3	18525	18466	0	0
T4	391279	391271	0	0
T5	438951	438942	0	0
T6	117430	117421	0	0
T13	766579	766502	0	0
T19	36992	36899	0	0
T20	102556	102499	0	0
T21	2026	1929	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T19,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T19,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T19,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T19,T5
1	0	1	Covered	T1,T19,T5
1	1	0	Covered	T2,T19,T5
1	1	1	Covered	T5,T6,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T13
0	1	Covered	T5,T70,T46
1	0	Covered	T49,T53,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T6,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T49,T53,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T13
1	0	Not Covered
1	1	Covered	T5,T70,T46

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T5
1	Covered	T13,T41,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T5
1	Covered	T5,T15,T18

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T13,T41
1	Covered	T2,T19,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T5
1	Covered	T5,T13,T26

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T19,T5,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T6,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T5,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T19,T5
Phase1St	198	Covered	T2,T19,T5
Phase2St	215	Covered	T2,T19,T5
Phase3St	233	Covered	T2,T19,T5
TerminalSt	249	Covered	T19,T5,T6
TimeoutSt	159	Covered	T5,T6,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T2,T19,T5
IdleSt->TimeoutSt	159	Covered	T5,T6,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T45,T95,T58
Phase0St->Phase1St	198	Covered	T2,T19,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T28,T95,T55
Phase1St->Phase2St	215	Covered	T2,T19,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T26,T93,T95
Phase2St->Phase3St	233	Covered	T2,T19,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T2,T96,T97
Phase3St->TerminalSt	249	Covered	T19,T5,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T5,T6,T13
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T6,T13
TimeoutSt->Phase0St	172	Covered	T5,T70,T46

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T70,T46
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T45,T95,T58
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T19,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T19,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T95,T55
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T19,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T19,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T93,T95
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T19,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T19,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T96,T97
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T19,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T19,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T6,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T19,T5,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	655097595	336	0	0
CheckAccumTrig0_A	655097595	508	0	0
CheckAccumTrig1_A	655097595	22	0	0
CheckClr_A	655097595	229	0	0
CheckEn_A	654280250	275182980	0	0
CheckPhase0_A	655097595	588	0	0
CheckPhase1_A	655097595	579	0	0
CheckPhase2_A	655097595	566	0	0
CheckPhase3_A	655097595	556	0	0
CheckTimeout0_A	655097595	1211	0	0
CheckTimeoutSt1_A	655097595	141320	0	0
CheckTimeoutSt2_A	655097595	1128	0	0
CheckTimeoutStTrig_A	655097595	61	0	0
ErrorStAllEscAsserted_A	655097595	1616	0	0
ErrorStIsTerminal_A	655097595	1346	0	0
EscStateOut_A	654278676	654205473	0	0
u_state_regs_A	655097595	654909513	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	336	0	0
T10	40480	57	0	0
T11	0	106	0	0
T12	0	65	0	0
T30	0	73	0	0
T31	0	35	0	0
T32	23384	0	0	0
T33	70042	0	0	0
T34	99672	0	0	0
T35	94674	0	0	0
T36	4026	0	0	0
T37	414911	0	0	0
T38	111081	0	0	0
T39	41970	0	0	0
T40	196376	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	508	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	4	0	0
T6	117430	2	0	0
T13	766579	6	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	7	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T22	0	2	0	0
T23	63440	0	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	22	0	0
T49	498299	2	0	0
T50	565726	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	72524	0	0	0
T63	762167	0	0	0
T64	631883	0	0	0
T65	810904	0	0	0
T66	35269	0	0	0
T67	106260	0	0	0
T68	389238	0	0	0
T69	896	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	229	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	1	0	0
T6	117430	1	0	0
T13	766579	1	0	0
T18	0	1	0	0
T19	36992	0	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T23	63440	0	0	0
T25	0	1	0	0
T26	0	4	0	0
T27	0	1	0	0
T70	0	4	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654280250	275182980	0	0
T1	400212	399353	0	0
T2	93154	86843	0	0
T3	18525	18465	0	0
T4	391279	386276	0	0
T5	438951	100605	0	0
T6	117430	2583	0	0
T13	766579	827184	0	0
T19	36992	4009	0	0
T20	102556	98433	0	0
T21	2026	695	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	588	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	5	0	0
T6	117430	2	0	0
T13	766579	6	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	7	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T22	0	2	0	0
T23	63440	0	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	579	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	5	0	0
T6	117430	2	0	0
T13	766579	6	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	7	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T22	0	2	0	0
T23	63440	0	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	566	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	5	0	0
T6	117430	2	0	0
T13	766579	6	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	7	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T22	0	2	0	0
T23	63440	0	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	556	0	0
T4	391279	0	0	0
T5	438951	5	0	0
T6	117430	2	0	0
T13	766579	6	0	0
T14	142699	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	7	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T22	0	2	0	0
T23	63440	0	0	0
T41	1223	1	0	0
T70	0	5	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1211	0	0
T5	438951	2	0	0
T6	117430	3	0	0
T13	766579	1	0	0
T14	142699	0	0	0
T15	126617	0	0	0
T16	138863	0	0	0
T22	0	2	0	0
T23	63440	4	0	0
T26	0	2	0	0
T27	0	2	0	0
T41	1223	0	0	0
T42	3205	0	0	0
T43	32273	0	0	0
T45	0	1	0	0
T70	0	4	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	141320	0	0
T5	438951	494	0	0
T6	117430	130	0	0
T13	766579	147	0	0
T14	142699	0	0	0
T15	126617	0	0	0
T16	138863	0	0	0
T22	0	140	0	0
T23	63440	569	0	0
T26	0	244	0	0
T27	0	133	0	0
T41	1223	0	0	0
T42	3205	0	0	0
T43	32273	0	0	0
T45	0	125	0	0
T70	0	141	0	0
T75	0	150	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1128	0	0
T5	438951	1	0	0
T6	117430	3	0	0
T13	766579	1	0	0
T14	142699	0	0	0
T15	126617	0	0	0
T16	138863	0	0	0
T22	0	2	0	0
T23	63440	4	0	0
T26	0	2	0	0
T27	0	2	0	0
T41	1223	0	0	0
T42	3205	0	0	0
T43	32273	0	0	0
T45	0	1	0	0
T70	0	3	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	61	0	0
T5	438951	1	0	0
T6	117430	0	0	0
T13	766579	0	0	0
T14	142699	0	0	0
T15	126617	0	0	0
T16	138863	0	0	0
T23	63440	0	0	0
T35	0	1	0	0
T41	1223	0	0	0
T42	3205	0	0	0
T43	32273	0	0	0
T46	0	4	0	0
T62	0	1	0	0
T70	0	1	0	0
T82	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1616	0	0
T10	40480	378	0	0
T11	0	363	0	0
T12	0	339	0	0
T30	0	350	0	0
T31	0	186	0	0
T32	23384	0	0	0
T33	70042	0	0	0
T34	99672	0	0	0
T35	94674	0	0	0
T36	4026	0	0	0
T37	414911	0	0	0
T38	111081	0	0	0
T39	41970	0	0	0
T40	196376	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1346	0	0
T10	40480	318	0	0
T11	0	303	0	0
T12	0	279	0	0
T30	0	290	0	0
T31	0	156	0	0
T32	23384	0	0	0
T33	70042	0	0	0
T34	99672	0	0	0
T35	94674	0	0	0
T36	4026	0	0	0
T37	414911	0	0	0
T38	111081	0	0	0
T39	41970	0	0	0
T40	196376	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654278676	654205473	0	0
T1	400212	400204	0	0
T2	93154	93078	0	0
T3	18525	18466	0	0
T4	391279	391271	0	0
T5	438951	438942	0	0
T6	117430	117421	0	0
T13	766579	766502	0	0
T19	36992	36899	0	0
T20	102556	102499	0	0
T21	2026	1929	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	654909513	0	0
T1	400212	400204	0	0
T2	93154	93078	0	0
T3	18525	18466	0	0
T4	391279	391271	0	0
T5	438951	438942	0	0
T6	117430	117421	0	0
T13	766579	766502	0	0
T19	36992	36899	0	0
T20	102556	102499	0	0
T21	2026	1929	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T19
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T19

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T19,T5
1	0	1	Covered	T4,T5,T13
1	1	0	Covered	T3,T5,T6
1	1	1	Covered	T19,T5,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T19,T5,T13
0	1	Covered	T23,T71,T77
1	0	Covered	T5,T45,T82

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T19,T5,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T45,T82

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T5,T13
1	0	Not Covered
1	1	Covered	T23,T71,T77

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T19,T5,T13
1	Covered	T1,T2,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T19
1	Covered	T13,T23,T77

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T19
1	Covered	T5,T13,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T19,T5,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T19,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T5,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T19,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T19
Phase1St	198	Covered	T1,T2,T19
Phase2St	215	Covered	T1,T2,T19
Phase3St	233	Covered	T1,T2,T19
TerminalSt	249	Covered	T1,T2,T19
TimeoutSt	159	Covered	T19,T5,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T19
IdleSt->TimeoutSt	159	Covered	T19,T5,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T26,T98,T99
Phase0St->Phase1St	198	Covered	T1,T2,T19
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T26,T27,T82
Phase1St->Phase2St	215	Covered	T1,T2,T19
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T82,T93,T100
Phase2St->Phase3St	233	Covered	T1,T2,T19
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T75,T26,T101
Phase3St->TerminalSt	249	Covered	T1,T2,T19
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T5,T13
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T19,T13,T23
TimeoutSt->Phase0St	172	Covered	T5,T23,T71

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T5,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T23,T71
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T19,T5,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T13,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T98,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27,T82
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T82,T93,T100
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T75,T26,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	655097595	352	0	0
CheckAccumTrig0_A	655097595	520	0	0
CheckAccumTrig1_A	655097595	20	0	0
CheckClr_A	655097595	273	0	0
CheckEn_A	654280250	292512024	0	0
CheckPhase0_A	655097595	606	0	0
CheckPhase1_A	655097595	594	0	0
CheckPhase2_A	655097595	583	0	0
CheckPhase3_A	655097595	575	0	0
CheckTimeout0_A	655097595	1517	0	0
CheckTimeoutSt1_A	655097595	161143	0	0
CheckTimeoutSt2_A	655097595	1423	0	0
CheckTimeoutStTrig_A	655097595	73	0	0
ErrorStAllEscAsserted_A	655097595	1628	0	0
ErrorStIsTerminal_A	655097595	1358	0	0
EscStateOut_A	654278676	654205473	0	0
u_state_regs_A	655097595	654909513	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	352	0	0
T10	40480	70	0	0
T11	0	72	0	0
T12	0	73	0	0
T30	0	100	0	0
T31	0	37	0	0
T32	23384	0	0	0
T33	70042	0	0	0
T34	99672	0	0	0
T35	94674	0	0	0
T36	4026	0	0	0
T37	414911	0	0	0
T38	111081	0	0	0
T39	41970	0	0	0
T40	196376	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	520	0	0
T1	400212	1	0	0
T2	93154	8	0	0
T3	18525	0	0	0
T4	391279	1	0	0
T5	438951	3	0	0
T6	117430	0	0	0
T13	766579	7	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	8	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	20	0	0
T5	438951	1	0	0
T6	117430	0	0	0
T13	766579	0	0	0
T14	142699	0	0	0
T15	126617	0	0	0
T16	138863	0	0	0
T23	63440	0	0	0
T41	1223	0	0	0
T42	3205	0	0	0
T43	32273	0	0	0
T45	0	1	0	0
T49	0	1	0	0
T57	0	2	0	0
T82	0	1	0	0
T99	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	273	0	0
T2	93154	7	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	1	0	0
T6	117430	0	0	0
T13	766579	1	0	0
T18	0	4	0	0
T19	36992	0	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T23	63440	0	0	0
T26	0	15	0	0
T27	0	5	0	0
T29	0	1	0	0
T71	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654280250	292512024	0	0
T1	400212	11718	0	0
T2	93154	3126	0	0
T3	18525	17163	0	0
T4	391279	2192	0	0
T5	438951	161773	0	0
T6	117430	117421	0	0
T13	766579	673789	0	0
T19	36992	4394	0	0
T20	102556	102498	0	0
T21	2026	699	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	606	0	0
T1	400212	1	0	0
T2	93154	8	0	0
T3	18525	0	0	0
T4	391279	1	0	0
T5	438951	4	0	0
T6	117430	0	0	0
T13	766579	7	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T23	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	594	0	0
T1	400212	1	0	0
T2	93154	8	0	0
T3	18525	0	0	0
T4	391279	1	0	0
T5	438951	4	0	0
T6	117430	0	0	0
T13	766579	7	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T23	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	583	0	0
T1	400212	1	0	0
T2	93154	8	0	0
T3	18525	0	0	0
T4	391279	1	0	0
T5	438951	4	0	0
T6	117430	0	0	0
T13	766579	7	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T23	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	575	0	0
T1	400212	1	0	0
T2	93154	8	0	0
T3	18525	0	0	0
T4	391279	1	0	0
T5	438951	4	0	0
T6	117430	0	0	0
T13	766579	7	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T23	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1517	0	0
T4	391279	0	0	0
T5	438951	1	0	0
T6	117430	0	0	0
T13	766579	1	0	0
T14	142699	0	0	0
T15	0	1	0	0
T18	0	5	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T22	0	212	0	0
T23	63440	2	0	0
T26	0	10	0	0
T41	1223	0	0	0
T71	0	1	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	161143	0	0
T4	391279	0	0	0
T5	438951	7	0	0
T6	117430	0	0	0
T13	766579	43	0	0
T14	142699	0	0	0
T15	0	134	0	0
T18	0	993	0	0
T19	36992	43	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T22	0	8603	0	0
T23	63440	119	0	0
T26	0	938	0	0
T41	1223	0	0	0
T71	0	178	0	0
T77	0	104	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1423	0	0
T4	391279	0	0	0
T5	438951	0	0	0
T6	117430	0	0	0
T13	766579	1	0	0
T14	142699	0	0	0
T15	0	1	0	0
T18	0	5	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T22	0	212	0	0
T23	63440	1	0	0
T26	0	8	0	0
T32	0	3	0	0
T35	0	1	0	0
T41	1223	0	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	73	0	0
T14	142699	0	0	0
T15	126617	0	0	0
T16	138863	0	0	0
T17	572533	0	0	0
T23	63440	1	0	0
T24	61351	0	0	0
T26	0	1	0	0
T41	1223	0	0	0
T42	3205	0	0	0
T43	32273	0	0	0
T44	57021	0	0	0
T71	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T82	0	3	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T93	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1628	0	0
T10	40480	353	0	0
T11	0	382	0	0
T12	0	377	0	0
T30	0	365	0	0
T31	0	151	0	0
T32	23384	0	0	0
T33	70042	0	0	0
T34	99672	0	0	0
T35	94674	0	0	0
T36	4026	0	0	0
T37	414911	0	0	0
T38	111081	0	0	0
T39	41970	0	0	0
T40	196376	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1358	0	0
T10	40480	293	0	0
T11	0	322	0	0
T12	0	317	0	0
T30	0	305	0	0
T31	0	121	0	0
T32	23384	0	0	0
T33	70042	0	0	0
T34	99672	0	0	0
T35	94674	0	0	0
T36	4026	0	0	0
T37	414911	0	0	0
T38	111081	0	0	0
T39	41970	0	0	0
T40	196376	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654278676	654205473	0	0
T1	400212	400204	0	0
T2	93154	93078	0	0
T3	18525	18466	0	0
T4	391279	391271	0	0
T5	438951	438942	0	0
T6	117430	117421	0	0
T13	766579	766502	0	0
T19	36992	36899	0	0
T20	102556	102499	0	0
T21	2026	1929	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	654909513	0	0
T1	400212	400204	0	0
T2	93154	93078	0	0
T3	18525	18466	0	0
T4	391279	391271	0	0
T5	438951	438942	0	0
T6	117430	117421	0	0
T13	766579	766502	0	0
T19	36992	36899	0	0
T20	102556	102499	0	0
T21	2026	1929	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T19,T21
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T19,T21

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T19,T21

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T6
1	0	1	Covered	T21,T5,T6
1	1	0	Covered	T19,T5,T13
1	1	1	Covered	T13,T23,T15

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T23,T15
0	1	Covered	T26,T27,T46
1	0	Covered	T18,T71,T45

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T23,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T71,T45

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T23,T15
1	0	Not Covered
1	1	Covered	T26,T27,T46

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T19,T21,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T21
1	Covered	T5,T13,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T19,T21,T5
1	Covered	T2,T5,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T21
1	Covered	T6,T13,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T21,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T21,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T19,T21,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T21,T13,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T19,T21
Phase1St	198	Covered	T2,T19,T21
Phase2St	215	Covered	T2,T19,T21
Phase3St	233	Covered	T2,T19,T21
TerminalSt	249	Covered	T2,T19,T21
TimeoutSt	159	Covered	T13,T23,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T2,T19,T21
IdleSt->TimeoutSt	159	Covered	T13,T23,T15
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T25,T45
Phase0St->Phase1St	198	Covered	T2,T19,T21
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T17,T85
Phase1St->Phase2St	215	Covered	T2,T19,T21
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T6,T18,T26
Phase2St->Phase3St	233	Covered	T2,T19,T21
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T6,T26,T93
Phase3St->TerminalSt	249	Covered	T2,T19,T21
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T19,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T23,T15
TimeoutSt->Phase0St	172	Covered	T18,T71,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T21
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T23,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T71,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T23,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T23,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T25,T45
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T19,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T19,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T17,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T19,T21
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T19,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T18,T26
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T19,T21
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T19,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T26,T93
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T19,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T19,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T19,T21
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	655097595	311	0	0
CheckAccumTrig0_A	655097595	530	0	0
CheckAccumTrig1_A	655097595	24	0	0
CheckClr_A	655097595	262	0	0
CheckEn_A	654280250	293949802	0	0
CheckPhase0_A	655097595	591	0	0
CheckPhase1_A	655097595	582	0	0
CheckPhase2_A	655097595	574	0	0
CheckPhase3_A	655097595	559	0	0
CheckTimeout0_A	655097595	2077	0	0
CheckTimeoutSt1_A	655097595	210515	0	0
CheckTimeoutSt2_A	655097595	2004	0	0
CheckTimeoutStTrig_A	655097595	49	0	0
ErrorStAllEscAsserted_A	655097595	1664	0	0
ErrorStIsTerminal_A	655097595	1394	0	0
EscStateOut_A	654278676	654205473	0	0
u_state_regs_A	655097595	654909513	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	311	0	0
T10	40480	56	0	0
T11	0	62	0	0
T12	0	73	0	0
T30	0	79	0	0
T31	0	41	0	0
T32	23384	0	0	0
T33	70042	0	0	0
T34	99672	0	0	0
T35	94674	0	0	0
T36	4026	0	0	0
T37	414911	0	0	0
T38	111081	0	0	0
T39	41970	0	0	0
T40	196376	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	530	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	5	0	0
T6	117430	11	0	0
T13	766579	7	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	1	0	0
T23	63440	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	24	0	0
T18	402522	1	0	0
T25	352244	0	0	0
T45	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T55	0	2	0	0
T70	41404	0	0	0
T71	94268	1	0	0
T72	589786	0	0	0
T73	76476	0	0	0
T77	8432	0	0	0
T85	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	3251	0	0	0
T111	413464	0	0	0
T112	15719	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	262	0	0
T4	391279	0	0	0
T5	438951	3	0	0
T6	117430	10	0	0
T13	766579	2	0	0
T14	142699	0	0	0
T17	0	1	0	0
T18	0	3	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	0	0	0
T23	63440	0	0	0
T25	0	1	0	0
T41	1223	0	0	0
T71	0	2	0	0
T73	0	1	0	0
T113	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654280250	293949802	0	0
T1	400212	399148	0	0
T2	93154	9589	0	0
T3	18525	18465	0	0
T4	391279	391271	0	0
T5	438951	274641	0	0
T6	117430	594	0	0
T13	766579	965908	0	0
T19	36992	34972	0	0
T20	102556	102498	0	0
T21	2026	703	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	591	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	5	0	0
T6	117430	10	0	0
T13	766579	7	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	1	0	0
T23	63440	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	582	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	5	0	0
T6	117430	9	0	0
T13	766579	7	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	2	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	1	0	0
T23	63440	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	574	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	5	0	0
T6	117430	8	0	0
T13	766579	7	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	2	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	1	0	0
T23	63440	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	559	0	0
T2	93154	1	0	0
T3	18525	0	0	0
T4	391279	0	0	0
T5	438951	5	0	0
T6	117430	7	0	0
T13	766579	7	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	2	0	0
T19	36992	1	0	0
T20	102556	0	0	0
T21	2026	1	0	0
T23	63440	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	2077	0	0
T13	766579	2	0	0
T14	142699	0	0	0
T15	126617	1	0	0
T16	138863	0	0	0
T18	0	1	0	0
T22	0	203	0	0
T23	63440	1	0	0
T24	61351	0	0	0
T26	0	8	0	0
T41	1223	0	0	0
T42	3205	0	0	0
T43	32273	0	0	0
T44	57021	0	0	0
T71	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	210515	0	0
T13	766579	211	0	0
T14	142699	0	0	0
T15	126617	69	0	0
T16	138863	0	0	0
T18	0	5	0	0
T22	0	8277	0	0
T23	63440	119	0	0
T24	61351	0	0	0
T26	0	1175	0	0
T41	1223	0	0	0
T42	3205	0	0	0
T43	32273	0	0	0
T44	57021	0	0	0
T71	0	27	0	0
T75	0	39	0	0
T77	0	152	0	0
T78	0	270	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	2004	0	0
T13	766579	2	0	0
T14	142699	0	0	0
T15	126617	1	0	0
T16	138863	0	0	0
T22	0	203	0	0
T23	63440	1	0	0
T24	61351	0	0	0
T26	0	7	0	0
T27	0	1	0	0
T41	1223	0	0	0
T42	3205	0	0	0
T43	32273	0	0	0
T44	57021	0	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	49	0	0
T26	346896	1	0	0
T27	525554	1	0	0
T28	383288	0	0	0
T46	0	1	0	0
T78	21958	0	0	0
T79	27558	0	0	0
T81	0	1	0	0
T82	0	3	0	0
T86	0	1	0	0
T90	134948	0	0	0
T91	25124	0	0	0
T92	170467	0	0	0
T93	0	2	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	11163	0	0	0
T118	59868	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1664	0	0
T10	40480	390	0	0
T11	0	360	0	0
T12	0	344	0	0
T30	0	370	0	0
T31	0	200	0	0
T32	23384	0	0	0
T33	70042	0	0	0
T34	99672	0	0	0
T35	94674	0	0	0
T36	4026	0	0	0
T37	414911	0	0	0
T38	111081	0	0	0
T39	41970	0	0	0
T40	196376	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	1394	0	0
T10	40480	330	0	0
T11	0	300	0	0
T12	0	284	0	0
T30	0	310	0	0
T31	0	170	0	0
T32	23384	0	0	0
T33	70042	0	0	0
T34	99672	0	0	0
T35	94674	0	0	0
T36	4026	0	0	0
T37	414911	0	0	0
T38	111081	0	0	0
T39	41970	0	0	0
T40	196376	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654278676	654205473	0	0
T1	400212	400204	0	0
T2	93154	93078	0	0
T3	18525	18466	0	0
T4	391279	391271	0	0
T5	438951	438942	0	0
T6	117430	117421	0	0
T13	766579	766502	0	0
T19	36992	36899	0	0
T20	102556	102499	0	0
T21	2026	1929	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655097595	654909513	0	0
T1	400212	400204	0	0
T2	93154	93078	0	0
T3	18525	18466	0	0
T4	391279	391271	0	0
T5	438951	438942	0	0
T6	117430	117421	0	0
T13	766579	766502	0	0
T19	36992	36899	0	0
T20	102556	102499	0	0
T21	2026	1929	0	0