Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67392241	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32631653

1

T1

1231

T2

2422

T3

103079

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15067260	1			T1	1316		T2	1116		T3	43188
values[0x0]	41384608	1			T1	1046		T2	3035		T3	140411
values[0x1]	43572026	1			T1	1047		T2	3037		T3	140425

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57506191	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42517703

1

T1

1552

T2

3021

T3

130332

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	530626	1			T1	8		T2	19		T3	1197
valid_sources[0x01]	328832	1			T1	11		T2	13		T3	1354
valid_sources[0x02]	329050	1			T1	16		T2	14		T3	1197
valid_sources[0x03]	327841	1			T1	12		T2	10		T3	1486
valid_sources[0x04]	317204	1			T1	8		T2	25		T3	1221
valid_sources[0x05]	317644	1			T1	8		T2	9		T3	1147
valid_sources[0x06]	732809	1			T1	5		T3	1414		T4	1242
valid_sources[0x07]	325173	1			T1	21		T2	9		T3	1313
valid_sources[0x08]	321085	1			T1	17		T2	19		T3	1457
valid_sources[0x09]	326783	1			T1	26		T2	17		T3	1485
valid_sources[0x0a]	329986	1			T1	17		T2	19		T3	1455
valid_sources[0x0b]	578602	1			T1	7		T2	36		T3	1189
valid_sources[0x0c]	319600	1			T1	11		T2	12		T3	1247
valid_sources[0x0d]	319422	1			T1	24		T3	1218		T4	1363
valid_sources[0x0e]	402490	1			T1	9		T2	16		T3	1275
valid_sources[0x0f]	315717	1			T1	9		T2	45		T3	1238
valid_sources[0x10]	314724	1			T1	9		T2	18		T3	1274
valid_sources[0x11]	311327	1			T1	14		T2	27		T3	1313
valid_sources[0x12]	326208	1			T1	1		T2	62		T3	1520
valid_sources[0x13]	324581	1			T1	21		T2	32		T3	1184
valid_sources[0x14]	321983	1			T1	37		T2	29		T3	1145
valid_sources[0x15]	324380	1			T1	10		T2	21		T3	1223
valid_sources[0x16]	324398	1			T1	8		T2	87		T3	1170
valid_sources[0x17]	333054	1			T1	6		T2	41		T3	1091
valid_sources[0x18]	326538	1			T1	13		T3	1357		T4	1285
valid_sources[0x19]	323433	1			T1	4		T2	90		T3	1151
valid_sources[0x1a]	514770	1			T1	12		T2	36		T3	1375
valid_sources[0x1b]	331816	1			T1	6		T2	5		T3	1266
valid_sources[0x1c]	326753	1			T1	16		T2	57		T3	1084
valid_sources[0x1d]	317020	1			T1	16		T2	4		T3	1327
valid_sources[0x1e]	653061	1			T1	19		T3	1390		T4	1178
valid_sources[0x1f]	318350	1			T1	6		T2	24		T3	1139
valid_sources[0x20]	329888	1			T1	12		T2	16		T3	1264
valid_sources[0x21]	332045	1			T1	10		T2	35		T3	1200
valid_sources[0x22]	317955	1			T1	18		T2	36		T3	1373
valid_sources[0x23]	318394	1			T1	21		T3	1191		T4	1322
valid_sources[0x24]	322996	1			T1	10		T2	15		T3	1282
valid_sources[0x25]	600675	1			T1	8		T2	54		T3	1224
valid_sources[0x26]	783494	1			T1	21		T2	17		T3	1192
valid_sources[0x27]	314951	1			T1	16		T2	6		T3	1298
valid_sources[0x28]	752026	1			T1	13		T2	28		T3	1364
valid_sources[0x29]	790505	1			T1	23		T2	41		T3	1330
valid_sources[0x2a]	313430	1			T1	17		T2	13		T3	1311
valid_sources[0x2b]	331357	1			T1	26		T2	73		T3	1177
valid_sources[0x2c]	314551	1			T1	7		T3	1361		T4	1271
valid_sources[0x2d]	337724	1			T1	8		T2	21		T3	1376
valid_sources[0x2e]	648171	1			T1	9		T2	8		T3	1337
valid_sources[0x2f]	321094	1			T1	22		T2	17		T3	1389
valid_sources[0x30]	321746	1			T1	18		T2	34		T3	1085
valid_sources[0x31]	319412	1			T1	15		T2	15		T3	1243
valid_sources[0x32]	321381	1			T1	5		T2	9		T3	1302
valid_sources[0x33]	315295	1			T1	7		T2	39		T3	1171
valid_sources[0x34]	322950	1			T1	14		T2	29		T3	1249
valid_sources[0x35]	319450	1			T1	20		T2	36		T3	1232
valid_sources[0x36]	655614	1			T1	4		T2	55		T3	1345
valid_sources[0x37]	324485	1			T1	8		T2	8		T3	1366
valid_sources[0x38]	709391	1			T1	19		T2	84		T3	1514
valid_sources[0x39]	321875	1			T1	7		T2	38		T3	1340
valid_sources[0x3a]	328343	1			T1	18		T2	9		T3	1247
valid_sources[0x3b]	320647	1			T1	17		T2	83		T3	1197
valid_sources[0x3c]	327413	1			T1	5		T2	60		T3	1390
valid_sources[0x3d]	373712	1			T1	7		T2	39		T3	1204
valid_sources[0x3e]	316788	1			T1	9		T2	22		T3	1133
valid_sources[0x3f]	317390	1			T1	9		T3	1279		T4	1125
valid_sources[0x40]	707527	1			T1	14		T2	21		T3	1383
valid_sources[0x41]	716676	1			T1	31		T2	65		T3	1273
valid_sources[0x42]	320395	1			T1	11		T2	21		T3	1482
valid_sources[0x43]	584758	1			T1	12		T2	18		T3	1272
valid_sources[0x44]	316461	1			T1	11		T2	35		T3	1203
valid_sources[0x45]	327304	1			T1	8		T2	8		T3	1298
valid_sources[0x46]	319913	1			T1	10		T2	11		T3	1146
valid_sources[0x47]	336196	1			T1	16		T2	10		T3	1121
valid_sources[0x48]	1135536	1			T1	12		T2	14		T3	1304
valid_sources[0x49]	320421	1			T1	11		T2	37		T3	1361
valid_sources[0x4a]	311120	1			T1	5		T2	79		T3	1258
valid_sources[0x4b]	321934	1			T1	21		T3	1098		T4	1366
valid_sources[0x4c]	333654	1			T1	8		T2	13		T3	1193
valid_sources[0x4d]	332919	1			T1	5		T2	29		T3	1248
valid_sources[0x4e]	319838	1			T1	4		T2	18		T3	1191
valid_sources[0x4f]	327454	1			T1	7		T2	3		T3	1217
valid_sources[0x50]	320515	1			T1	9		T2	34		T3	1245
valid_sources[0x51]	322363	1			T1	9		T2	30		T3	1327
valid_sources[0x52]	604364	1			T1	6		T2	26		T3	1334
valid_sources[0x53]	320821	1			T1	10		T2	66		T3	1485
valid_sources[0x54]	324069	1			T1	12		T2	32		T3	1533
valid_sources[0x55]	323683	1			T1	25		T2	33		T3	1175
valid_sources[0x56]	314732	1			T1	2		T2	38		T3	1293
valid_sources[0x57]	319863	1			T1	16		T3	1319		T4	1399
valid_sources[0x58]	327774	1			T1	14		T3	1035		T4	1304
valid_sources[0x59]	717262	1			T1	12		T3	1161		T4	1190
valid_sources[0x5a]	660133	1			T1	22		T2	13		T3	1242
valid_sources[0x5b]	358806	1			T1	3		T2	12		T3	1415
valid_sources[0x5c]	326075	1			T1	8		T3	1175		T4	1279
valid_sources[0x5d]	883799	1			T1	11		T2	26		T3	1289
valid_sources[0x5e]	338792	1			T1	24		T2	48		T3	1212
valid_sources[0x5f]	320670	1			T1	6		T2	22		T3	1285
valid_sources[0x60]	328680	1			T1	12		T2	51		T3	1123
valid_sources[0x61]	316603	1			T1	10		T2	17		T3	1302
valid_sources[0x62]	444633	1			T1	14		T2	65		T3	1294
valid_sources[0x63]	320381	1			T1	11		T2	6		T3	1444
valid_sources[0x64]	335013	1			T1	11		T2	14		T3	1164
valid_sources[0x65]	321093	1			T1	26		T2	6		T3	1376
valid_sources[0x66]	587525	1			T1	11		T2	8		T3	1323
valid_sources[0x67]	331707	1			T1	13		T2	12		T3	1260
valid_sources[0x68]	313937	1			T1	10		T3	1109		T4	1235
valid_sources[0x69]	311250	1			T1	8		T2	26		T3	1163
valid_sources[0x6a]	327665	1			T1	23		T2	16		T3	1216
valid_sources[0x6b]	322401	1			T1	36		T2	58		T3	1656
valid_sources[0x6c]	330576	1			T1	18		T2	32		T3	1145
valid_sources[0x6d]	333310	1			T1	26		T2	23		T3	1250
valid_sources[0x6e]	854896	1			T1	9		T2	58		T3	1460
valid_sources[0x6f]	316025	1			T1	33		T2	4		T3	1224
valid_sources[0x70]	813222	1			T1	7		T2	20		T3	1212
valid_sources[0x71]	326995	1			T1	16		T2	35		T3	1097
valid_sources[0x72]	324580	1			T1	9		T2	29		T3	1250
valid_sources[0x73]	331329	1			T1	11		T2	61		T3	1341
valid_sources[0x74]	326286	1			T1	25		T2	31		T3	1312
valid_sources[0x75]	312370	1			T1	17		T2	16		T3	1176
valid_sources[0x76]	842772	1			T1	23		T2	31		T3	1163
valid_sources[0x77]	321731	1			T1	9		T2	40		T3	1160
valid_sources[0x78]	323488	1			T1	19		T2	28		T3	1249
valid_sources[0x79]	323901	1			T1	6		T2	16		T3	1395
valid_sources[0x7a]	327565	1			T1	7		T2	81		T3	1307
valid_sources[0x7b]	327338	1			T1	10		T2	22		T3	1338
valid_sources[0x7c]	340493	1			T1	21		T2	2		T3	1258
valid_sources[0x7d]	328660	1			T1	7		T2	16		T3	1366
valid_sources[0x7e]	316698	1			T1	4		T2	34		T3	1089
valid_sources[0x7f]	323210	1			T1	4		T2	29		T3	1129
valid_sources[0x80]	322072	1			T1	8		T2	28		T3	1436

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7489625

1

T1

640

T2

554

T3

21647

values[0x0]

all_enables

biggest_size

15862500

1

T1

386

T2

1163

T3

52066

values[0x1]

all_enables

biggest_size

9279528

1

T1

205

T2

705

T3

29366