Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T229,T71,T72
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14154	0	0
DisabledNoTrigBkwd_A	2147483647	735657	0	0
DisabledNoTrigFwd_A	2147483647	1535027089	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14154	0	0
T25	335865	0	0	0
T34	0	1044	0	0
T71	3788	887	0	0
T72	1343	477	0	0
T73	32008	0	0	0
T77	59493	0	0	0
T78	35164	0	0	0
T79	10682	0	0	0
T80	54620	0	0	0
T82	7613	0	0	0
T83	14425	0	0	0
T84	14732	0	0	0
T85	190500	0	0	0
T127	166721	0	0	0
T229	3316	1083	0	0
T230	6170	661	0	0
T231	2630	597	0	0
T232	0	516	0	0
T233	0	610	0	0
T234	0	582	0	0
T235	0	505	0	0
T236	0	544	0	0
T237	0	738	0	0
T238	0	660	0	0
T239	0	266	0	0
T240	0	440	0	0
T241	0	614	0	0
T242	0	842	0	0
T243	0	603	0	0
T244	0	1611	0	0
T245	0	874	0	0
T246	51443	0	0	0
T247	76401	0	0	0
T248	153922	0	0	0
T249	95059	0	0	0
T250	353130	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	735657	0	0
T1	26829	51	0	0
T2	166263	1182	0	0
T3	464880	3260	0	0
T4	1586648	3534	0	0
T5	3428224	20	0	0
T6	204876	0	0	0
T7	128533	0	0	0
T8	0	2014	0	0
T14	597712	3	0	0
T15	3422764	4014	0	0
T16	104295	1450	0	0
T18	130232	15	0	0
T19	1299448	101	0	0
T21	0	9519	0	0
T40	0	132	0	0
T41	0	115	0	0
T42	0	680	0	0
T44	0	86	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1535027089	0	0
T1	35772	14560	0	0
T2	221684	122056	0	0
T3	464880	233352	0	0
T4	1586648	815896	0	0
T5	3428224	1430137	0	0
T6	204876	61095	0	0
T14	597712	595493	0	0
T15	3422764	861718	0	0
T18	130232	98185	0	0
T19	1299448	875692	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T19
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T72,T237
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	675814448	2944	0	0
DisabledNoTrigBkwd_A	675814448	218222	0	0
DisabledNoTrigFwd_A	675814448	367321810	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	2944	0	0
T25	335865	0	0	0
T71	3788	887	0	0
T72	1343	477	0	0
T73	32008	0	0	0
T79	5341	0	0	0
T84	7366	0	0	0
T85	95250	0	0	0
T230	3085	0	0	0
T231	1315	0	0	0
T237	0	738	0	0
T242	0	842	0	0
T250	176565	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	218222	0	0
T1	8943	7	0	0
T2	55421	13	0	0
T3	116220	1692	0	0
T4	396662	2	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	4	0	0
T14	149428	3	0	0
T15	855691	1300	0	0
T16	0	2	0	0
T18	32558	15	0	0
T19	324862	22	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	367321810	0	0
T1	8943	1919	0	0
T2	55421	1952	0	0
T3	116220	619	0	0
T4	396662	396006	0	0
T5	857056	856975	0	0
T6	51219	3325	0	0
T14	149428	147636	0	0
T15	855691	3898	0	0
T18	32558	703	0	0
T19	324862	51753	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T229,T231,T233
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	675814448	6300	0	0
DisabledNoTrigBkwd_A	675814448	183195	0	0
DisabledNoTrigFwd_A	675814448	364593910	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	6300	0	0
T34	0	1044	0	0
T77	59493	0	0	0
T78	35164	0	0	0
T82	7613	0	0	0
T83	14425	0	0	0
T127	166721	0	0	0
T229	3316	1083	0	0
T231	0	597	0	0
T233	0	610	0	0
T235	0	505	0	0
T236	0	544	0	0
T240	0	440	0	0
T243	0	603	0	0
T245	0	874	0	0
T246	51443	0	0	0
T247	76401	0	0	0
T248	153922	0	0	0
T249	95059	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	183195	0	0
T3	116220	3	0	0
T4	396662	11	0	0
T5	857056	20	0	0
T6	51219	0	0	0
T7	128533	0	0	0
T8	0	682	0	0
T14	149428	0	0	0
T15	855691	23	0	0
T16	104295	0	0	0
T18	32558	0	0	0
T19	324862	57	0	0
T21	0	382	0	0
T41	0	2	0	0
T42	0	587	0	0
T44	0	86	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	364593910	0	0
T1	8943	4498	0	0
T2	55421	55323	0	0
T3	116220	115891	0	0
T4	396662	392673	0	0
T5	857056	98198	0	0
T6	51219	3335	0	0
T14	149428	149418	0	0
T15	855691	842560	0	0
T18	32558	32494	0	0
T19	324862	258325	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T230,T234,T241
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	675814448	1857	0	0
DisabledNoTrigBkwd_A	675814448	160281	0	0
DisabledNoTrigFwd_A	675814448	409594589	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1857	0	0
T24	154170	0	0	0
T79	5341	0	0	0
T80	54620	0	0	0
T84	7366	0	0	0
T85	95250	0	0	0
T230	3085	661	0	0
T231	1315	0	0	0
T234	0	582	0	0
T241	0	614	0	0
T250	176565	0	0	0
T251	27383	0	0	0
T252	388513	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	160281	0	0
T1	8943	42	0	0
T2	55421	0	0	0
T3	116220	1565	0	0
T4	396662	1857	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	976	0	0
T14	149428	0	0	0
T15	855691	1764	0	0
T18	32558	0	0	0
T19	324862	1	0	0
T21	0	7	0	0
T40	0	80	0	0
T41	0	40	0	0
T42	0	93	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	409594589	0	0
T1	8943	6283	0	0
T2	55421	55323	0	0
T3	116220	627	0	0
T4	396662	16857	0	0
T5	857056	471807	0	0
T6	51219	51056	0	0
T14	149428	149021	0	0
T15	855691	7841	0	0
T18	32558	32494	0	0
T19	324862	272731	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T232,T238,T239
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	675814448	3053	0	0
DisabledNoTrigBkwd_A	675814448	173959	0	0
DisabledNoTrigFwd_A	675814448	393516780	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	3053	0	0
T81	188714	0	0	0
T91	45531	0	0	0
T126	363359	0	0	0
T142	21177	0	0	0
T143	281148	0	0	0
T144	26215	0	0	0
T232	3868	516	0	0
T238	0	660	0	0
T239	0	266	0	0
T244	0	1611	0	0
T253	10244	0	0	0
T254	367292	0	0	0
T255	30276	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	173959	0	0
T1	8943	2	0	0
T2	55421	1169	0	0
T3	116220	0	0	0
T4	396662	1664	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	352	0	0
T14	149428	0	0	0
T15	855691	927	0	0
T16	0	1448	0	0
T18	32558	0	0	0
T19	324862	21	0	0
T21	0	9130	0	0
T40	0	52	0	0
T41	0	73	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	393516780	0	0
T1	8943	1860	0	0
T2	55421	9458	0	0
T3	116220	116215	0	0
T4	396662	10360	0	0
T5	857056	3157	0	0
T6	51219	3379	0	0
T14	149428	149418	0	0
T15	855691	7419	0	0
T18	32558	32494	0	0
T19	324862	292883	0	0