Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T20
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T18
1	0	1	Covered	T3,T4,T18
1	1	0	Covered	T1,T2,T19
1	1	1	Covered	T1,T19,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T21
0	1	Covered	T1,T19,T21
1	0	Covered	T21,T22,T23

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T21
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T21,T22,T23

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T21
1	0	Not Covered
1	1	Covered	T1,T19,T21

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T19,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T19,T21

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T19,T21
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T3,T21,T24
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T19,T21,T10
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T25,T24,T26
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T27,T28,T24
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T3,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T19,T21
TimeoutSt->Phase0St	172	Covered	T1,T19,T21

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T21,T22
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T21,T10,T22
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T25,T24,T26
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T28,T24
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	995	0	0
CheckAccumTrig0_A	2147483647	2219	0	0
CheckAccumTrig1_A	2147483647	129	0	0
CheckClr_A	2147483647	1023	0	0
CheckEn_A	2147483647	1216058301	0	0
CheckPhase0_A	2147483647	2554	0	0
CheckPhase1_A	2147483647	2509	0	0
CheckPhase2_A	2147483647	2453	0	0
CheckPhase3_A	2147483647	2394	0	0
CheckTimeout0_A	2147483647	4806	0	0
CheckTimeoutSt1_A	2147483647	481154	0	0
CheckTimeoutSt2_A	2147483647	4421	0	0
CheckTimeoutStTrig_A	2147483647	250	0	0
ErrorStAllEscAsserted_A	2147483647	5745	0	0
ErrorStIsTerminal_A	2147483647	4785	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	995	0	0
T11	67720	106	0	0
T12	0	239	0	0
T13	0	126	0	0
T29	0	262	0	0
T30	0	262	0	0
T31	3589064	0	0	0
T32	86640	0	0	0
T33	175752	0	0	0
T34	16740	0	0	0
T35	153016	0	0	0
T36	45284	0	0	0
T37	466316	0	0	0
T38	390740	0	0	0
T39	24644	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2219	0	0
T1	17886	2	0	0
T2	166263	2	0	0
T3	464880	10	0	0
T4	1586648	4	0	0
T5	3428224	1	0	0
T6	204876	0	0	0
T7	128533	0	0	0
T8	0	4	0	0
T14	597712	1	0	0
T15	3422764	5	0	0
T16	208590	3	0	0
T18	130232	1	0	0
T19	1299448	16	0	0
T21	0	12	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	129	0	0
T9	247818	0	0	0
T21	915540	4	0	0
T22	528564	1	0	0
T23	245463	1	0	0
T24	0	1	0	0
T26	0	1	0	0
T27	595166	0	0	0
T43	244062	0	0	0
T44	532688	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	771158	0	0	0
T62	208990	0	0	0
T63	897080	0	0	0
T64	785052	0	0	0
T65	110204	0	0	0
T66	21696	0	0	0
T67	19256	0	0	0
T68	27812	0	0	0
T69	36664	0	0	0
T70	301652	0	0	0
T71	3788	0	0	0
T72	1343	0	0	0
T73	32008	0	0	0
T74	67281	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1023	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	232440	7	0	0
T4	793324	1	0	0
T5	1714112	0	0	0
T6	102438	0	0	0
T7	128533	0	0	0
T9	123909	0	0	0
T10	0	2	0	0
T14	298856	0	0	0
T15	1711382	1	0	0
T16	104295	0	0	0
T18	65116	0	0	0
T19	649724	7	0	0
T21	457770	17	0	0
T22	0	9	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	4	0	0
T27	297583	1	0	0
T28	0	1	0	0
T43	122031	0	0	0
T61	385579	0	0	0
T62	104495	0	0	0
T63	448540	0	0	0
T64	392526	0	0	0
T65	55102	0	0	0
T67	0	4	0	0
T75	0	5	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1216058301	0	0
T1	35772	11996	0	0
T2	221684	118174	0	0
T3	464880	121138	0	0
T4	1586648	412623	0	0
T5	3428224	1430136	0	0
T6	204876	61090	0	0
T14	597712	448439	0	0
T15	3422764	8893	0	0
T18	130232	98182	0	0
T19	1299448	808601	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2554	0	0
T1	35772	4	0	0
T2	221684	2	0	0
T3	464880	9	0	0
T4	1586648	4	0	0
T5	3428224	1	0	0
T6	204876	0	0	0
T8	0	4	0	0
T14	597712	1	0	0
T15	3422764	5	0	0
T16	0	3	0	0
T18	130232	1	0	0
T19	1299448	17	0	0
T21	0	15	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2509	0	0
T1	35772	4	0	0
T2	221684	2	0	0
T3	464880	9	0	0
T4	1586648	4	0	0
T5	3428224	1	0	0
T6	204876	0	0	0
T8	0	4	0	0
T14	597712	1	0	0
T15	3422764	5	0	0
T16	0	3	0	0
T18	130232	1	0	0
T19	1299448	16	0	0
T21	0	14	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2453	0	0
T1	35772	4	0	0
T2	221684	2	0	0
T3	464880	9	0	0
T4	1586648	4	0	0
T5	3428224	1	0	0
T6	204876	0	0	0
T8	0	4	0	0
T14	597712	1	0	0
T15	3422764	5	0	0
T16	0	3	0	0
T18	130232	1	0	0
T19	1299448	16	0	0
T21	0	14	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2394	0	0
T1	35772	4	0	0
T2	221684	2	0	0
T3	464880	9	0	0
T4	1586648	4	0	0
T5	3428224	1	0	0
T6	204876	0	0	0
T8	0	4	0	0
T14	597712	1	0	0
T15	3422764	5	0	0
T16	0	3	0	0
T18	130232	1	0	0
T19	1299448	16	0	0
T21	0	13	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4806	0	0
T1	17886	4	0	0
T2	110842	0	0	0
T3	232440	0	0	0
T4	793324	0	0	0
T5	1714112	0	0	0
T6	102438	0	0	0
T7	257066	0	0	0
T8	507496	0	0	0
T14	597712	0	0	0
T15	3422764	0	0	0
T16	208590	0	0	0
T17	38218	0	0	0
T18	65116	0	0	0
T19	1299448	25	0	0
T21	0	37	0	0
T22	0	39	0	0
T23	0	6	0	0
T24	0	25	0	0
T25	0	4	0	0
T28	0	2	0	0
T40	144668	0	0	0
T41	87032	0	0	0
T42	218240	0	0	0
T62	0	1	0	0
T65	0	1	0	0
T67	0	4	0	0
T69	0	10	0	0
T73	0	1	0	0
T82	0	4	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	481154	0	0
T1	17886	1453	0	0
T2	110842	0	0	0
T3	232440	0	0	0
T4	793324	0	0	0
T5	1714112	0	0	0
T6	102438	0	0	0
T7	257066	0	0	0
T8	507496	0	0	0
T14	597712	0	0	0
T15	3422764	0	0	0
T16	208590	0	0	0
T17	38218	0	0	0
T18	65116	0	0	0
T19	1299448	1808	0	0
T21	0	5064	0	0
T22	0	1771	0	0
T23	0	1157	0	0
T24	0	2418	0	0
T25	0	186	0	0
T28	0	164	0	0
T40	144668	0	0	0
T41	87032	0	0	0
T42	218240	0	0	0
T62	0	63	0	0
T65	0	46	0	0
T67	0	1307	0	0
T69	0	600	0	0
T73	0	46	0	0
T82	0	359	0	0
T83	0	615	0	0
T84	0	95	0	0
T85	0	39	0	0
T86	0	131	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4421	0	0
T1	8943	2	0	0
T2	55421	0	0	0
T3	116220	0	0	0
T4	396662	0	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T7	385599	0	0	0
T8	761244	0	0	0
T14	597712	0	0	0
T15	3422764	0	0	0
T16	312885	0	0	0
T17	57327	0	0	0
T18	32558	0	0	0
T19	1299448	24	0	0
T21	0	31	0	0
T22	0	37	0	0
T23	0	4	0	0
T24	0	35	0	0
T25	0	4	0	0
T28	0	2	0	0
T40	217002	0	0	0
T41	130548	0	0	0
T42	327360	0	0	0
T65	0	1	0	0
T67	0	2	0	0
T69	0	10	0	0
T73	0	1	0	0
T82	0	4	0	0
T83	0	3	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	3	0	0
T87	0	18	0	0
T88	0	2	0	0
T89	0	5	0	0
T90	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	250	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	0	0	0
T4	396662	0	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T7	128533	0	0	0
T8	253748	0	0	0
T14	298856	0	0	0
T15	1711382	0	0	0
T16	104295	0	0	0
T17	19109	0	0	0
T18	32558	0	0	0
T19	649724	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	245463	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T33	0	1	0	0
T40	72334	0	0	0
T41	43516	0	0	0
T42	109120	0	0	0
T47	0	2	0	0
T66	21696	0	0	0
T67	19256	2	0	0
T68	27812	0	0	0
T74	0	2	0	0
T80	0	2	0	0
T88	0	3	0	0
T89	0	2	0	0
T90	0	2	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5745	0	0
T11	67720	686	0	0
T12	0	1407	0	0
T13	0	751	0	0
T29	0	1471	0	0
T30	0	1430	0	0
T31	3589064	0	0	0
T32	86640	0	0	0
T33	175752	0	0	0
T34	16740	0	0	0
T35	153016	0	0	0
T36	45284	0	0	0
T37	466316	0	0	0
T38	390740	0	0	0
T39	24644	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4785	0	0
T11	67720	566	0	0
T12	0	1167	0	0
T13	0	631	0	0
T29	0	1231	0	0
T30	0	1190	0	0
T31	3589064	0	0	0
T32	86640	0	0	0
T33	175752	0	0	0
T34	16740	0	0	0
T35	153016	0	0	0
T36	45284	0	0	0
T37	466316	0	0	0
T38	390740	0	0	0
T39	24644	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	35772	35536	0	0
T2	221684	221292	0	0
T3	464880	464860	0	0
T4	1586648	1586608	0	0
T5	3428224	3427900	0	0
T6	204876	204224	0	0
T14	597712	597672	0	0
T15	3422764	3422396	0	0
T18	130232	129976	0	0
T19	1299448	1296316	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	35772	35536	0	0
T2	221684	221292	0	0
T3	464880	464860	0	0
T4	1586648	1586608	0	0
T5	3428224	3427900	0	0
T6	204876	204224	0	0
T14	597712	597672	0	0
T15	3422764	3422396	0	0
T18	130232	129976	0	0
T19	1299448	1296316	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T21
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T1,T2,T19
1	1	1	Covered	T1,T19,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T21
0	1	Covered	T1,T21,T67
1	0	Covered	T21,T47,T48

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T47,T48

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T21
1	0	Not Covered
1	1	Covered	T1,T21,T67

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T19,T21,T97

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T5,T41,T42

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T19
1	Covered	T1,T4,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T19,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T19,T8,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T5,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T1,T19,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T3,T4,T5
IdleSt->TimeoutSt	159	Covered	T1,T19,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T98,T99,T100
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T10,T101,T102
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T50,T103,T104
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T105,T106,T107
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T19,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T19,T21
TimeoutSt->Phase0St	172	Covered	T1,T21,T67

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T67
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T98,T99,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T101,T102
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T50,T103,T104
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T105,T106,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T19,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	675814448	263	0	0
CheckAccumTrig0_A	675814448	517	0	0
CheckAccumTrig1_A	675814448	25	0	0
CheckClr_A	675814448	258	0	0
CheckEn_A	675666033	302495486	0	0
CheckPhase0_A	675814448	608	0	0
CheckPhase1_A	675814448	598	0	0
CheckPhase2_A	675814448	587	0	0
CheckPhase3_A	675814448	568	0	0
CheckTimeout0_A	675814448	1107	0	0
CheckTimeoutSt1_A	675814448	109453	0	0
CheckTimeoutSt2_A	675814448	1006	0	0
CheckTimeoutStTrig_A	675814448	75	0	0
ErrorStAllEscAsserted_A	675814448	1372	0	0
ErrorStIsTerminal_A	675814448	1132	0	0
EscStateOut_A	675664616	675595473	0	0
u_state_regs_A	675814448	675642911	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	263	0	0
T11	16930	28	0	0
T12	0	57	0	0
T13	0	45	0	0
T29	0	89	0	0
T30	0	44	0	0
T31	897266	0	0	0
T32	21660	0	0	0
T33	43938	0	0	0
T34	4185	0	0	0
T35	38254	0	0	0
T36	11321	0	0	0
T37	116579	0	0	0
T38	97685	0	0	0
T39	6161	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	517	0	0
T3	116220	1	0	0
T4	396662	1	0	0
T5	857056	1	0	0
T6	51219	0	0	0
T7	128533	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T16	104295	0	0	0
T18	32558	0	0	0
T19	324862	9	0	0
T21	0	6	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	25	0	0
T9	123909	0	0	0
T21	457770	1	0	0
T27	297583	0	0	0
T43	122031	0	0	0
T44	266344	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	385579	0	0	0
T62	104495	0	0	0
T63	448540	0	0	0
T64	392526	0	0	0
T65	55102	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	258	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	0	0	0
T4	396662	0	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T10	0	2	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T18	32558	0	0	0
T19	324862	7	0	0
T21	0	3	0	0
T22	0	1	0	0
T25	0	1	0	0
T76	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675666033	302495486	0	0
T1	8943	4497	0	0
T2	55421	55322	0	0
T3	116220	3677	0	0
T4	396662	3114	0	0
T5	857056	98198	0	0
T6	51219	3334	0	0
T14	149428	149418	0	0
T15	855691	586	0	0
T18	32558	32493	0	0
T19	324862	254585	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	608	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	1	0	0
T4	396662	1	0	0
T5	857056	1	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T18	32558	0	0	0
T19	324862	9	0	0
T21	0	8	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	598	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	1	0	0
T4	396662	1	0	0
T5	857056	1	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T18	32558	0	0	0
T19	324862	9	0	0
T21	0	8	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	587	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	1	0	0
T4	396662	1	0	0
T5	857056	1	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T18	32558	0	0	0
T19	324862	9	0	0
T21	0	8	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	568	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	1	0	0
T4	396662	1	0	0
T5	857056	1	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T18	32558	0	0	0
T19	324862	9	0	0
T21	0	8	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1107	0	0
T1	8943	3	0	0
T2	55421	0	0	0
T3	116220	0	0	0
T4	396662	0	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T18	32558	0	0	0
T19	324862	8	0	0
T21	0	4	0	0
T22	0	34	0	0
T23	0	1	0	0
T28	0	1	0	0
T67	0	1	0	0
T69	0	6	0	0
T82	0	4	0	0
T83	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	109453	0	0
T1	8943	1429	0	0
T2	55421	0	0	0
T3	116220	0	0	0
T4	396662	0	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T18	32558	0	0	0
T19	324862	448	0	0
T21	0	388	0	0
T22	0	1208	0	0
T23	0	313	0	0
T28	0	82	0	0
T67	0	572	0	0
T69	0	349	0	0
T82	0	359	0	0
T83	0	258	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1006	0	0
T1	8943	2	0	0
T2	55421	0	0	0
T3	116220	0	0	0
T4	396662	0	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T18	32558	0	0	0
T19	324862	8	0	0
T21	0	2	0	0
T22	0	34	0	0
T23	0	1	0	0
T25	0	1	0	0
T28	0	1	0	0
T69	0	6	0	0
T82	0	4	0	0
T83	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	75	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	0	0	0
T4	396662	0	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T18	32558	0	0	0
T19	324862	0	0	0
T21	0	1	0	0
T47	0	2	0	0
T67	0	1	0	0
T74	0	1	0	0
T80	0	2	0	0
T88	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1372	0	0
T11	16930	162	0	0
T12	0	305	0	0
T13	0	192	0	0
T29	0	367	0	0
T30	0	346	0	0
T31	897266	0	0	0
T32	21660	0	0	0
T33	43938	0	0	0
T34	4185	0	0	0
T35	38254	0	0	0
T36	11321	0	0	0
T37	116579	0	0	0
T38	97685	0	0	0
T39	6161	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1132	0	0
T11	16930	132	0	0
T12	0	245	0	0
T13	0	162	0	0
T29	0	307	0	0
T30	0	286	0	0
T31	897266	0	0	0
T32	21660	0	0	0
T33	43938	0	0	0
T34	4185	0	0	0
T35	38254	0	0	0
T36	11321	0	0	0
T37	116579	0	0	0
T38	97685	0	0	0
T39	6161	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675664616	675595473	0	0
T1	8943	8884	0	0
T2	55421	55323	0	0
T3	116220	116215	0	0
T4	396662	396652	0	0
T5	857056	856975	0	0
T6	51219	51056	0	0
T14	149428	149418	0	0
T15	855691	855599	0	0
T18	32558	32494	0	0
T19	324862	324079	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	675642911	0	0
T1	8943	8884	0	0
T2	55421	55323	0	0
T3	116220	116215	0	0
T4	396662	396652	0	0
T5	857056	856975	0	0
T6	51219	51056	0	0
T14	149428	149418	0	0
T15	855691	855599	0	0
T18	32558	32494	0	0
T19	324862	324079	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T21
1	0	1	Covered	T3,T5,T19
1	1	0	Covered	T1,T2,T19
1	1	1	Covered	T19,T21,T28

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T28
0	1	Covered	T23,T25,T88
1	0	Covered	T22,T45,T108

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T19,T21,T28
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T45,T108

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T28
1	0	Not Covered
1	1	Covered	T23,T25,T88

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T19
1	Covered	T1,T40,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T8
1	Covered	T3,T4,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T15,T8,T42

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T41,T21,T61

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T19,T15,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T19,T21,T28

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T19,T21,T28
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T109,T110,T111
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T21,T112,T50
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T24,T113,T114
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T28,T88
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T19,T21,T75
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T19,T21,T28
TimeoutSt->Phase0St	172	Covered	T22,T23,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T28
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T28
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T28
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T109,T111,T115
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T21,T112,T50
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T113,T114
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T28,T88
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T75,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	675814448	236	0	0
CheckAccumTrig0_A	675814448	444	0	0
CheckAccumTrig1_A	675814448	37	0	0
CheckClr_A	675814448	209	0	0
CheckEn_A	675666033	347802267	0	0
CheckPhase0_A	675814448	527	0	0
CheckPhase1_A	675814448	513	0	0
CheckPhase2_A	675814448	502	0	0
CheckPhase3_A	675814448	489	0	0
CheckTimeout0_A	675814448	1862	0	0
CheckTimeoutSt1_A	675814448	162761	0	0
CheckTimeoutSt2_A	675814448	1770	0	0
CheckTimeoutStTrig_A	675814448	51	0	0
ErrorStAllEscAsserted_A	675814448	1480	0	0
ErrorStIsTerminal_A	675814448	1240	0	0
EscStateOut_A	675664616	675595473	0	0
u_state_regs_A	675814448	675642911	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	236	0	0
T11	16930	28	0	0
T12	0	73	0	0
T13	0	29	0	0
T29	0	32	0	0
T30	0	74	0	0
T31	897266	0	0	0
T32	21660	0	0	0
T33	43938	0	0	0
T34	4185	0	0	0
T35	38254	0	0	0
T36	11321	0	0	0
T37	116579	0	0	0
T38	97685	0	0	0
T39	6161	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	444	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	1	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T18	32558	0	0	0
T19	324862	1	0	0
T21	0	3	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	37	0	0
T22	528564	1	0	0
T23	245463	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T66	21696	0	0	0
T67	19256	0	0	0
T68	27812	0	0	0
T69	36664	0	0	0
T70	301652	0	0	0
T71	3788	0	0	0
T72	1343	0	0	0
T73	32008	0	0	0
T108	0	1	0	0
T114	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	209	0	0
T9	123909	0	0	0
T21	457770	3	0	0
T22	0	2	0	0
T24	0	1	0	0
T25	0	1	0	0
T27	297583	1	0	0
T28	0	1	0	0
T43	122031	0	0	0
T44	266344	0	0	0
T61	385579	0	0	0
T62	104495	0	0	0
T63	448540	0	0	0
T64	392526	0	0	0
T65	55102	0	0	0
T67	0	3	0	0
T75	0	5	0	0
T88	0	1	0	0
T121	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675666033	347802267	0	0
T1	8943	6283	0	0
T2	55421	55322	0	0
T3	116220	627	0	0
T4	396662	3143	0	0
T5	857056	471807	0	0
T6	51219	51054	0	0
T14	149428	149021	0	0
T15	855691	590	0	0
T18	32558	32493	0	0
T19	324862	248162	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	527	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	1	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T18	32558	0	0	0
T19	324862	1	0	0
T21	0	3	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	513	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	1	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T18	32558	0	0	0
T19	324862	1	0	0
T21	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	502	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	1	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T18	32558	0	0	0
T19	324862	1	0	0
T21	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	489	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	1	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T18	32558	0	0	0
T19	324862	1	0	0
T21	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1862	0	0
T7	128533	0	0	0
T8	253748	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T16	104295	0	0	0
T17	19109	0	0	0
T19	324862	4	0	0
T21	0	19	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	21	0	0
T25	0	1	0	0
T28	0	1	0	0
T40	72334	0	0	0
T41	43516	0	0	0
T42	109120	0	0	0
T67	0	2	0	0
T84	0	1	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	162761	0	0
T7	128533	0	0	0
T8	253748	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T16	104295	0	0	0
T17	19109	0	0	0
T19	324862	262	0	0
T21	0	2937	0	0
T22	0	1	0	0
T23	0	289	0	0
T24	0	1858	0	0
T25	0	65	0	0
T28	0	82	0	0
T40	72334	0	0	0
T41	43516	0	0	0
T42	109120	0	0	0
T67	0	14	0	0
T84	0	53	0	0
T86	0	131	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1770	0	0
T7	128533	0	0	0
T8	253748	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T16	104295	0	0	0
T17	19109	0	0	0
T19	324862	4	0	0
T21	0	19	0	0
T24	0	21	0	0
T28	0	1	0	0
T40	72334	0	0	0
T41	43516	0	0	0
T42	109120	0	0	0
T67	0	2	0	0
T84	0	1	0	0
T86	0	1	0	0
T88	0	2	0	0
T89	0	5	0	0
T90	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	51	0	0
T23	245463	1	0	0
T25	335865	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T66	21696	0	0	0
T67	19256	0	0	0
T68	27812	0	0	0
T69	36664	0	0	0
T70	301652	0	0	0
T71	3788	0	0	0
T72	1343	0	0	0
T73	32008	0	0	0
T74	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	2	0	0
T99	0	1	0	0
T122	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1480	0	0
T11	16930	173	0	0
T12	0	353	0	0
T13	0	180	0	0
T29	0	389	0	0
T30	0	385	0	0
T31	897266	0	0	0
T32	21660	0	0	0
T33	43938	0	0	0
T34	4185	0	0	0
T35	38254	0	0	0
T36	11321	0	0	0
T37	116579	0	0	0
T38	97685	0	0	0
T39	6161	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1240	0	0
T11	16930	143	0	0
T12	0	293	0	0
T13	0	150	0	0
T29	0	329	0	0
T30	0	325	0	0
T31	897266	0	0	0
T32	21660	0	0	0
T33	43938	0	0	0
T34	4185	0	0	0
T35	38254	0	0	0
T36	11321	0	0	0
T37	116579	0	0	0
T38	97685	0	0	0
T39	6161	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675664616	675595473	0	0
T1	8943	8884	0	0
T2	55421	55323	0	0
T3	116220	116215	0	0
T4	396662	396652	0	0
T5	857056	856975	0	0
T6	51219	51056	0	0
T14	149428	149418	0	0
T15	855691	855599	0	0
T18	32558	32494	0	0
T19	324862	324079	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	675642911	0	0
T1	8943	8884	0	0
T2	55421	55323	0	0
T3	116220	116215	0	0
T4	396662	396652	0	0
T5	857056	856975	0	0
T6	51219	51056	0	0
T14	149428	149418	0	0
T15	855691	855599	0	0
T18	32558	32494	0	0
T19	324862	324079	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T19
1	0	1	Covered	T19,T16,T8
1	1	0	Covered	T19,T41,T21
1	1	1	Covered	T1,T19,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T21
0	1	Covered	T1,T21,T62
1	0	Covered	T74,T47,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T74,T47,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T21
1	0	Not Covered
1	1	Covered	T1,T21,T62

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T19
1	Covered	T4,T19,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T19,T8,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T19
1	Covered	T1,T19,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T2,T40,T61

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T19,T16,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T19,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T1,T19,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T4,T19
IdleSt->TimeoutSt	159	Covered	T1,T19,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T22,T123,T53
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T22,T124,T125
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T22,T24,T53
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T21,T22,T126
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T19,T16,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T19,T21,T65
TimeoutSt->Phase0St	172	Covered	T1,T21,T62

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T62
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T65
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T22,T123,T53
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T22,T124,T125
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T22,T24,T53
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T126
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T16,T127
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	675814448	247	0	0
CheckAccumTrig0_A	675814448	492	0	0
CheckAccumTrig1_A	675814448	15	0	0
CheckClr_A	675814448	186	0	0
CheckEn_A	675666033	305365489	0	0
CheckPhase0_A	675814448	549	0	0
CheckPhase1_A	675814448	545	0	0
CheckPhase2_A	675814448	532	0	0
CheckPhase3_A	675814448	520	0	0
CheckTimeout0_A	675814448	1107	0	0
CheckTimeoutSt1_A	675814448	116250	0	0
CheckTimeoutSt2_A	675814448	1034	0	0
CheckTimeoutStTrig_A	675814448	57	0	0
ErrorStAllEscAsserted_A	675814448	1454	0	0
ErrorStIsTerminal_A	675814448	1214	0	0
EscStateOut_A	675664616	675595473	0	0
u_state_regs_A	675814448	675642911	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	247	0	0
T11	16930	22	0	0
T12	0	61	0	0
T13	0	22	0	0
T29	0	64	0	0
T30	0	78	0	0
T31	897266	0	0	0
T32	21660	0	0	0
T33	43938	0	0	0
T34	4185	0	0	0
T35	38254	0	0	0
T36	11321	0	0	0
T37	116579	0	0	0
T38	97685	0	0	0
T39	6161	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	492	0	0
T2	55421	1	0	0
T3	116220	0	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T16	104295	2	0	0
T18	32558	0	0	0
T19	324862	3	0	0
T21	0	3	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	15	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T74	67281	1	0	0
T109	573891	0	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	217504	0	0	0
T135	193693	0	0	0
T136	10850	0	0	0
T137	546584	0	0	0
T138	160341	0	0	0
T139	654241	0	0	0
T140	91096	0	0	0
T141	245174	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	186	0	0
T7	128533	0	0	0
T8	253748	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T16	104295	1	0	0
T17	19109	0	0	0
T19	324862	1	0	0
T21	0	1	0	0
T22	0	12	0	0
T23	0	1	0	0
T24	0	2	0	0
T25	0	3	0	0
T40	72334	0	0	0
T41	43516	0	0	0
T42	109120	0	0	0
T127	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675666033	305365489	0	0
T1	8943	614	0	0
T2	55421	5578	0	0
T3	116220	116215	0	0
T4	396662	10360	0	0
T5	857056	3157	0	0
T6	51219	3378	0	0
T14	149428	149418	0	0
T15	855691	3819	0	0
T18	32558	32493	0	0
T19	324862	255145	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	549	0	0
T1	8943	1	0	0
T2	55421	1	0	0
T3	116220	0	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T16	0	2	0	0
T18	32558	0	0	0
T19	324862	3	0	0
T21	0	4	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	545	0	0
T1	8943	1	0	0
T2	55421	1	0	0
T3	116220	0	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T16	0	2	0	0
T18	32558	0	0	0
T19	324862	3	0	0
T21	0	4	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	532	0	0
T1	8943	1	0	0
T2	55421	1	0	0
T3	116220	0	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T16	0	2	0	0
T18	32558	0	0	0
T19	324862	3	0	0
T21	0	4	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	520	0	0
T1	8943	1	0	0
T2	55421	1	0	0
T3	116220	0	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T16	0	2	0	0
T18	32558	0	0	0
T19	324862	3	0	0
T21	0	3	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1107	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	0	0	0
T4	396662	0	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T18	32558	0	0	0
T19	324862	3	0	0
T21	0	4	0	0
T22	0	2	0	0
T23	0	3	0	0
T24	0	4	0	0
T25	0	2	0	0
T62	0	1	0	0
T65	0	1	0	0
T84	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	116250	0	0
T1	8943	24	0	0
T2	55421	0	0	0
T3	116220	0	0	0
T4	396662	0	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T18	32558	0	0	0
T19	324862	191	0	0
T21	0	705	0	0
T22	0	470	0	0
T23	0	548	0	0
T24	0	560	0	0
T25	0	47	0	0
T62	0	63	0	0
T65	0	46	0	0
T84	0	42	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1034	0	0
T7	128533	0	0	0
T8	253748	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T16	104295	0	0	0
T17	19109	0	0	0
T19	324862	3	0	0
T21	0	3	0	0
T22	0	2	0	0
T23	0	3	0	0
T24	0	3	0	0
T25	0	2	0	0
T40	72334	0	0	0
T41	43516	0	0	0
T42	109120	0	0	0
T65	0	1	0	0
T86	0	2	0	0
T87	0	7	0	0
T144	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	57	0	0
T1	8943	1	0	0
T2	55421	0	0	0
T3	116220	0	0	0
T4	396662	0	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T18	32558	0	0	0
T19	324862	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T62	0	1	0	0
T84	0	1	0	0
T89	0	1	0	0
T94	0	1	0	0
T96	0	2	0	0
T118	0	1	0	0
T145	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1454	0	0
T11	16930	180	0	0
T12	0	364	0	0
T13	0	201	0	0
T29	0	345	0	0
T30	0	364	0	0
T31	897266	0	0	0
T32	21660	0	0	0
T33	43938	0	0	0
T34	4185	0	0	0
T35	38254	0	0	0
T36	11321	0	0	0
T37	116579	0	0	0
T38	97685	0	0	0
T39	6161	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1214	0	0
T11	16930	150	0	0
T12	0	304	0	0
T13	0	171	0	0
T29	0	285	0	0
T30	0	304	0	0
T31	897266	0	0	0
T32	21660	0	0	0
T33	43938	0	0	0
T34	4185	0	0	0
T35	38254	0	0	0
T36	11321	0	0	0
T37	116579	0	0	0
T38	97685	0	0	0
T39	6161	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675664616	675595473	0	0
T1	8943	8884	0	0
T2	55421	55323	0	0
T3	116220	116215	0	0
T4	396662	396652	0	0
T5	857056	856975	0	0
T6	51219	51056	0	0
T14	149428	149418	0	0
T15	855691	855599	0	0
T18	32558	32494	0	0
T19	324862	324079	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	675642911	0	0
T1	8943	8884	0	0
T2	55421	55323	0	0
T3	116220	116215	0	0
T4	396662	396652	0	0
T5	857056	856975	0	0
T6	51219	51056	0	0
T14	149428	149418	0	0
T15	855691	855599	0	0
T18	32558	32494	0	0
T19	324862	324079	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T20
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T18
1	0	1	Covered	T18,T19,T15
1	1	0	Covered	T19,T41,T21
1	1	1	Covered	T19,T21,T83

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T83
0	1	Covered	T19,T22,T67
1	0	Covered	T21,T23,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T19,T21,T83
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T23,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T83
1	0	Not Covered
1	1	Covered	T19,T22,T67

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T1,T4,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T19,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T2,T16,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T77,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T19,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T19,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T19,T21,T83

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T19,T21,T83
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T3,T21,T24
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T19,T21,T22
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T25,T26,T146
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T24,T105,T49
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T19,T21,T83
TimeoutSt->Phase0St	172	Covered	T19,T21,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T83
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T83
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T83
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T21,T24
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T21,T22,T147
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T25,T26,T146
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T105,T49
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	675814448	249	0	0
CheckAccumTrig0_A	675814448	766	0	0
CheckAccumTrig1_A	675814448	52	0	0
CheckClr_A	675814448	370	0	0
CheckEn_A	675666033	260395059	0	0
CheckPhase0_A	675814448	870	0	0
CheckPhase1_A	675814448	853	0	0
CheckPhase2_A	675814448	832	0	0
CheckPhase3_A	675814448	817	0	0
CheckTimeout0_A	675814448	730	0	0
CheckTimeoutSt1_A	675814448	92690	0	0
CheckTimeoutSt2_A	675814448	611	0	0
CheckTimeoutStTrig_A	675814448	67	0	0
ErrorStAllEscAsserted_A	675814448	1439	0	0
ErrorStIsTerminal_A	675814448	1199	0	0
EscStateOut_A	675664616	675595473	0	0
u_state_regs_A	675814448	675642911	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	249	0	0
T11	16930	28	0	0
T12	0	48	0	0
T13	0	30	0	0
T29	0	77	0	0
T30	0	66	0	0
T31	897266	0	0	0
T32	21660	0	0	0
T33	43938	0	0	0
T34	4185	0	0	0
T35	38254	0	0	0
T36	11321	0	0	0
T37	116579	0	0	0
T38	97685	0	0	0
T39	6161	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	766	0	0
T1	8943	1	0	0
T2	55421	1	0	0
T3	116220	8	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	1	0	0
T15	855691	2	0	0
T16	0	1	0	0
T18	32558	1	0	0
T19	324862	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	52	0	0
T9	123909	0	0	0
T21	457770	3	0	0
T23	0	1	0	0
T24	0	1	0	0
T26	0	1	0	0
T27	297583	0	0	0
T43	122031	0	0	0
T44	266344	0	0	0
T46	0	1	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T61	385579	0	0	0
T62	104495	0	0	0
T63	448540	0	0	0
T64	392526	0	0	0
T65	55102	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	370	0	0
T3	116220	7	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T7	128533	0	0	0
T14	149428	0	0	0
T15	855691	1	0	0
T16	104295	0	0	0
T18	32558	0	0	0
T19	324862	0	0	0
T21	0	11	0	0
T22	0	6	0	0
T23	0	1	0	0
T25	0	2	0	0
T67	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675666033	260395059	0	0
T1	8943	602	0	0
T2	55421	1952	0	0
T3	116220	619	0	0
T4	396662	396006	0	0
T5	857056	856974	0	0
T6	51219	3324	0	0
T14	149428	582	0	0
T15	855691	3898	0	0
T18	32558	703	0	0
T19	324862	50709	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	870	0	0
T1	8943	1	0	0
T2	55421	1	0	0
T3	116220	7	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	1	0	0
T15	855691	2	0	0
T16	0	1	0	0
T18	32558	1	0	0
T19	324862	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	853	0	0
T1	8943	1	0	0
T2	55421	1	0	0
T3	116220	7	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	1	0	0
T15	855691	2	0	0
T16	0	1	0	0
T18	32558	1	0	0
T19	324862	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	832	0	0
T1	8943	1	0	0
T2	55421	1	0	0
T3	116220	7	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	1	0	0
T15	855691	2	0	0
T16	0	1	0	0
T18	32558	1	0	0
T19	324862	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	817	0	0
T1	8943	1	0	0
T2	55421	1	0	0
T3	116220	7	0	0
T4	396662	1	0	0
T5	857056	0	0	0
T6	51219	0	0	0
T8	0	1	0	0
T14	149428	1	0	0
T15	855691	2	0	0
T16	0	1	0	0
T18	32558	1	0	0
T19	324862	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	730	0	0
T7	128533	0	0	0
T8	253748	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T16	104295	0	0	0
T17	19109	0	0	0
T19	324862	10	0	0
T21	0	10	0	0
T22	0	2	0	0
T23	0	1	0	0
T25	0	1	0	0
T40	72334	0	0	0
T41	43516	0	0	0
T42	109120	0	0	0
T67	0	1	0	0
T69	0	4	0	0
T73	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	92690	0	0
T7	128533	0	0	0
T8	253748	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T16	104295	0	0	0
T17	19109	0	0	0
T19	324862	907	0	0
T21	0	1034	0	0
T22	0	92	0	0
T23	0	7	0	0
T25	0	74	0	0
T40	72334	0	0	0
T41	43516	0	0	0
T42	109120	0	0	0
T67	0	721	0	0
T69	0	251	0	0
T73	0	46	0	0
T83	0	357	0	0
T85	0	39	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	611	0	0
T7	128533	0	0	0
T8	253748	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T16	104295	0	0	0
T17	19109	0	0	0
T19	324862	9	0	0
T21	0	7	0	0
T22	0	1	0	0
T24	0	11	0	0
T25	0	1	0	0
T40	72334	0	0	0
T41	43516	0	0	0
T42	109120	0	0	0
T69	0	4	0	0
T73	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0
T87	0	11	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	67	0	0
T7	128533	0	0	0
T8	253748	0	0	0
T14	149428	0	0	0
T15	855691	0	0	0
T16	104295	0	0	0
T17	19109	0	0	0
T19	324862	1	0	0
T22	0	1	0	0
T24	0	1	0	0
T33	0	1	0	0
T40	72334	0	0	0
T41	43516	0	0	0
T42	109120	0	0	0
T67	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T92	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1439	0	0
T11	16930	171	0	0
T12	0	385	0	0
T13	0	178	0	0
T29	0	370	0	0
T30	0	335	0	0
T31	897266	0	0	0
T32	21660	0	0	0
T33	43938	0	0	0
T34	4185	0	0	0
T35	38254	0	0	0
T36	11321	0	0	0
T37	116579	0	0	0
T38	97685	0	0	0
T39	6161	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	1199	0	0
T11	16930	141	0	0
T12	0	325	0	0
T13	0	148	0	0
T29	0	310	0	0
T30	0	275	0	0
T31	897266	0	0	0
T32	21660	0	0	0
T33	43938	0	0	0
T34	4185	0	0	0
T35	38254	0	0	0
T36	11321	0	0	0
T37	116579	0	0	0
T38	97685	0	0	0
T39	6161	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675664616	675595473	0	0
T1	8943	8884	0	0
T2	55421	55323	0	0
T3	116220	116215	0	0
T4	396662	396652	0	0
T5	857056	856975	0	0
T6	51219	51056	0	0
T14	149428	149418	0	0
T15	855691	855599	0	0
T18	32558	32494	0	0
T19	324862	324079	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675814448	675642911	0	0
T1	8943	8884	0	0
T2	55421	55323	0	0
T3	116220	116215	0	0
T4	396662	396652	0	0
T5	857056	856975	0	0
T6	51219	51056	0	0
T14	149428	149418	0	0
T15	855691	855599	0	0
T18	32558	32494	0	0
T19	324862	324079	0	0