Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65459736	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31753285

1

T1

2516

T2

1857

T3

1429

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14679942	1			T1	1253		T2	772		T3	784
values[0x0]	40203236	1			T1	3348		T2	2543		T3	1864
values[0x1]	42329843	1			T1	3366		T2	2635		T3	1888

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55853280	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41359741

1

T1

3200

T2

2386

T3

1816

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	306071	1			T2	27		T4	1601		T5	24
valid_sources[0x01]	303115	1			T2	41		T4	1762		T5	31
valid_sources[0x02]	315968	1			T2	24		T4	1717		T5	21
valid_sources[0x03]	303324	1			T2	7		T4	1701		T5	34
valid_sources[0x04]	529231	1			T1	7967		T2	51		T4	1764
valid_sources[0x05]	299236	1			T2	32		T4	1759		T5	22
valid_sources[0x06]	583055	1			T2	9		T4	1621		T5	17
valid_sources[0x07]	302769	1			T2	8		T4	1805		T5	24
valid_sources[0x08]	310280	1			T2	14		T4	1677		T5	21
valid_sources[0x09]	295796	1			T2	16		T4	1577		T5	19
valid_sources[0x0a]	293374	1			T2	20		T4	1665		T5	38
valid_sources[0x0b]	315181	1			T2	14		T4	1615		T5	31
valid_sources[0x0c]	311064	1			T2	16		T4	1880		T5	23
valid_sources[0x0d]	790411	1			T2	28		T4	1762		T5	26
valid_sources[0x0e]	511343	1			T2	49		T4	1726		T5	29
valid_sources[0x0f]	316129	1			T4	1603		T5	31		T18	19
valid_sources[0x10]	313225	1			T2	12		T4	1643		T5	35
valid_sources[0x11]	345875	1			T2	27		T4	1654		T5	27
valid_sources[0x12]	302595	1			T2	19		T4	1668		T5	21
valid_sources[0x13]	311768	1			T2	18		T4	1506		T5	15
valid_sources[0x14]	309974	1			T2	43		T4	1767		T5	36
valid_sources[0x15]	316552	1			T2	11		T4	1855		T5	25
valid_sources[0x16]	312010	1			T2	41		T4	1692		T5	32
valid_sources[0x17]	310226	1			T2	16		T4	1758		T5	31
valid_sources[0x18]	300776	1			T2	23		T4	1563		T5	20
valid_sources[0x19]	311997	1			T2	36		T4	1507		T5	26
valid_sources[0x1a]	299676	1			T2	7		T4	1705		T5	43
valid_sources[0x1b]	745262	1			T2	13		T4	1632		T5	32
valid_sources[0x1c]	605558	1			T2	20		T4	1697		T5	14
valid_sources[0x1d]	313453	1			T2	19		T4	1547		T5	30
valid_sources[0x1e]	304054	1			T2	15		T4	1644		T5	38
valid_sources[0x1f]	305358	1			T2	20		T4	1803		T5	23
valid_sources[0x20]	304954	1			T2	39		T4	1741		T5	29
valid_sources[0x21]	302154	1			T2	18		T4	1693		T5	32
valid_sources[0x22]	1452966	1			T2	13		T4	1971		T5	27
valid_sources[0x23]	306594	1			T2	56		T4	1829		T5	9
valid_sources[0x24]	311591	1			T2	13		T4	1830		T5	18
valid_sources[0x25]	317632	1			T4	1852		T5	27		T18	44
valid_sources[0x26]	308272	1			T2	32		T4	1786		T5	28
valid_sources[0x27]	301625	1			T2	18		T4	1899		T5	33
valid_sources[0x28]	296017	1			T2	58		T4	1687		T5	34
valid_sources[0x29]	298774	1			T2	36		T4	2025		T5	38
valid_sources[0x2a]	356992	1			T2	25		T4	1847		T5	31
valid_sources[0x2b]	924519	1			T2	66		T4	1623		T5	18
valid_sources[0x2c]	695946	1			T2	2		T4	1771		T5	31
valid_sources[0x2d]	300622	1			T2	33		T4	1851		T5	28
valid_sources[0x2e]	299607	1			T2	1		T4	1684		T5	33
valid_sources[0x2f]	316406	1			T2	23		T4	1694		T5	29
valid_sources[0x30]	300789	1			T4	1710		T17	6376		T5	27
valid_sources[0x31]	297407	1			T2	28		T4	1582		T5	13
valid_sources[0x32]	302966	1			T2	23		T4	1673		T5	21
valid_sources[0x33]	299614	1			T2	3		T4	1883		T5	48
valid_sources[0x34]	423208	1			T2	43		T4	1830		T5	21
valid_sources[0x35]	301223	1			T2	13		T4	1807		T5	18
valid_sources[0x36]	680876	1			T2	12		T4	1653		T5	22
valid_sources[0x37]	310586	1			T2	46		T4	1562		T5	28
valid_sources[0x38]	306472	1			T2	22		T4	1714		T5	25
valid_sources[0x39]	306044	1			T4	1660		T5	26		T18	27
valid_sources[0x3a]	308425	1			T2	15		T4	1496		T5	30
valid_sources[0x3b]	299631	1			T2	7		T4	1714		T5	40
valid_sources[0x3c]	304032	1			T2	23		T4	1559		T5	26
valid_sources[0x3d]	312359	1			T2	61		T4	1698		T5	25
valid_sources[0x3e]	310488	1			T2	9		T4	1750		T5	15
valid_sources[0x3f]	307935	1			T2	47		T4	1946		T5	27
valid_sources[0x40]	313867	1			T2	20		T4	1804		T5	29
valid_sources[0x41]	302853	1			T2	7		T4	1717		T5	22
valid_sources[0x42]	318104	1			T2	27		T4	1674		T5	37
valid_sources[0x43]	315234	1			T2	19		T4	1752		T5	15
valid_sources[0x44]	296978	1			T2	23		T4	1710		T5	21
valid_sources[0x45]	320303	1			T2	39		T4	1670		T5	23
valid_sources[0x46]	304748	1			T2	43		T4	1752		T5	18
valid_sources[0x47]	314625	1			T2	35		T4	1740		T5	32
valid_sources[0x48]	301043	1			T2	22		T4	1798		T5	17
valid_sources[0x49]	505735	1			T2	47		T4	1998		T5	32
valid_sources[0x4a]	306157	1			T2	13		T4	1618		T5	21
valid_sources[0x4b]	302897	1			T2	7		T4	1664		T5	22
valid_sources[0x4c]	307670	1			T2	25		T4	1714		T5	26
valid_sources[0x4d]	825335	1			T2	30		T4	1874		T5	33
valid_sources[0x4e]	344707	1			T2	7		T4	1535		T5	20
valid_sources[0x4f]	293579	1			T2	52		T4	1811		T5	23
valid_sources[0x50]	298847	1			T2	7		T4	1621		T5	25
valid_sources[0x51]	302882	1			T2	51		T4	1923		T5	25
valid_sources[0x52]	297408	1			T2	72		T4	1599		T5	23
valid_sources[0x53]	912431	1			T4	1785		T5	25		T18	16
valid_sources[0x54]	306725	1			T2	36		T4	1797		T5	24
valid_sources[0x55]	609255	1			T2	26		T4	1645		T5	17
valid_sources[0x56]	305818	1			T2	18		T4	1734		T5	25
valid_sources[0x57]	302671	1			T2	39		T4	1575		T5	24
valid_sources[0x58]	305106	1			T2	36		T4	1698		T5	22
valid_sources[0x59]	313219	1			T2	27		T4	1800		T5	24
valid_sources[0x5a]	304057	1			T2	29		T4	1663		T5	17
valid_sources[0x5b]	303084	1			T2	64		T4	1667		T5	27
valid_sources[0x5c]	746766	1			T4	1624		T5	18		T18	46
valid_sources[0x5d]	316793	1			T2	65		T4	1799		T5	23
valid_sources[0x5e]	307733	1			T2	22		T4	1480		T5	22
valid_sources[0x5f]	325082	1			T2	44		T4	1630		T5	20
valid_sources[0x60]	306924	1			T2	42		T4	1908		T5	22
valid_sources[0x61]	314711	1			T2	17		T4	1728		T5	25
valid_sources[0x62]	296894	1			T2	28		T4	1712		T5	22
valid_sources[0x63]	306662	1			T2	12		T4	1758		T5	32
valid_sources[0x64]	307698	1			T2	5		T4	1770		T5	17
valid_sources[0x65]	316862	1			T2	16		T4	1677		T5	36
valid_sources[0x66]	738273	1			T4	1707		T5	32		T18	19
valid_sources[0x67]	299797	1			T2	1		T4	1666		T5	22
valid_sources[0x68]	295194	1			T2	12		T4	1912		T5	27
valid_sources[0x69]	298090	1			T2	5		T4	1766		T5	23
valid_sources[0x6a]	300963	1			T2	53		T4	1905		T5	24
valid_sources[0x6b]	302059	1			T2	10		T4	1779		T5	37
valid_sources[0x6c]	307455	1			T2	24		T4	1642		T5	27
valid_sources[0x6d]	300974	1			T2	22		T4	1651		T5	19
valid_sources[0x6e]	292529	1			T2	78		T4	1755		T5	22
valid_sources[0x6f]	301240	1			T2	36		T4	1511		T5	20
valid_sources[0x70]	302507	1			T2	34		T4	1770		T5	23
valid_sources[0x71]	684377	1			T2	21		T4	1751		T5	23
valid_sources[0x72]	688862	1			T2	28		T4	1649		T5	24
valid_sources[0x73]	294355	1			T2	59		T4	1720		T5	23
valid_sources[0x74]	997166	1			T2	21		T4	1702		T5	30
valid_sources[0x75]	299214	1			T2	3		T4	1893		T5	15
valid_sources[0x76]	309586	1			T2	5		T4	1685		T5	17
valid_sources[0x77]	316699	1			T4	1747		T5	28		T18	4
valid_sources[0x78]	295537	1			T2	7		T4	1682		T5	31
valid_sources[0x79]	295146	1			T2	22		T4	1634		T5	24
valid_sources[0x7a]	310716	1			T2	4		T4	1760		T5	27
valid_sources[0x7b]	316943	1			T2	11		T4	1587		T5	24
valid_sources[0x7c]	314277	1			T2	40		T4	1608		T5	13
valid_sources[0x7d]	317308	1			T2	14		T4	1899		T5	16
valid_sources[0x7e]	301538	1			T2	16		T4	2033		T5	33
valid_sources[0x7f]	294730	1			T2	18		T4	1855		T5	24
valid_sources[0x80]	298341	1			T2	63		T4	1886		T5	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7310664

1

T1

658

T2

381

T3

388

values[0x0]

all_enables

biggest_size

15416050

1

T1

1191

T2

916

T3

673

values[0x1]

all_enables

biggest_size

9026571

1

T1

667

T2

560

T3

368