Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T207,T208
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13832	0	0
DisabledNoTrigBkwd_A	2147483647	792893	0	0
DisabledNoTrigFwd_A	2147483647	1576640340	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13832	0	0
T50	528991	0	0	0
T90	565786	0	0	0
T199	0	424	0	0
T207	1602	778	0	0
T208	0	705	0	0
T209	0	635	0	0
T210	0	729	0	0
T211	0	639	0	0
T212	0	528	0	0
T213	4130	780	0	0
T214	0	449	0	0
T215	0	689	0	0
T216	0	320	0	0
T217	0	397	0	0
T218	3447	981	0	0
T219	0	562	0	0
T220	0	1229	0	0
T221	0	783	0	0
T222	0	942	0	0
T223	0	433	0	0
T224	0	1623	0	0
T225	0	206	0	0
T226	380978	0	0	0
T227	29687	0	0	0
T228	316013	0	0	0
T229	66110	0	0	0
T230	7225	0	0	0
T231	8897	0	0	0
T232	232156	0	0	0
T233	403392	0	0	0
T234	136823	0	0	0
T235	37657	0	0	0
T236	533048	0	0	0
T237	10196	0	0	0
T238	283398	0	0	0
T239	326536	0	0	0
T240	824856	0	0	0
T241	22853	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	792893	0	0
T1	84678	70	0	0
T2	76212	0	0	0
T3	1774716	4	0	0
T4	680160	4116	0	0
T5	74452	47	0	0
T6	659124	439	0	0
T7	278480	1786	0	0
T8	798241	5	0	0
T13	0	6124	0	0
T14	0	9	0	0
T15	0	539	0	0
T16	0	717	0	0
T17	105344	6	0	0
T18	249220	0	0	0
T19	312084	91	0	0
T20	1378728	6145	0	0
T22	0	897	0	0
T29	0	98	0	0
T43	0	242	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1576640340	0	0
T1	112904	67336	0	0
T2	101616	84852	0	0
T3	1774716	1214277	0	0
T4	680160	360884	0	0
T5	74452	23629	0	0
T6	659124	590685	0	0
T17	105344	78493	0	0
T18	249220	248924	0	0
T19	312084	131916	0	0
T20	1378728	1572501	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207,T211,T217
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T17,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	728249920	3870	0	0
DisabledNoTrigBkwd_A	728249920	252052	0	0
DisabledNoTrigFwd_A	728249920	354037805	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	3870	0	0
T50	528991	0	0	0
T90	565786	0	0	0
T207	1602	778	0	0
T211	0	639	0	0
T217	0	397	0	0
T223	0	433	0	0
T224	0	1623	0	0
T226	380978	0	0	0
T227	29687	0	0	0
T228	316013	0	0	0
T229	66110	0	0	0
T230	7225	0	0	0
T231	8897	0	0	0
T232	232156	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	252052	0	0
T1	28226	50	0	0
T2	25404	0	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	5	0	0
T6	164781	285	0	0
T7	0	829	0	0
T8	0	1	0	0
T13	0	6124	0	0
T17	26336	6	0	0
T18	62305	0	0	0
T19	78021	11	0	0
T20	344682	3279	0	0
T29	0	98	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	354037805	0	0
T1	28226	610	0	0
T2	25404	20221	0	0
T3	443679	375469	0	0
T4	170040	170035	0	0
T5	18613	7761	0	0
T6	164781	127051	0	0
T17	26336	730	0	0
T18	62305	62231	0	0
T19	78021	3151	0	0
T20	344682	183302	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T218,T219,T220
1	1	Covered	T3,T4,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	728249920	2772	0	0
DisabledNoTrigBkwd_A	728249920	186061	0	0
DisabledNoTrigFwd_A	728249920	395100702	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	2772	0	0
T218	3447	981	0	0
T219	0	562	0	0
T220	0	1229	0	0
T233	403392	0	0	0
T234	136823	0	0	0
T235	37657	0	0	0
T236	533048	0	0	0
T237	10196	0	0	0
T238	283398	0	0	0
T239	326536	0	0	0
T240	824856	0	0	0
T241	22853	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	186061	0	0
T3	443679	1	0	0
T4	170040	1	0	0
T5	18613	16	0	0
T6	164781	27	0	0
T7	278480	957	0	0
T8	798241	0	0	0
T15	0	141	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	80	0	0
T20	344682	1182	0	0
T22	0	222	0	0
T43	0	242	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	395100702	0	0
T1	28226	28158	0	0
T2	25404	25305	0	0
T3	443679	331561	0	0
T4	170040	169193	0	0
T5	18613	6235	0	0
T6	164781	156515	0	0
T17	26336	26263	0	0
T18	62305	62231	0	0
T19	78021	3177	0	0
T20	344682	163329	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T213,T216,T222
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	728249920	2042	0	0
DisabledNoTrigBkwd_A	728249920	163147	0	0
DisabledNoTrigFwd_A	728249920	424428360	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	2042	0	0
T59	398050	0	0	0
T60	303353	0	0	0
T213	4130	780	0	0
T214	3854	0	0	0
T216	0	320	0	0
T222	0	942	0	0
T242	50318	0	0	0
T243	89818	0	0	0
T244	237522	0	0	0
T245	9185	0	0	0
T246	60818	0	0	0
T247	909108	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	163147	0	0
T1	28226	8	0	0
T2	25404	0	0	0
T3	443679	0	0	0
T4	170040	1673	0	0
T5	18613	12	0	0
T6	164781	121	0	0
T8	0	2	0	0
T14	0	3	0	0
T15	0	231	0	0
T16	0	717	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	0	0	0
T20	344682	193	0	0
T22	0	138	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	424428360	0	0
T1	28226	20970	0	0
T2	25404	14021	0	0
T3	443679	375469	0	0
T4	170040	13936	0	0
T5	18613	6100	0	0
T6	164781	144241	0	0
T17	26336	25237	0	0
T18	62305	62231	0	0
T19	78021	71530	0	0
T20	344682	256228	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T208,T209
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	728249920	5148	0	0
DisabledNoTrigBkwd_A	728249920	191633	0	0
DisabledNoTrigFwd_A	728249920	403073473	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	5148	0	0
T78	157834	0	0	0
T89	64312	0	0	0
T199	2827	424	0	0
T200	149506	0	0	0
T201	64357	0	0	0
T202	21241	0	0	0
T203	4394	0	0	0
T208	0	705	0	0
T209	0	635	0	0
T210	0	729	0	0
T212	0	528	0	0
T214	0	449	0	0
T215	0	689	0	0
T221	0	783	0	0
T225	0	206	0	0
T248	987132	0	0	0
T249	2362	0	0	0
T250	72964	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	191633	0	0
T1	28226	12	0	0
T2	25404	0	0	0
T3	443679	3	0	0
T4	170040	2442	0	0
T5	18613	14	0	0
T6	164781	6	0	0
T8	0	2	0	0
T14	0	6	0	0
T15	0	167	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	0	0	0
T20	344682	1491	0	0
T22	0	537	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	403073473	0	0
T1	28226	17598	0	0
T2	25404	25305	0	0
T3	443679	131778	0	0
T4	170040	7720	0	0
T5	18613	3533	0	0
T6	164781	162878	0	0
T17	26336	26263	0	0
T18	62305	62231	0	0
T19	78021	54058	0	0
T20	344682	969642	0	0