Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T21
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T17
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T1,T2,T19
1	1	1	Covered	T1,T2,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T22,T16,T23

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T22,T16,T23

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T24,T25
1	1	Covered	T1,T2,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T2,T17,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T17

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T1,T2,T5
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T22,T26,T27
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T15,T16,T28
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T19,T6,T20
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T6,T29,T30
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T19,T6
TimeoutSt->Phase0St	172	Covered	T1,T2,T5

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T14,T22,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T15,T16,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T6,T20
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T29,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1037	0	0
CheckAccumTrig0_A	2147483647	2386	0	0
CheckAccumTrig1_A	2147483647	112	0	0
CheckClr_A	2147483647	1071	0	0
CheckEn_A	2147483647	1212313781	0	0
CheckPhase0_A	2147483647	2680	0	0
CheckPhase1_A	2147483647	2622	0	0
CheckPhase2_A	2147483647	2573	0	0
CheckPhase3_A	2147483647	2521	0	0
CheckTimeout0_A	2147483647	4642	0	0
CheckTimeoutSt1_A	2147483647	531204	0	0
CheckTimeoutSt2_A	2147483647	4299	0	0
CheckTimeoutStTrig_A	2147483647	225	0	0
ErrorStAllEscAsserted_A	2147483647	4968	0	0
ErrorStIsTerminal_A	2147483647	4128	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1037	0	0
T10	132656	313	0	0
T11	0	314	0	0
T12	0	126	0	0
T31	0	150	0	0
T32	0	134	0	0
T33	1356808	0	0	0
T34	421544	0	0	0
T35	492060	0	0	0
T36	936440	0	0	0
T37	136652	0	0	0
T38	1827232	0	0	0
T39	611440	0	0	0
T40	326324	0	0	0
T41	229380	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2386	0	0
T1	84678	3	0	0
T2	76212	0	0	0
T3	1774716	2	0	0
T4	680160	3	0	0
T5	74452	3	0	0
T6	659124	23	0	0
T7	278480	2	0	0
T8	798241	3	0	0
T13	0	1	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	0	4	0	0
T17	105344	1	0	0
T18	249220	0	0	0
T19	312084	1	0	0
T20	1378728	7	0	0
T22	0	15	0	0
T29	0	3	0	0
T30	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	112	0	0
T9	192929	0	0	0
T16	1652886	7	0	0
T22	118764	3	0	0
T23	0	2	0	0
T26	748904	0	0	0
T28	768488	0	0	0
T43	190177	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	14159	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	5	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	76069	0	0	0
T63	57849	0	0	0
T64	665624	0	0	0
T65	32110	0	0	0
T66	816228	0	0	0
T67	313787	0	0	0
T68	27348	0	0	0
T69	123595	0	0	0
T70	228603	0	0	0
T71	244013	0	0	0
T72	539159	0	0	0
T73	433071	0	0	0
T74	125891	0	0	0
T75	32746	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1071	0	0
T1	28226	1	0	0
T2	50808	1	0	0
T3	887358	0	0	0
T4	510120	1	0	0
T5	55839	0	0	0
T6	659124	11	0	0
T7	556960	0	0	0
T8	2394723	0	0	0
T13	334266	0	0	0
T15	0	4	0	0
T16	0	17	0	0
T17	79008	0	0	0
T18	186915	0	0	0
T19	312084	4	0	0
T20	1378728	1	0	0
T22	0	8	0	0
T23	0	4	0	0
T26	0	3	0	0
T28	0	1	0	0
T29	40078	2	0	0
T30	12306	2	0	0
T42	95897	0	0	0
T67	0	2	0	0
T76	0	3	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	7	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	36787	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1212313781	0	0
T1	112904	37917	0	0
T2	101616	84849	0	0
T3	1774716	1214275	0	0
T4	680160	353920	0	0
T5	74452	12006	0	0
T6	659124	747050	0	0
T17	105344	78490	0	0
T18	249220	248920	0	0
T19	312084	131914	0	0
T20	1378728	1572498	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2680	0	0
T1	84678	4	0	0
T2	76212	1	0	0
T3	1774716	2	0	0
T4	680160	3	0	0
T5	74452	4	0	0
T6	659124	25	0	0
T7	278480	2	0	0
T8	798241	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	6	0	0
T17	105344	1	0	0
T18	249220	0	0	0
T19	312084	7	0	0
T20	1378728	9	0	0
T22	0	7	0	0
T82	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2622	0	0
T1	84678	4	0	0
T2	76212	1	0	0
T3	1774716	2	0	0
T4	680160	3	0	0
T5	74452	4	0	0
T6	659124	25	0	0
T7	278480	2	0	0
T8	798241	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	6	0	0
T17	105344	1	0	0
T18	249220	0	0	0
T19	312084	7	0	0
T20	1378728	9	0	0
T22	0	7	0	0
T82	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2573	0	0
T1	84678	4	0	0
T2	76212	1	0	0
T3	1774716	2	0	0
T4	680160	3	0	0
T5	74452	4	0	0
T6	659124	24	0	0
T7	278480	2	0	0
T8	798241	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	6	0	0
T17	105344	1	0	0
T18	249220	0	0	0
T19	312084	6	0	0
T20	1378728	8	0	0
T22	0	7	0	0
T82	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2521	0	0
T1	84678	4	0	0
T2	76212	1	0	0
T3	1774716	2	0	0
T4	680160	3	0	0
T5	74452	4	0	0
T6	659124	23	0	0
T7	278480	2	0	0
T8	798241	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	6	0	0
T17	105344	1	0	0
T18	249220	0	0	0
T19	312084	6	0	0
T20	1378728	8	0	0
T22	0	7	0	0
T82	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4642	0	0
T1	28226	1	0	0
T2	50808	4	0	0
T3	887358	0	0	0
T4	340080	0	0	0
T5	37226	1	0	0
T6	659124	65	0	0
T7	556960	0	0	0
T8	2394723	0	0	0
T13	334266	0	0	0
T15	0	12	0	0
T16	0	156	0	0
T17	52672	0	0	0
T18	124610	0	0	0
T19	234063	11	0	0
T20	1378728	3	0	0
T22	0	11	0	0
T28	0	2	0	0
T29	80156	0	0	0
T30	24612	0	0	0
T42	191794	0	0	0
T63	0	1	0	0
T65	0	3	0	0
T66	0	21	0	0
T68	0	1	0	0
T77	0	87	0	0
T82	73574	4	0	0
T83	0	3	0	0
T84	19954	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	531204	0	0
T1	28226	79	0	0
T2	50808	205	0	0
T3	887358	0	0	0
T4	340080	0	0	0
T5	37226	100	0	0
T6	659124	5499	0	0
T7	556960	0	0	0
T8	2394723	0	0	0
T13	334266	0	0	0
T15	0	1895	0	0
T16	0	12507	0	0
T17	52672	0	0	0
T18	124610	0	0	0
T19	234063	3050	0	0
T20	1378728	1560	0	0
T22	0	900	0	0
T28	0	120	0	0
T29	80156	0	0	0
T30	24612	0	0	0
T42	191794	0	0	0
T63	0	47	0	0
T65	0	352	0	0
T66	0	3874	0	0
T68	0	145	0	0
T77	0	11608	0	0
T82	73574	709	0	0
T83	0	542	0	0
T84	19954	0	0	0
T85	0	1784	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4299	0	0
T2	50808	3	0	0
T3	887358	0	0	0
T4	340080	0	0	0
T5	37226	0	0	0
T6	659124	63	0	0
T7	556960	0	0	0
T8	3192964	0	0	0
T13	334266	0	0	0
T15	0	10	0	0
T16	0	148	0	0
T17	52672	0	0	0
T18	124610	0	0	0
T19	234063	5	0	0
T20	1378728	1	0	0
T22	0	7	0	0
T28	0	1	0	0
T29	80156	0	0	0
T30	24612	0	0	0
T42	191794	0	0	0
T63	0	1	0	0
T65	0	2	0	0
T66	0	21	0	0
T68	0	1	0	0
T77	0	167	0	0
T82	73574	3	0	0
T83	0	3	0	0
T84	19954	0	0	0
T85	0	14	0	0
T86	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	225	0	0
T1	28226	1	0	0
T2	50808	1	0	0
T3	887358	0	0	0
T4	340080	0	0	0
T5	37226	1	0	0
T6	494343	2	0	0
T7	556960	0	0	0
T8	2394723	0	0	0
T13	334266	0	0	0
T14	369678	0	0	0
T15	0	1	0	0
T17	52672	0	0	0
T18	124610	0	0	0
T19	234063	5	0	0
T20	1378728	2	0	0
T22	0	1	0	0
T23	0	2	0	0
T29	80156	0	0	0
T30	24612	0	0	0
T42	191794	0	0	0
T46	0	1	0	0
T49	0	2	0	0
T50	0	2	0	0
T52	0	1	0	0
T54	0	3	0	0
T65	0	1	0	0
T80	0	4	0	0
T82	73574	1	0	0
T84	19954	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4968	0	0
T10	132656	1410	0	0
T11	0	1437	0	0
T12	0	719	0	0
T31	0	669	0	0
T32	0	733	0	0
T33	1356808	0	0	0
T34	421544	0	0	0
T35	492060	0	0	0
T36	936440	0	0	0
T37	136652	0	0	0
T38	1827232	0	0	0
T39	611440	0	0	0
T40	326324	0	0	0
T41	229380	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4128	0	0
T10	132656	1170	0	0
T11	0	1197	0	0
T12	0	599	0	0
T31	0	549	0	0
T32	0	613	0	0
T33	1356808	0	0	0
T34	421544	0	0	0
T35	492060	0	0	0
T36	936440	0	0	0
T37	136652	0	0	0
T38	1827232	0	0	0
T39	611440	0	0	0
T40	326324	0	0	0
T41	229380	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	112904	112632	0	0
T2	101616	101220	0	0
T3	1774716	1774508	0	0
T4	680160	680140	0	0
T5	74452	74132	0	0
T6	659124	658804	0	0
T17	105344	105052	0	0
T18	249220	248924	0	0
T19	312084	311748	0	0
T20	1378728	1378680	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	112904	112632	0	0
T2	101616	101220	0	0
T3	1774716	1774508	0	0
T4	680160	680140	0	0
T5	74452	74132	0	0
T6	659124	658804	0	0
T17	105344	105052	0	0
T18	249220	248924	0	0
T19	312084	311748	0	0
T20	1378728	1378680	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T19
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T2,T19,T6
1	1	1	Covered	T19,T6,T15

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T19,T6,T15
0	1	Covered	T19,T89,T44
1	0	Covered	T15,T22,T16

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T19,T6,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T22,T16

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T6,T15
1	0	Not Covered
1	1	Covered	T19,T89,T44

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T20,T14,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T3,T4,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T15,T22,T43

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T19
1	Covered	T1,T5,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T6,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T19,T6,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T19,T6,T15
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T14,T69,T46
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T22,T67,T90
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T91,T90,T92
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T72,T91,T93
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T19,T6,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T19,T6,T15
TimeoutSt->Phase0St	172	Covered	T19,T15,T16

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T6,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T15,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T19,T6,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T6,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T14,T69,T46
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T22,T67,T90
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T91,T90,T92
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T72,T91,T93
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T6,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	728249920	197	0	0
CheckAccumTrig0_A	728249920	508	0	0
CheckAccumTrig1_A	728249920	23	0	0
CheckClr_A	728249920	213	0	0
CheckEn_A	728039355	314333748	0	0
CheckPhase0_A	728249920	579	0	0
CheckPhase1_A	728249920	568	0	0
CheckPhase2_A	728249920	558	0	0
CheckPhase3_A	728249920	549	0	0
CheckTimeout0_A	728249920	1262	0	0
CheckTimeoutSt1_A	728249920	155940	0	0
CheckTimeoutSt2_A	728249920	1184	0	0
CheckTimeoutStTrig_A	728249920	55	0	0
ErrorStAllEscAsserted_A	728249920	1220	0	0
ErrorStIsTerminal_A	728249920	1010	0	0
EscStateOut_A	728037453	727967243	0	0
u_state_regs_A	728249920	728090017	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	197	0	0
T10	33164	51	0	0
T11	0	71	0	0
T12	0	12	0	0
T31	0	25	0	0
T32	0	38	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T36	234110	0	0	0
T37	34163	0	0	0
T38	456808	0	0	0
T39	152860	0	0	0
T40	81581	0	0	0
T41	57345	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	508	0	0
T1	28226	1	0	0
T2	25404	0	0	0
T3	443679	1	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	2	0	0
T8	0	1	0	0
T14	0	3	0	0
T15	0	1	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	0	0	0
T20	344682	3	0	0
T22	0	9	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	23	0	0
T9	192929	0	0	0
T15	105093	1	0	0
T16	826443	1	0	0
T22	118764	0	0	0
T28	0	1	0	0
T43	190177	0	0	0
T62	76069	0	0	0
T63	57849	0	0	0
T72	0	2	0	0
T80	0	1	0	0
T83	55945	0	0	0
T89	0	1	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	5000	0	0	0
T99	5115	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	213	0	0
T6	164781	2	0	0
T7	278480	0	0	0
T8	798241	0	0	0
T13	167133	0	0	0
T14	0	2	0	0
T16	0	2	0	0
T19	78021	1	0	0
T20	344682	0	0	0
T22	0	7	0	0
T29	40078	0	0	0
T30	12306	0	0	0
T42	95897	0	0	0
T67	0	1	0	0
T69	0	1	0	0
T78	0	1	0	0
T82	36787	0	0	0
T86	0	1	0	0
T89	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728039355	314333748	0	0
T1	28226	3559	0	0
T2	25404	25304	0	0
T3	443679	131778	0	0
T4	170040	756	0	0
T5	18613	1985	0	0
T6	164781	162877	0	0
T17	26336	26262	0	0
T18	62305	62230	0	0
T19	78021	54057	0	0
T20	344682	969640	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	579	0	0
T1	28226	1	0	0
T2	25404	0	0	0
T3	443679	1	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	2	0	0
T8	0	1	0	0
T14	0	2	0	0
T15	0	2	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	568	0	0
T1	28226	1	0	0
T2	25404	0	0	0
T3	443679	1	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	2	0	0
T8	0	1	0	0
T14	0	2	0	0
T15	0	2	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	558	0	0
T1	28226	1	0	0
T2	25404	0	0	0
T3	443679	1	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	2	0	0
T8	0	1	0	0
T14	0	2	0	0
T15	0	2	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	549	0	0
T1	28226	1	0	0
T2	25404	0	0	0
T3	443679	1	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	2	0	0
T8	0	1	0	0
T14	0	2	0	0
T15	0	2	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	1262	0	0
T6	164781	3	0	0
T7	278480	0	0	0
T8	798241	0	0	0
T13	167133	0	0	0
T15	0	4	0	0
T16	0	74	0	0
T19	78021	2	0	0
T20	344682	0	0	0
T22	0	4	0	0
T28	0	1	0	0
T29	40078	0	0	0
T30	12306	0	0	0
T42	95897	0	0	0
T65	0	1	0	0
T66	0	11	0	0
T77	0	85	0	0
T82	36787	0	0	0
T83	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	155940	0	0
T6	164781	341	0	0
T7	278480	0	0	0
T8	798241	0	0	0
T13	167133	0	0	0
T15	0	729	0	0
T16	0	6294	0	0
T19	78021	316	0	0
T20	344682	0	0	0
T22	0	380	0	0
T29	40078	0	0	0
T30	12306	0	0	0
T42	95897	0	0	0
T65	0	126	0	0
T66	0	2036	0	0
T77	0	11109	0	0
T82	36787	0	0	0
T83	0	346	0	0
T85	0	1784	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	1184	0	0
T6	164781	3	0	0
T7	278480	0	0	0
T8	798241	0	0	0
T13	167133	0	0	0
T15	0	3	0	0
T16	0	73	0	0
T19	78021	1	0	0
T20	344682	0	0	0
T22	0	4	0	0
T29	40078	0	0	0
T30	12306	0	0	0
T42	95897	0	0	0
T65	0	1	0	0
T66	0	11	0	0
T77	0	85	0	0
T82	36787	0	0	0
T83	0	2	0	0
T85	0	10	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	55	0	0
T6	164781	0	0	0
T7	278480	0	0	0
T8	798241	0	0	0
T13	167133	0	0	0
T19	78021	1	0	0
T20	344682	0	0	0
T29	40078	0	0	0
T30	12306	0	0	0
T42	95897	0	0	0
T44	0	1	0	0
T50	0	2	0	0
T52	0	1	0	0
T82	36787	0	0	0
T89	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	1220	0	0
T10	33164	315	0	0
T11	0	389	0	0
T12	0	175	0	0
T31	0	147	0	0
T32	0	194	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T36	234110	0	0	0
T37	34163	0	0	0
T38	456808	0	0	0
T39	152860	0	0	0
T40	81581	0	0	0
T41	57345	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	1010	0	0
T10	33164	255	0	0
T11	0	329	0	0
T12	0	145	0	0
T31	0	117	0	0
T32	0	164	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T36	234110	0	0	0
T37	34163	0	0	0
T38	456808	0	0	0
T39	152860	0	0	0
T40	81581	0	0	0
T41	57345	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728037453	727967243	0	0
T1	28226	28158	0	0
T2	25404	25305	0	0
T3	443679	443627	0	0
T4	170040	170035	0	0
T5	18613	18533	0	0
T6	164781	164701	0	0
T17	26336	26263	0	0
T18	62305	62231	0	0
T19	78021	77937	0	0
T20	344682	344670	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	728090017	0	0
T1	28226	28158	0	0
T2	25404	25305	0	0
T3	443679	443627	0	0
T4	170040	170035	0	0
T5	18613	18533	0	0
T6	164781	164701	0	0
T17	26336	26263	0	0
T18	62305	62231	0	0
T19	78021	77937	0	0
T20	344682	344670	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T17,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T2,T6,T20
1	1	1	Covered	T2,T5,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T19
0	1	Covered	T2,T5,T19
1	0	Covered	T22,T16,T23

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T5,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T16,T23

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T25
1	1	Covered	T2,T5,T19

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T20,T29,T30

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T17,T5
1	Covered	T1,T6,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T2,T17,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T5,T19,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T17,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T19,T6,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T17,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T17,T5,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T17
Phase1St	198	Covered	T1,T2,T17
Phase2St	215	Covered	T1,T2,T17
Phase3St	233	Covered	T1,T2,T17
TerminalSt	249	Covered	T1,T2,T17
TimeoutSt	159	Covered	T2,T5,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T17,T6
IdleSt->TimeoutSt	159	Covered	T2,T5,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T22,T27,T44
Phase0St->Phase1St	198	Covered	T1,T2,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T15,T16,T28
Phase1St->Phase2St	215	Covered	T1,T2,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T19,T38,T105
Phase2St->Phase3St	233	Covered	T1,T2,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T30,T16
Phase3St->TerminalSt	249	Covered	T1,T2,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T19,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T19,T6
TimeoutSt->Phase0St	172	Covered	T2,T5,T19

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T22,T27,T44
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T15,T16,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T38,T105
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T19,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	728249920	273	0	0
CheckAccumTrig0_A	728249920	862	0	0
CheckAccumTrig1_A	728249920	51	0	0
CheckClr_A	728249920	413	0	0
CheckEn_A	728039355	259167858	0	0
CheckPhase0_A	728249920	939	0	0
CheckPhase1_A	728249920	916	0	0
CheckPhase2_A	728249920	898	0	0
CheckPhase3_A	728249920	882	0	0
CheckTimeout0_A	728249920	1419	0	0
CheckTimeoutSt1_A	728249920	152288	0	0
CheckTimeoutSt2_A	728249920	1318	0	0
CheckTimeoutStTrig_A	728249920	48	0	0
ErrorStAllEscAsserted_A	728249920	1243	0	0
ErrorStIsTerminal_A	728249920	1033	0	0
EscStateOut_A	728037453	727967243	0	0
u_state_regs_A	728249920	728090017	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	273	0	0
T10	33164	72	0	0
T11	0	90	0	0
T12	0	45	0	0
T31	0	36	0	0
T32	0	30	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T36	234110	0	0	0
T37	34163	0	0	0
T38	456808	0	0	0
T39	152860	0	0	0
T40	81581	0	0	0
T41	57345	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	862	0	0
T1	28226	1	0	0
T2	25404	0	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	0	0	0
T6	164781	11	0	0
T7	0	1	0	0
T8	0	1	0	0
T13	0	1	0	0
T17	26336	1	0	0
T18	62305	0	0	0
T19	78021	0	0	0
T20	344682	1	0	0
T29	0	3	0	0
T30	0	2	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	51	0	0
T9	192929	0	0	0
T16	826443	6	0	0
T22	118764	3	0	0
T23	0	1	0	0
T28	384244	0	0	0
T43	190177	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T52	0	2	0	0
T53	0	5	0	0
T62	76069	0	0	0
T63	57849	0	0	0
T64	332812	0	0	0
T65	16055	0	0	0
T66	408114	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	413	0	0
T2	25404	1	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	0	0	0
T6	164781	4	0	0
T8	798241	0	0	0
T15	0	2	0	0
T16	0	15	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	3	0	0
T20	344682	0	0	0
T22	0	6	0	0
T28	0	1	0	0
T29	0	2	0	0
T30	0	2	0	0
T76	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728039355	259167858	0	0
T1	28226	610	0	0
T2	25404	20221	0	0
T3	443679	375468	0	0
T4	170040	170035	0	0
T5	18613	3335	0	0
T6	164781	36551	0	0
T17	26336	730	0	0
T18	62305	62230	0	0
T19	78021	3151	0	0
T20	344682	183301	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	939	0	0
T1	28226	1	0	0
T2	25404	1	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	1	0	0
T6	164781	11	0	0
T7	0	1	0	0
T8	0	1	0	0
T13	0	1	0	0
T17	26336	1	0	0
T18	62305	0	0	0
T19	78021	4	0	0
T20	344682	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	916	0	0
T1	28226	1	0	0
T2	25404	1	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	1	0	0
T6	164781	11	0	0
T7	0	1	0	0
T8	0	1	0	0
T13	0	1	0	0
T17	26336	1	0	0
T18	62305	0	0	0
T19	78021	4	0	0
T20	344682	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	898	0	0
T1	28226	1	0	0
T2	25404	1	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	1	0	0
T6	164781	11	0	0
T7	0	1	0	0
T8	0	1	0	0
T13	0	1	0	0
T17	26336	1	0	0
T18	62305	0	0	0
T19	78021	3	0	0
T20	344682	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	882	0	0
T1	28226	1	0	0
T2	25404	1	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	1	0	0
T6	164781	11	0	0
T7	0	1	0	0
T8	0	1	0	0
T13	0	1	0	0
T17	26336	1	0	0
T18	62305	0	0	0
T19	78021	3	0	0
T20	344682	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	1419	0	0
T2	25404	2	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	1	0	0
T6	164781	31	0	0
T8	798241	0	0	0
T16	0	6	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	7	0	0
T20	344682	2	0	0
T22	0	4	0	0
T65	0	1	0	0
T77	0	2	0	0
T83	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	152288	0	0
T2	25404	88	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	100	0	0
T6	164781	2656	0	0
T8	798241	0	0	0
T16	0	9	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	2451	0	0
T20	344682	1460	0	0
T22	0	160	0	0
T65	0	126	0	0
T77	0	499	0	0
T83	0	196	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	1318	0	0
T2	25404	1	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	0	0	0
T6	164781	31	0	0
T8	798241	0	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	3	0	0
T20	344682	1	0	0
T22	0	1	0	0
T65	0	1	0	0
T77	0	2	0	0
T83	0	1	0	0
T85	0	2	0	0
T86	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	48	0	0
T2	25404	1	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	1	0	0
T6	164781	0	0	0
T8	798241	0	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	4	0	0
T20	344682	1	0	0
T23	0	1	0	0
T46	0	1	0	0
T50	0	1	0	0
T80	0	2	0	0
T85	0	1	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	1243	0	0
T10	33164	353	0	0
T11	0	351	0	0
T12	0	193	0	0
T31	0	154	0	0
T32	0	192	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T36	234110	0	0	0
T37	34163	0	0	0
T38	456808	0	0	0
T39	152860	0	0	0
T40	81581	0	0	0
T41	57345	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	1033	0	0
T10	33164	293	0	0
T11	0	291	0	0
T12	0	163	0	0
T31	0	124	0	0
T32	0	162	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T36	234110	0	0	0
T37	34163	0	0	0
T38	456808	0	0	0
T39	152860	0	0	0
T40	81581	0	0	0
T41	57345	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728037453	727967243	0	0
T1	28226	28158	0	0
T2	25404	25305	0	0
T3	443679	443627	0	0
T4	170040	170035	0	0
T5	18613	18533	0	0
T6	164781	164701	0	0
T17	26336	26263	0	0
T18	62305	62231	0	0
T19	78021	77937	0	0
T20	344682	344670	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	728090017	0	0
T1	28226	28158	0	0
T2	25404	25305	0	0
T3	443679	443627	0	0
T4	170040	170035	0	0
T5	18613	18533	0	0
T6	164781	164701	0	0
T17	26336	26263	0	0
T18	62305	62231	0	0
T19	78021	77937	0	0
T20	344682	344670	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T19,T6,T20
1	0	1	Covered	T3,T4,T20
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T6,T20,T82

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T20,T82
0	1	Covered	T20,T82,T15
1	0	Covered	T16,T23,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T20,T82
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T23,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T82
1	0	Covered	T24
1	1	Covered	T20,T82,T15

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T19,T6,T20
1	Covered	T3,T4,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T6,T20,T7

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T82,T15,T63

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T19,T6,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T6,T20,T82

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T4,T5
Phase1St	198	Covered	T3,T4,T5
Phase2St	215	Covered	T3,T4,T5
Phase3St	233	Covered	T3,T4,T5
TerminalSt	249	Covered	T3,T4,T5
TimeoutSt	159	Covered	T6,T20,T82

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T3,T4,T5
IdleSt->TimeoutSt	159	Covered	T6,T20,T82
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T26,T78,T54
Phase0St->Phase1St	198	Covered	T3,T4,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T67,T106,T87
Phase1St->Phase2St	215	Covered	T3,T4,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T6,T73,T107
Phase2St->Phase3St	233	Covered	T3,T4,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T26,T47,T51
Phase3St->TerminalSt	249	Covered	T3,T4,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T6,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T82,T15
TimeoutSt->Phase0St	172	Covered	T20,T82,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T82
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T82,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T82
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T82,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T78,T54
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T67,T106,T87
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T73,T107
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T47,T51
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T6,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	728249920	248	0	0
CheckAccumTrig0_A	728249920	511	0	0
CheckAccumTrig1_A	728249920	21	0	0
CheckClr_A	728249920	235	0	0
CheckEn_A	728039355	312008601	0	0
CheckPhase0_A	728249920	589	0	0
CheckPhase1_A	728249920	576	0	0
CheckPhase2_A	728249920	560	0	0
CheckPhase3_A	728249920	544	0	0
CheckTimeout0_A	728249920	892	0	0
CheckTimeoutSt1_A	728249920	108838	0	0
CheckTimeoutSt2_A	728249920	805	0	0
CheckTimeoutStTrig_A	728249920	63	0	0
ErrorStAllEscAsserted_A	728249920	1206	0	0
ErrorStIsTerminal_A	728249920	996	0	0
EscStateOut_A	728037453	727967243	0	0
u_state_regs_A	728249920	728090017	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	248	0	0
T10	33164	95	0	0
T11	0	52	0	0
T12	0	30	0	0
T31	0	46	0	0
T32	0	25	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T36	234110	0	0	0
T37	34163	0	0	0
T38	456808	0	0	0
T39	152860	0	0	0
T40	81581	0	0	0
T41	57345	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	511	0	0
T3	443679	1	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	7	0	0
T7	278480	1	0	0
T8	798241	0	0	0
T15	0	2	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	1	0	0
T22	0	2	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	21	0	0
T16	826443	1	0	0
T23	0	1	0	0
T26	748904	0	0	0
T28	384244	0	0	0
T49	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T64	332812	0	0	0
T65	16055	0	0	0
T66	408114	0	0	0
T67	313787	0	0	0
T68	27348	0	0	0
T69	123595	0	0	0
T70	228603	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	235	0	0
T4	170040	1	0	0
T5	18613	0	0	0
T6	164781	5	0	0
T7	278480	0	0	0
T8	798241	0	0	0
T13	167133	0	0	0
T15	0	2	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	0	0	0
T20	344682	0	0	0
T23	0	4	0	0
T26	0	3	0	0
T67	0	1	0	0
T78	0	1	0	0
T79	0	6	0	0
T80	0	1	0	0
T81	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728039355	312008601	0	0
T1	28226	28157	0	0
T2	25404	25304	0	0
T3	443679	331561	0	0
T4	170040	169193	0	0
T5	18613	586	0	0
T6	164781	315700	0	0
T17	26336	26262	0	0
T18	62305	62230	0	0
T19	78021	3177	0	0
T20	344682	163329	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	589	0	0
T3	443679	1	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	7	0	0
T7	278480	1	0	0
T8	798241	0	0	0
T15	0	3	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	2	0	0
T22	0	2	0	0
T82	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	576	0	0
T3	443679	1	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	7	0	0
T7	278480	1	0	0
T8	798241	0	0	0
T15	0	3	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	2	0	0
T22	0	2	0	0
T82	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	560	0	0
T3	443679	1	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	6	0	0
T7	278480	1	0	0
T8	798241	0	0	0
T15	0	3	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	2	0	0
T22	0	2	0	0
T82	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	544	0	0
T3	443679	1	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	6	0	0
T7	278480	1	0	0
T8	798241	0	0	0
T15	0	3	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	2	0	0
T22	0	2	0	0
T82	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	892	0	0
T6	164781	23	0	0
T7	278480	0	0	0
T8	798241	0	0	0
T13	167133	0	0	0
T15	0	2	0	0
T16	0	70	0	0
T20	344682	1	0	0
T22	0	2	0	0
T28	0	1	0	0
T29	40078	0	0	0
T30	12306	0	0	0
T42	95897	0	0	0
T63	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T82	36787	2	0	0
T84	19954	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	108838	0	0
T6	164781	2093	0	0
T7	278480	0	0	0
T8	798241	0	0	0
T13	167133	0	0	0
T15	0	281	0	0
T16	0	5746	0	0
T20	344682	100	0	0
T22	0	279	0	0
T28	0	120	0	0
T29	40078	0	0	0
T30	12306	0	0	0
T42	95897	0	0	0
T63	0	47	0	0
T66	0	212	0	0
T68	0	145	0	0
T82	36787	296	0	0
T84	19954	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	805	0	0
T6	164781	23	0	0
T7	278480	0	0	0
T8	798241	0	0	0
T13	167133	0	0	0
T15	0	1	0	0
T16	0	69	0	0
T20	344682	0	0	0
T22	0	2	0	0
T28	0	1	0	0
T29	40078	0	0	0
T30	12306	0	0	0
T42	95897	0	0	0
T63	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T77	0	2	0	0
T82	36787	1	0	0
T84	19954	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	63	0	0
T7	278480	0	0	0
T8	798241	0	0	0
T13	167133	0	0	0
T14	369678	0	0	0
T15	0	1	0	0
T20	344682	1	0	0
T23	0	1	0	0
T29	40078	0	0	0
T30	12306	0	0	0
T42	95897	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T54	0	3	0	0
T80	0	1	0	0
T82	36787	1	0	0
T84	19954	0	0	0
T86	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	1206	0	0
T10	33164	362	0	0
T11	0	324	0	0
T12	0	171	0	0
T31	0	197	0	0
T32	0	152	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T36	234110	0	0	0
T37	34163	0	0	0
T38	456808	0	0	0
T39	152860	0	0	0
T40	81581	0	0	0
T41	57345	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	996	0	0
T10	33164	302	0	0
T11	0	264	0	0
T12	0	141	0	0
T31	0	167	0	0
T32	0	122	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T36	234110	0	0	0
T37	34163	0	0	0
T38	456808	0	0	0
T39	152860	0	0	0
T40	81581	0	0	0
T41	57345	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728037453	727967243	0	0
T1	28226	28158	0	0
T2	25404	25305	0	0
T3	443679	443627	0	0
T4	170040	170035	0	0
T5	18613	18533	0	0
T6	164781	164701	0	0
T17	26336	26263	0	0
T18	62305	62231	0	0
T19	78021	77937	0	0
T20	344682	344670	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	728090017	0	0
T1	28226	28158	0	0
T2	25404	25305	0	0
T3	443679	443627	0	0
T4	170040	170035	0	0
T5	18613	18533	0	0
T6	164781	164701	0	0
T17	26336	26263	0	0
T18	62305	62231	0	0
T19	78021	77937	0	0
T20	344682	344670	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T21
1	1	1	Covered	T1,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T17
1	0	1	Covered	T4,T20,T8
1	1	0	Covered	T1,T2,T19
1	1	1	Covered	T1,T2,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T19
0	1	Covered	T1,T19,T6
1	0	Covered	T47,T51,T58

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T47,T51,T58

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Not Covered
1	1	Covered	T1,T19,T6

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T19,T6,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T19
1	Covered	T1,T8,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T5,T6,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T4,T6,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T6,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T5,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T19,T6,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T5
Phase1St	198	Covered	T1,T4,T5
Phase2St	215	Covered	T1,T4,T5
Phase3St	233	Covered	T1,T4,T5
TerminalSt	249	Covered	T1,T4,T5
TimeoutSt	159	Covered	T1,T2,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T4,T5
IdleSt->TimeoutSt	159	Covered	T1,T2,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T108,T61,T109
Phase0St->Phase1St	198	Covered	T1,T4,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T110,T21,T111
Phase1St->Phase2St	215	Covered	T1,T4,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T20,T78,T112
Phase2St->Phase3St	233	Covered	T1,T4,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T6,T52,T21
Phase3St->TerminalSt	249	Covered	T1,T4,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T19,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T19,T6
TimeoutSt->Phase0St	172	Covered	T1,T19,T6

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T109,T113,T114
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T110,T21,T111
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T20,T78,T112
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T52,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T19,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	728249920	319	0	0
CheckAccumTrig0_A	728249920	505	0	0
CheckAccumTrig1_A	728249920	17	0	0
CheckClr_A	728249920	210	0	0
CheckEn_A	728039355	326803574	0	0
CheckPhase0_A	728249920	573	0	0
CheckPhase1_A	728249920	562	0	0
CheckPhase2_A	728249920	557	0	0
CheckPhase3_A	728249920	546	0	0
CheckTimeout0_A	728249920	1069	0	0
CheckTimeoutSt1_A	728249920	114138	0	0
CheckTimeoutSt2_A	728249920	992	0	0
CheckTimeoutStTrig_A	728249920	59	0	0
ErrorStAllEscAsserted_A	728249920	1299	0	0
ErrorStIsTerminal_A	728249920	1089	0	0
EscStateOut_A	728037453	727967243	0	0
u_state_regs_A	728249920	728090017	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	319	0	0
T10	33164	95	0	0
T11	0	101	0	0
T12	0	39	0	0
T31	0	43	0	0
T32	0	41	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T36	234110	0	0	0
T37	34163	0	0	0
T38	456808	0	0	0
T39	152860	0	0	0
T40	81581	0	0	0
T41	57345	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	505	0	0
T1	28226	1	0	0
T2	25404	0	0	0
T3	443679	0	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	3	0	0
T8	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	4	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	0	0	0
T20	344682	2	0	0
T22	0	4	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	17	0	0
T10	33164	0	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T47	14159	1	0	0
T51	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0
T71	244013	0	0	0
T72	539159	0	0	0
T73	433071	0	0	0
T74	125891	0	0	0
T75	32746	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	210	0	0
T1	28226	1	0	0
T2	25404	0	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	0	0	0
T6	164781	2	0	0
T16	0	2	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	1	0	0
T22	0	2	0	0
T67	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728039355	326803574	0	0
T1	28226	5591	0	0
T2	25404	14020	0	0
T3	443679	375468	0	0
T4	170040	13936	0	0
T5	18613	6100	0	0
T6	164781	231922	0	0
T17	26336	25236	0	0
T18	62305	62230	0	0
T19	78021	71529	0	0
T20	344682	256228	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	573	0	0
T1	28226	2	0	0
T2	25404	0	0	0
T3	443679	0	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	5	0	0
T8	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	2	0	0
T22	0	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	562	0	0
T1	28226	2	0	0
T2	25404	0	0	0
T3	443679	0	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	5	0	0
T8	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	2	0	0
T22	0	5	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	557	0	0
T1	28226	2	0	0
T2	25404	0	0	0
T3	443679	0	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	5	0	0
T8	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	1	0	0
T22	0	5	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	546	0	0
T1	28226	2	0	0
T2	25404	0	0	0
T3	443679	0	0	0
T4	170040	1	0	0
T5	18613	1	0	0
T6	164781	4	0	0
T8	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	1	0	0
T22	0	5	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	1069	0	0
T1	28226	1	0	0
T2	25404	2	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	0	0	0
T6	164781	8	0	0
T15	0	6	0	0
T16	0	6	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	2	0	0
T20	344682	0	0	0
T22	0	1	0	0
T65	0	1	0	0
T66	0	9	0	0
T82	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	114138	0	0
T1	28226	79	0	0
T2	25404	117	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	0	0	0
T6	164781	409	0	0
T15	0	885	0	0
T16	0	458	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	283	0	0
T20	344682	0	0	0
T22	0	81	0	0
T65	0	100	0	0
T66	0	1626	0	0
T82	0	413	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	992	0	0
T2	25404	2	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	0	0	0
T6	164781	6	0	0
T8	798241	0	0	0
T15	0	6	0	0
T16	0	6	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	0	0	0
T66	0	9	0	0
T77	0	78	0	0
T82	0	2	0	0
T85	0	2	0	0
T86	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	59	0	0
T1	28226	1	0	0
T2	25404	0	0	0
T3	443679	0	0	0
T4	170040	0	0	0
T5	18613	0	0	0
T6	164781	2	0	0
T17	26336	0	0	0
T18	62305	0	0	0
T19	78021	1	0	0
T20	344682	0	0	0
T22	0	1	0	0
T49	0	1	0	0
T65	0	1	0	0
T80	0	1	0	0
T88	0	1	0	0
T100	0	1	0	0
T121	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	1299	0	0
T10	33164	380	0	0
T11	0	373	0	0
T12	0	180	0	0
T31	0	171	0	0
T32	0	195	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T36	234110	0	0	0
T37	34163	0	0	0
T38	456808	0	0	0
T39	152860	0	0	0
T40	81581	0	0	0
T41	57345	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	1089	0	0
T10	33164	320	0	0
T11	0	313	0	0
T12	0	150	0	0
T31	0	141	0	0
T32	0	165	0	0
T33	339202	0	0	0
T34	105386	0	0	0
T35	123015	0	0	0
T36	234110	0	0	0
T37	34163	0	0	0
T38	456808	0	0	0
T39	152860	0	0	0
T40	81581	0	0	0
T41	57345	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728037453	727967243	0	0
T1	28226	28158	0	0
T2	25404	25305	0	0
T3	443679	443627	0	0
T4	170040	170035	0	0
T5	18613	18533	0	0
T6	164781	164701	0	0
T17	26336	26263	0	0
T18	62305	62231	0	0
T19	78021	77937	0	0
T20	344682	344670	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728249920	728090017	0	0
T1	28226	28158	0	0
T2	25404	25305	0	0
T3	443679	443627	0	0
T4	170040	170035	0	0
T5	18613	18533	0	0
T6	164781	164701	0	0
T17	26336	26263	0	0
T18	62305	62231	0	0
T19	78021	77937	0	0
T20	344682	344670	0	0