Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65890967	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32008023

1

T1

2920

T2

1834

T3

2718

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14650054	1			T1	1156		T2	736		T3	1086
values[0x0]	40496589	1			T1	3857		T2	2371		T3	3814
values[0x1]	42752347	1			T1	3903		T2	2361		T3	3882

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56152871	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41746119

1

T1

3728

T2

2272

T3

3435

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	300987	1			T1	26		T2	17		T5	914
valid_sources[0x01]	299864	1			T1	52		T2	14		T5	1008
valid_sources[0x02]	306392	1			T1	26		T2	20		T5	875
valid_sources[0x03]	299450	1			T1	42		T2	19		T5	962
valid_sources[0x04]	321991	1			T1	30		T2	20		T5	1028
valid_sources[0x05]	300834	1			T1	27		T2	15		T5	967
valid_sources[0x06]	297550	1			T1	32		T2	27		T5	942
valid_sources[0x07]	299325	1			T1	54		T2	19		T5	950
valid_sources[0x08]	299838	1			T1	26		T2	24		T5	985
valid_sources[0x09]	301468	1			T1	29		T2	23		T5	994
valid_sources[0x0a]	329274	1			T1	28		T2	18		T5	1051
valid_sources[0x0b]	296482	1			T1	39		T2	27		T5	914
valid_sources[0x0c]	296533	1			T1	23		T2	15		T5	961
valid_sources[0x0d]	294369	1			T1	27		T2	23		T5	967
valid_sources[0x0e]	731715	1			T1	27		T2	17		T5	949
valid_sources[0x0f]	297344	1			T1	37		T2	24		T5	968
valid_sources[0x10]	291286	1			T1	36		T2	17		T5	1020
valid_sources[0x11]	300853	1			T1	34		T2	17		T5	1023
valid_sources[0x12]	297013	1			T1	28		T2	28		T5	1002
valid_sources[0x13]	301744	1			T1	40		T2	22		T5	903
valid_sources[0x14]	307312	1			T1	29		T2	23		T5	976
valid_sources[0x15]	308659	1			T1	42		T2	13		T5	945
valid_sources[0x16]	298492	1			T1	39		T2	22		T5	930
valid_sources[0x17]	294070	1			T1	30		T2	29		T5	976
valid_sources[0x18]	296204	1			T1	35		T2	19		T5	1037
valid_sources[0x19]	316025	1			T1	36		T2	31		T5	954
valid_sources[0x1a]	302209	1			T1	30		T2	24		T5	1009
valid_sources[0x1b]	782933	1			T1	38		T2	25		T5	1001
valid_sources[0x1c]	596325	1			T1	36		T2	20		T5	967
valid_sources[0x1d]	299354	1			T1	37		T2	21		T5	978
valid_sources[0x1e]	293197	1			T1	27		T2	18		T5	949
valid_sources[0x1f]	298314	1			T1	32		T2	22		T5	1043
valid_sources[0x20]	302176	1			T1	41		T2	30		T5	1015
valid_sources[0x21]	297517	1			T1	26		T2	24		T5	937
valid_sources[0x22]	296766	1			T1	49		T2	24		T5	924
valid_sources[0x23]	660276	1			T1	23		T2	16		T5	1017
valid_sources[0x24]	347515	1			T1	38		T2	18		T5	935
valid_sources[0x25]	304638	1			T1	35		T2	19		T5	1039
valid_sources[0x26]	305630	1			T1	37		T2	30		T5	949
valid_sources[0x27]	289678	1			T1	33		T2	30		T5	1042
valid_sources[0x28]	303062	1			T1	32		T2	27		T5	1044
valid_sources[0x29]	312093	1			T1	30		T2	23		T5	1018
valid_sources[0x2a]	304374	1			T1	35		T2	30		T5	1000
valid_sources[0x2b]	297107	1			T1	38		T2	15		T5	1044
valid_sources[0x2c]	308738	1			T1	29		T2	17		T5	1080
valid_sources[0x2d]	293553	1			T1	26		T2	24		T5	953
valid_sources[0x2e]	296917	1			T1	38		T2	24		T5	962
valid_sources[0x2f]	303334	1			T1	38		T2	22		T5	1050
valid_sources[0x30]	298024	1			T1	32		T2	23		T5	999
valid_sources[0x31]	609790	1			T1	28		T2	24		T5	960
valid_sources[0x32]	293418	1			T1	43		T2	19		T5	1027
valid_sources[0x33]	710243	1			T1	41		T2	32		T5	910
valid_sources[0x34]	315027	1			T1	32		T2	17		T5	1014
valid_sources[0x35]	300270	1			T1	32		T2	23		T5	1005
valid_sources[0x36]	306002	1			T1	41		T2	22		T5	949
valid_sources[0x37]	730181	1			T1	32		T2	20		T5	996
valid_sources[0x38]	296155	1			T1	32		T2	19		T5	980
valid_sources[0x39]	302224	1			T1	28		T2	19		T5	1034
valid_sources[0x3a]	311617	1			T1	37		T2	20		T5	1063
valid_sources[0x3b]	307542	1			T1	29		T2	23		T5	972
valid_sources[0x3c]	297276	1			T1	36		T2	16		T5	1026
valid_sources[0x3d]	298384	1			T1	43		T2	22		T5	959
valid_sources[0x3e]	302817	1			T1	29		T2	12		T5	988
valid_sources[0x3f]	303096	1			T1	43		T2	14		T5	975
valid_sources[0x40]	1235401	1			T1	33		T2	19		T4	297912
valid_sources[0x41]	297076	1			T1	34		T2	13		T5	958
valid_sources[0x42]	300653	1			T1	28		T2	22		T5	1021
valid_sources[0x43]	307243	1			T1	37		T2	17		T5	1023
valid_sources[0x44]	295586	1			T1	41		T2	18		T5	1056
valid_sources[0x45]	296775	1			T1	35		T2	21		T5	1038
valid_sources[0x46]	297678	1			T1	46		T2	22		T5	959
valid_sources[0x47]	303050	1			T1	29		T2	23		T5	985
valid_sources[0x48]	1218293	1			T1	51		T2	24		T5	1008
valid_sources[0x49]	594368	1			T1	30		T2	27		T5	964
valid_sources[0x4a]	329274	1			T1	29		T2	20		T5	975
valid_sources[0x4b]	299249	1			T1	36		T2	27		T5	973
valid_sources[0x4c]	295438	1			T1	42		T2	27		T5	1048
valid_sources[0x4d]	305828	1			T1	23		T2	16		T5	1039
valid_sources[0x4e]	307496	1			T1	26		T2	22		T5	970
valid_sources[0x4f]	542740	1			T1	31		T2	28		T5	923
valid_sources[0x50]	313410	1			T1	32		T2	16		T5	1047
valid_sources[0x51]	653366	1			T1	35		T2	25		T5	984
valid_sources[0x52]	302263	1			T1	54		T2	17		T5	962
valid_sources[0x53]	296099	1			T1	30		T2	25		T5	962
valid_sources[0x54]	301697	1			T1	25		T2	23		T5	948
valid_sources[0x55]	657555	1			T1	39		T2	16		T5	1027
valid_sources[0x56]	298310	1			T1	51		T2	23		T5	1041
valid_sources[0x57]	302584	1			T1	44		T2	16		T5	1030
valid_sources[0x58]	650945	1			T1	48		T2	27		T5	920
valid_sources[0x59]	300433	1			T1	31		T2	25		T5	990
valid_sources[0x5a]	654642	1			T1	48		T2	20		T5	977
valid_sources[0x5b]	777231	1			T1	37		T2	21		T5	987
valid_sources[0x5c]	297675	1			T1	39		T2	17		T5	997
valid_sources[0x5d]	303321	1			T1	33		T2	17		T5	997
valid_sources[0x5e]	302460	1			T1	33		T2	30		T5	1013
valid_sources[0x5f]	307872	1			T1	33		T2	25		T5	1067
valid_sources[0x60]	300773	1			T1	36		T2	18		T5	967
valid_sources[0x61]	310527	1			T1	30		T2	16		T5	903
valid_sources[0x62]	752851	1			T1	37		T2	20		T5	976
valid_sources[0x63]	308083	1			T1	37		T2	25		T5	951
valid_sources[0x64]	536068	1			T1	28		T2	26		T5	961
valid_sources[0x65]	768633	1			T1	34		T2	18		T5	971
valid_sources[0x66]	335836	1			T1	26		T2	21		T5	991
valid_sources[0x67]	293921	1			T1	26		T2	19		T5	932
valid_sources[0x68]	299853	1			T1	38		T2	29		T5	1039
valid_sources[0x69]	297515	1			T1	29		T2	28		T5	963
valid_sources[0x6a]	299184	1			T1	28		T2	12		T5	992
valid_sources[0x6b]	297572	1			T1	38		T2	21		T5	997
valid_sources[0x6c]	619521	1			T1	32		T2	22		T3	8782
valid_sources[0x6d]	293325	1			T1	37		T2	15		T5	1054
valid_sources[0x6e]	305742	1			T1	31		T2	12		T5	1070
valid_sources[0x6f]	316061	1			T1	35		T2	26		T5	901
valid_sources[0x70]	323000	1			T1	22		T2	21		T5	990
valid_sources[0x71]	301492	1			T1	37		T2	21		T5	983
valid_sources[0x72]	309991	1			T1	40		T2	20		T5	987
valid_sources[0x73]	305044	1			T1	31		T2	14		T5	967
valid_sources[0x74]	295794	1			T1	33		T2	12		T5	1002
valid_sources[0x75]	303615	1			T1	51		T2	22		T5	1027
valid_sources[0x76]	295594	1			T1	38		T2	25		T5	1032
valid_sources[0x77]	301514	1			T1	40		T2	17		T5	1030
valid_sources[0x78]	293547	1			T1	27		T2	22		T5	994
valid_sources[0x79]	301479	1			T1	40		T2	18		T5	963
valid_sources[0x7a]	320106	1			T1	38		T2	22		T5	951
valid_sources[0x7b]	552908	1			T1	27		T2	26		T5	989
valid_sources[0x7c]	304615	1			T1	34		T2	20		T5	962
valid_sources[0x7d]	297429	1			T1	40		T2	19		T5	898
valid_sources[0x7e]	311005	1			T1	30		T2	23		T5	958
valid_sources[0x7f]	297847	1			T1	43		T2	24		T5	991
valid_sources[0x80]	300359	1			T1	28		T2	24		T5	1068

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7332269

1

T1

573

T2

389

T3

521

values[0x0]

all_enables

biggest_size

15554327

1

T1

1466

T2

918

T3

1420

values[0x1]

all_enables

biggest_size

9121427

1

T1

881

T2

527

T3

777