Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T195,T196
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13455	0	0
DisabledNoTrigBkwd_A	2147483647	837754	0	0
DisabledNoTrigFwd_A	2147483647	1554113472	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13455	0	0
T40	2845	510	0	0
T54	505753	0	0	0
T55	397449	0	0	0
T87	35975	0	0	0
T99	181902	0	0	0
T195	0	366	0	0
T196	3717	579	0	0
T197	1725	923	0	0
T198	1245	400	0	0
T199	0	485	0	0
T200	0	1536	0	0
T201	0	915	0	0
T202	0	340	0	0
T203	0	441	0	0
T204	0	381	0	0
T205	0	631	0	0
T206	0	1070	0	0
T207	0	470	0	0
T208	0	2058	0	0
T209	0	301	0	0
T210	0	181	0	0
T211	0	423	0	0
T212	0	894	0	0
T213	0	551	0	0
T214	148581	0	0	0
T215	75774	0	0	0
T216	72978	0	0	0
T217	15461	0	0	0
T218	166661	0	0	0
T219	101410	0	0	0
T220	804923	0	0	0
T221	920936	0	0	0
T222	10527	0	0	0
T223	188866	0	0	0
T224	5955	0	0	0
T225	111608	0	0	0
T226	38810	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	837754	0	0
T3	94871	1	0	0
T4	3306620	3162	0	0
T5	3654484	262	0	0
T6	1485424	7163	0	0
T7	121704	0	0	0
T8	0	2901	0	0
T9	0	14	0	0
T10	0	731	0	0
T14	123864	0	0	0
T17	0	1100	0	0
T18	0	12425	0	0
T19	0	2140	0	0
T20	107292	0	0	0
T21	210644	0	0	0
T22	329340	90	0	0
T23	385256	0	0	0
T24	101508	0	0	0
T29	0	989	0	0
T33	0	40	0	0
T37	0	15	0	0
T38	0	8	0	0
T39	0	34	0	0
T40	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1554113472	0	0
T1	126184	48956	0	0
T2	55448	38934	0	0
T3	379484	282792	0	0
T4	3306620	1649111	0	0
T5	3654484	920727	0	0
T6	1485424	378359	0	0
T14	123864	22128	0	0
T20	107292	30937	0	0
T21	210644	181758	0	0
T22	329340	174400	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T196,T198,T200
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T29

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	711093775	4067	0	0
DisabledNoTrigBkwd_A	711093775	225687	0	0
DisabledNoTrigFwd_A	711093775	375605876	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	4067	0	0
T54	505753	0	0	0
T196	3717	579	0	0
T198	0	400	0	0
T200	0	1536	0	0
T206	0	1070	0	0
T209	0	301	0	0
T210	0	181	0	0
T214	148581	0	0	0
T215	75774	0	0	0
T216	72978	0	0	0
T217	15461	0	0	0
T218	166661	0	0	0
T219	101410	0	0	0
T220	804923	0	0	0
T221	920936	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	225687	0	0
T3	94871	1	0	0
T4	826655	1	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T7	30426	0	0	0
T8	0	1215	0	0
T14	30966	0	0	0
T18	0	1940	0	0
T19	0	608	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T29	0	619	0	0
T33	0	14	0	0
T37	0	15	0	0
T38	0	8	0	0
T39	0	34	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	375605876	0	0
T1	31546	6540	0	0
T2	13862	2677	0	0
T3	94871	7100	0	0
T4	826655	819970	0	0
T5	913621	913543	0	0
T6	371356	370951	0	0
T14	30966	5532	0	0
T20	26823	1804	0	0
T21	52661	52590	0	0
T22	82335	77769	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T199,T201
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	711093775	5655	0	0
DisabledNoTrigBkwd_A	711093775	230138	0	0
DisabledNoTrigFwd_A	711093775	410649498	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	5655	0	0
T55	397449	0	0	0
T87	35975	0	0	0
T99	181902	0	0	0
T197	1725	923	0	0
T198	1245	0	0	0
T199	0	485	0	0
T201	0	915	0	0
T204	0	381	0	0
T207	0	470	0	0
T208	0	2058	0	0
T211	0	423	0	0
T222	10527	0	0	0
T223	188866	0	0	0
T224	5955	0	0	0
T225	111608	0	0	0
T226	38810	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	230138	0	0
T4	826655	1274	0	0
T5	913621	2	0	0
T6	371356	2614	0	0
T7	30426	0	0	0
T8	0	1685	0	0
T10	0	729	0	0
T14	30966	0	0	0
T17	0	1	0	0
T18	0	4942	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	42	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	0	149	0	0
T33	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	410649498	0	0
T1	31546	5584	0	0
T2	13862	10734	0	0
T3	94871	90452	0	0
T4	826655	1978	0	0
T5	913621	3293	0	0
T6	371356	2455	0	0
T14	30966	5532	0	0
T20	26823	586	0	0
T21	52661	29487	0	0
T22	82335	19375	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T195,T202
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	711093775	3102	0	0
DisabledNoTrigBkwd_A	711093775	222312	0	0
DisabledNoTrigFwd_A	711093775	351085568	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	3102	0	0
T11	118339	0	0	0
T12	821270	0	0	0
T31	28473	0	0	0
T40	2845	510	0	0
T62	17648	0	0	0
T63	11840	0	0	0
T195	0	366	0	0
T202	0	340	0	0
T203	0	441	0	0
T212	0	894	0	0
T213	0	551	0	0
T227	13974	0	0	0
T228	121425	0	0	0
T229	10550	0	0	0
T230	6555	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	222312	0	0
T4	826655	2	0	0
T5	913621	259	0	0
T6	371356	1747	0	0
T7	30426	0	0	0
T9	0	14	0	0
T14	30966	0	0	0
T18	0	2622	0	0
T19	0	1532	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	40	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	0	52	0	0
T33	0	17	0	0
T40	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	351085568	0	0
T1	31546	24371	0	0
T2	13862	12781	0	0
T3	94871	90457	0	0
T4	826655	825177	0	0
T5	913621	1940	0	0
T6	371356	2470	0	0
T14	30966	5532	0	0
T20	26823	1812	0	0
T21	52661	52590	0	0
T22	82335	7678	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T205
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	711093775	631	0	0
DisabledNoTrigBkwd_A	711093775	159617	0	0
DisabledNoTrigFwd_A	711093775	416772530	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	631	0	0
T16	41532	0	0	0
T205	1368	631	0	0
T231	537908	0	0	0
T232	146907	0	0	0
T233	858763	0	0	0
T234	149446	0	0	0
T235	167269	0	0	0
T236	12586	0	0	0
T237	80975	0	0	0
T238	54257	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	159617	0	0
T4	826655	1885	0	0
T5	913621	1	0	0
T6	371356	2802	0	0
T7	30426	0	0	0
T8	0	1	0	0
T10	0	2	0	0
T14	30966	0	0	0
T17	0	1099	0	0
T18	0	2921	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	8	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	0	169	0	0
T33	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	416772530	0	0
T1	31546	12461	0	0
T2	13862	12742	0	0
T3	94871	94783	0	0
T4	826655	1986	0	0
T5	913621	1951	0	0
T6	371356	2483	0	0
T14	30966	5532	0	0
T20	26823	26735	0	0
T21	52661	47091	0	0
T22	82335	69578	0	0