Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T25
1	1	1	Covered	T3,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T1,T2,T20
1	1	1	Covered	T1,T2,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T20
0	1	Covered	T21,T22,T23
1	0	Covered	T22,T18,T19

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T20
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T22,T18,T19

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Covered	T26,T27,T28
1	1	Covered	T21,T22,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T4,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T4,T6,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T5,T22,T29

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T5,T6,T21

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T4,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T4,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T4,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T3,T5,T6

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T14,T15,T16
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T4,T5
Phase1St	198	Covered	T3,T4,T5
Phase2St	215	Covered	T3,T4,T5
Phase3St	233	Covered	T3,T4,T5
TerminalSt	249	Covered	T3,T4,T5
TimeoutSt	159	Covered	T1,T2,T20

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T14,T15,T16
IdleSt->Phase0St	152	Covered	T3,T4,T5
IdleSt->TimeoutSt	159	Covered	T1,T2,T20
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T6,T19,T30
Phase0St->Phase1St	198	Covered	T3,T4,T5
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T6,T22,T31
Phase1St->Phase2St	215	Covered	T3,T4,T5
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T31,T26,T32
Phase2St->Phase3St	233	Covered	T3,T4,T5
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T4,T22,T33
Phase3St->TerminalSt	249	Covered	T3,T4,T5
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T4,T6,T22
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T2,T20
TimeoutSt->Phase0St	172	Covered	T21,T22,T23

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T30,T34
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T22,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T26,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T22,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T6,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1128	0	0
CheckAccumTrig0_A	2147483647	2428	0	0
CheckAccumTrig1_A	2147483647	117	0	0
CheckClr_A	2147483647	1169	0	0
CheckEn_A	2147483647	1211568579	0	0
CheckPhase0_A	2147483647	2779	0	0
CheckPhase1_A	2147483647	2724	0	0
CheckPhase2_A	2147483647	2672	0	0
CheckPhase3_A	2147483647	2604	0	0
CheckTimeout0_A	2147483647	5315	0	0
CheckTimeoutSt1_A	2147483647	524526	0	0
CheckTimeoutSt2_A	2147483647	4904	0	0
CheckTimeoutStTrig_A	2147483647	290	0	0
ErrorStAllEscAsserted_A	2147483647	5813	0	0
ErrorStIsTerminal_A	2147483647	4853	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1128	0	0
T7	121704	0	0	0
T8	1006264	0	0	0
T14	123864	266	0	0
T15	0	139	0	0
T16	0	272	0	0
T17	1116852	0	0	0
T21	210644	0	0	0
T22	329340	0	0	0
T23	385256	0	0	0
T24	135344	0	0	0
T29	3884584	0	0	0
T35	0	147	0	0
T36	0	304	0	0
T37	23956	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2428	0	0
T3	94871	1	0	0
T4	3306620	9	0	0
T5	3654484	3	0	0
T6	1485424	23	0	0
T7	121704	0	0	0
T8	0	4	0	0
T9	0	1	0	0
T10	0	3	0	0
T14	123864	0	0	0
T17	0	8	0	0
T18	0	20	0	0
T19	0	13	0	0
T20	107292	0	0	0
T21	210644	0	0	0
T22	329340	9	0	0
T23	385256	0	0	0
T24	101508	0	0	0
T29	0	19	0	0
T33	0	6	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T9	128090	0	0	0
T10	133478	0	0	0
T17	279213	0	0	0
T18	954236	1	0	0
T19	476699	2	0	0
T22	82335	1	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T26	0	1	0	0
T29	971146	0	0	0
T30	165989	3	0	0
T33	20695	0	0	0
T37	5989	0	0	0
T38	7316	0	0	0
T39	272719	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	80691	0	0	0
T58	20614	0	0	0
T59	4631	0	0	0
T60	26220	0	0	0
T61	29415	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1169	0	0
T4	2479965	6	0	0
T5	2740863	0	0	0
T6	1114068	20	0	0
T7	91278	0	0	0
T8	251566	1	0	0
T9	128090	0	0	0
T10	133478	2	0	0
T14	92898	0	0	0
T18	477118	8	0	0
T19	0	12	0	0
T20	80469	0	0	0
T21	157983	0	0	0
T22	247005	8	0	0
T23	288942	6	0	0
T24	101508	2	0	0
T26	0	16	0	0
T29	971146	7	0	0
T31	0	2	0	0
T33	20695	2	0	0
T37	5989	0	0	0
T38	7316	0	0	0
T39	0	1	0	0
T41	0	2	0	0
T57	80691	0	0	0
T58	20614	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1211568579	0	0
T1	126184	48955	0	0
T2	55448	38931	0	0
T3	379484	278457	0	0
T4	3306620	830425	0	0
T5	3654484	920726	0	0
T6	1485424	378359	0	0
T14	688	428	0	0
T20	107292	30936	0	0
T21	210644	155318	0	0
T22	329340	104274	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2779	0	0
T3	94871	1	0	0
T4	3306620	9	0	0
T5	3654484	3	0	0
T6	1485424	22	0	0
T7	121704	0	0	0
T8	0	4	0	0
T9	0	1	0	0
T14	123864	0	0	0
T17	0	8	0	0
T18	0	27	0	0
T19	0	13	0	0
T20	107292	0	0	0
T21	210644	1	0	0
T22	329340	11	0	0
T23	385256	7	0	0
T24	101508	3	0	0
T29	0	20	0	0
T33	0	4	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2724	0	0
T3	94871	1	0	0
T4	3306620	9	0	0
T5	3654484	3	0	0
T6	1485424	20	0	0
T7	121704	0	0	0
T8	0	4	0	0
T9	0	1	0	0
T14	123864	0	0	0
T17	0	8	0	0
T18	0	27	0	0
T19	0	13	0	0
T20	107292	0	0	0
T21	210644	1	0	0
T22	329340	10	0	0
T23	385256	7	0	0
T24	101508	3	0	0
T29	0	19	0	0
T33	0	4	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2672	0	0
T3	94871	1	0	0
T4	3306620	9	0	0
T5	3654484	3	0	0
T6	1485424	20	0	0
T7	121704	0	0	0
T8	0	4	0	0
T9	0	1	0	0
T14	123864	0	0	0
T17	0	7	0	0
T18	0	27	0	0
T19	0	13	0	0
T20	107292	0	0	0
T21	210644	1	0	0
T22	329340	10	0	0
T23	385256	7	0	0
T24	101508	3	0	0
T29	0	19	0	0
T33	0	4	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2604	0	0
T3	94871	1	0	0
T4	3306620	8	0	0
T5	3654484	3	0	0
T6	1485424	18	0	0
T7	121704	0	0	0
T8	0	4	0	0
T9	0	1	0	0
T14	123864	0	0	0
T17	0	5	0	0
T18	0	27	0	0
T19	0	13	0	0
T20	107292	0	0	0
T21	210644	1	0	0
T22	329340	7	0	0
T23	385256	6	0	0
T24	101508	3	0	0
T29	0	19	0	0
T33	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5315	0	0
T1	126184	24	0	0
T2	55448	7	0	0
T3	379484	0	0	0
T4	3306620	0	0	0
T5	3654484	0	0	0
T6	1485424	1	0	0
T14	123864	0	0	0
T17	0	1	0	0
T18	0	28	0	0
T19	0	3	0	0
T20	107292	24	0	0
T21	210644	2	0	0
T22	329340	4	0	0
T23	0	7	0	0
T24	0	20	0	0
T29	0	13	0	0
T33	0	1	0	0
T38	0	1	0	0
T39	0	3	0	0
T57	0	10	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	524526	0	0
T1	126184	1676	0	0
T2	55448	361	0	0
T3	379484	0	0	0
T4	3306620	0	0	0
T5	3654484	0	0	0
T6	1485424	148	0	0
T14	123864	0	0	0
T17	0	195	0	0
T18	0	4151	0	0
T19	0	252	0	0
T20	107292	1485	0	0
T21	210644	214	0	0
T22	329340	269	0	0
T23	0	400	0	0
T24	0	4264	0	0
T29	0	1332	0	0
T33	0	140	0	0
T38	0	359	0	0
T39	0	333	0	0
T57	0	1684	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4904	0	0
T1	126184	24	0	0
T2	55448	7	0	0
T3	379484	0	0	0
T4	3306620	0	0	0
T5	3654484	0	0	0
T6	1485424	1	0	0
T14	123864	0	0	0
T17	0	1	0	0
T18	0	30	0	0
T19	0	2	0	0
T20	107292	24	0	0
T21	210644	1	0	0
T22	329340	2	0	0
T24	0	17	0	0
T29	0	12	0	0
T33	0	1	0	0
T39	0	139	0	0
T57	0	10	0	0
T60	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	290	0	0
T7	91278	0	0	0
T8	754698	0	0	0
T9	256180	0	0	0
T10	133478	0	0	0
T17	837639	0	0	0
T18	1431354	5	0	0
T19	476699	0	0	0
T21	52661	1	0	0
T22	164670	1	0	0
T23	288942	2	0	0
T24	101508	0	0	0
T26	0	2	0	0
T27	0	2	0	0
T29	2913438	1	0	0
T30	0	1	0	0
T32	0	5	0	0
T33	20695	0	0	0
T37	17967	0	0	0
T38	7316	0	0	0
T39	272719	2	0	0
T42	0	2	0	0
T46	0	1	0	0
T57	242073	0	0	0
T58	20614	0	0	0
T59	4631	0	0	0
T60	26220	0	0	0
T61	0	1	0	0
T68	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5813	0	0
T7	121704	0	0	0
T8	1006264	0	0	0
T14	123864	1480	0	0
T15	0	661	0	0
T16	0	1469	0	0
T17	1116852	0	0	0
T21	210644	0	0	0
T22	329340	0	0	0
T23	385256	0	0	0
T24	135344	0	0	0
T29	3884584	0	0	0
T35	0	740	0	0
T36	0	1463	0	0
T37	23956	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4853	0	0
T7	121704	0	0	0
T8	1006264	0	0	0
T14	123864	1240	0	0
T15	0	541	0	0
T16	0	1229	0	0
T17	1116852	0	0	0
T21	210644	0	0	0
T22	329340	0	0	0
T23	385256	0	0	0
T24	135344	0	0	0
T29	3884584	0	0	0
T35	0	620	0	0
T36	0	1223	0	0
T37	23956	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	126184	125928	0	0
T2	55448	55236	0	0
T3	379484	379132	0	0
T4	3306620	3306276	0	0
T5	3654484	3654172	0	0
T6	1485424	1485392	0	0
T14	256	0	0	0
T20	107292	106940	0	0
T21	210644	210360	0	0
T22	329340	329136	0	0
T23	0	384884	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	126184	125928	0	0
T2	55448	55236	0	0
T3	379484	379132	0	0
T4	3306620	3306276	0	0
T5	3654484	3654172	0	0
T6	1485424	1485392	0	0
T14	123864	22128	0	0
T20	107292	106940	0	0
T21	210644	210360	0	0
T22	329340	329136	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T29

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T8,T18
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T1,T2,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T20
0	1	Covered	T22,T18,T68
1	0	Covered	T18,T19,T41

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T19,T41

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Not Covered
1	1	Covered	T22,T18,T68

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T29,T8
1	Covered	T3,T22,T29

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T22,T29
1	Covered	T4,T29,T18

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T22
1	Covered	T8,T18,T38

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T22
1	Covered	T29,T18,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T4,T29,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T22,T29,T37

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T29,T8,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T3,T22,T29

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T14,T15,T16
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T4,T22
Phase1St	198	Covered	T3,T4,T22
Phase2St	215	Covered	T3,T4,T22
Phase3St	233	Covered	T3,T4,T22
TerminalSt	249	Covered	T3,T4,T22
TimeoutSt	159	Covered	T1,T2,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T14,T15,T16
IdleSt->Phase0St	152	Covered	T3,T4,T29
IdleSt->TimeoutSt	159	Covered	T1,T2,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T19,T30,T34
Phase0St->Phase1St	198	Covered	T3,T4,T22
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T65,T26,T70
Phase1St->Phase2St	215	Covered	T3,T4,T22
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T26,T76
Phase2St->Phase3St	233	Covered	T3,T4,T22
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T77,T76,T78
Phase3St->TerminalSt	249	Covered	T3,T4,T22
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T29,T18,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T20
TimeoutSt->Phase0St	172	Covered	T22,T18,T19

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T29
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T18,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T34,T79
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T22
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T22
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T65,T26,T80
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T22
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T26,T76
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T77,T76,T78
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T29,T18,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	711093775	248	0	0
CheckAccumTrig0_A	711093775	891	0	0
CheckAccumTrig1_A	711093775	46	0	0
CheckClr_A	711093775	439	0	0
CheckEn_A	710915653	283987348	0	0
CheckPhase0_A	711093775	968	0	0
CheckPhase1_A	711093775	947	0	0
CheckPhase2_A	711093775	928	0	0
CheckPhase3_A	711093775	904	0	0
CheckTimeout0_A	711093775	1740	0	0
CheckTimeoutSt1_A	711093775	153944	0	0
CheckTimeoutSt2_A	711093775	1630	0	0
CheckTimeoutStTrig_A	711093775	62	0	0
ErrorStAllEscAsserted_A	711093775	1431	0	0
ErrorStIsTerminal_A	711093775	1191	0	0
EscStateOut_A	710914142	710842289	0	0
u_state_regs_A	711093775	710920382	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	248	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T14	30966	56	0	0
T15	0	32	0	0
T16	0	56	0	0
T17	279213	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	971146	0	0	0
T35	0	41	0	0
T36	0	63	0	0
T37	5989	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	891	0	0
T3	94871	1	0	0
T4	826655	1	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T7	30426	0	0	0
T8	0	1	0	0
T14	30966	0	0	0
T18	0	7	0	0
T19	0	10	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T29	0	3	0	0
T33	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	46	0	0
T9	128090	0	0	0
T10	133478	0	0	0
T18	477118	1	0	0
T19	476699	1	0	0
T33	20695	0	0	0
T38	7316	0	0	0
T39	272719	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T58	20614	0	0	0
T59	4631	0	0	0
T60	26220	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	439	0	0
T8	251566	0	0	0
T9	128090	0	0	0
T10	133478	0	0	0
T18	477118	5	0	0
T19	0	7	0	0
T26	0	10	0	0
T29	971146	1	0	0
T31	0	1	0	0
T33	20695	0	0	0
T37	5989	0	0	0
T38	7316	0	0	0
T41	0	1	0	0
T57	80691	0	0	0
T58	20614	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710915653	283987348	0	0
T1	31546	6540	0	0
T2	13862	2677	0	0
T3	94871	2768	0	0
T4	826655	2239	0	0
T5	913621	913542	0	0
T6	371356	370951	0	0
T14	172	107	0	0
T20	26823	1804	0	0
T21	52661	52589	0	0
T22	82335	7644	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	968	0	0
T3	94871	1	0	0
T4	826655	1	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T7	30426	0	0	0
T8	0	1	0	0
T14	30966	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	1	0	0
T23	96314	0	0	0
T29	0	3	0	0
T33	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	947	0	0
T3	94871	1	0	0
T4	826655	1	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T7	30426	0	0	0
T8	0	1	0	0
T14	30966	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	1	0	0
T23	96314	0	0	0
T29	0	3	0	0
T33	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	928	0	0
T3	94871	1	0	0
T4	826655	1	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T7	30426	0	0	0
T8	0	1	0	0
T14	30966	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	1	0	0
T23	96314	0	0	0
T29	0	3	0	0
T33	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	904	0	0
T3	94871	1	0	0
T4	826655	1	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T7	30426	0	0	0
T8	0	1	0	0
T14	30966	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	1	0	0
T23	96314	0	0	0
T29	0	3	0	0
T33	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1740	0	0
T1	31546	8	0	0
T2	13862	3	0	0
T3	94871	0	0	0
T4	826655	0	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T14	30966	0	0	0
T18	0	11	0	0
T19	0	1	0	0
T20	26823	7	0	0
T21	52661	0	0	0
T22	82335	1	0	0
T24	0	3	0	0
T29	0	3	0	0
T39	0	2	0	0
T57	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	153944	0	0
T1	31546	559	0	0
T2	13862	136	0	0
T3	94871	0	0	0
T4	826655	0	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T14	30966	0	0	0
T18	0	2031	0	0
T19	0	5	0	0
T20	26823	444	0	0
T21	52661	0	0	0
T22	82335	93	0	0
T24	0	643	0	0
T29	0	397	0	0
T39	0	239	0	0
T57	0	152	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1630	0	0
T1	31546	8	0	0
T2	13862	3	0	0
T3	94871	0	0	0
T4	826655	0	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T14	30966	0	0	0
T18	0	8	0	0
T20	26823	7	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T24	0	3	0	0
T29	0	3	0	0
T39	0	2	0	0
T57	0	1	0	0
T60	0	1	0	0
T65	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	62	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T17	279213	0	0	0
T18	477118	2	0	0
T22	82335	1	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T27	0	1	0	0
T29	971146	0	0	0
T30	0	1	0	0
T37	5989	0	0	0
T42	0	2	0	0
T57	80691	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1431	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T14	30966	386	0	0
T15	0	163	0	0
T16	0	353	0	0
T17	279213	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	971146	0	0	0
T35	0	188	0	0
T36	0	341	0	0
T37	5989	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1191	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T14	30966	326	0	0
T15	0	133	0	0
T16	0	293	0	0
T17	279213	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	971146	0	0	0
T35	0	158	0	0
T36	0	281	0	0
T37	5989	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710914142	710842289	0	0
T1	31546	31482	0	0
T2	13862	13809	0	0
T3	94871	94783	0	0
T4	826655	826569	0	0
T5	913621	913543	0	0
T6	371356	371348	0	0
T14	64	0	0	0
T20	26823	26735	0	0
T21	52661	52590	0	0
T22	82335	82284	0	0
T23	0	96221	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	710920382	0	0
T1	31546	31482	0	0
T2	13862	13809	0	0
T3	94871	94783	0	0
T4	826655	826569	0	0
T5	913621	913543	0	0
T6	371356	371348	0	0
T14	30966	5532	0	0
T20	26823	26735	0	0
T21	52661	52590	0	0
T22	82335	82284	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T8
1	1	0	Covered	T1,T2,T20
1	1	1	Covered	T1,T2,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T20
0	1	Covered	T18,T26,T61
1	0	Covered	T18,T30,T44

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T30,T44

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Covered	T27
1	1	Covered	T18,T26,T61

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T18,T9,T33

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T22,T29
1	Covered	T4,T6,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T18,T26,T81

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T22
1	Covered	T5,T22,T29

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T6,T22,T29

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T4,T6,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T5,T6,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T5,T22,T29

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T14,T15,T16
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T5,T6
Phase1St	198	Covered	T4,T5,T6
Phase2St	215	Covered	T4,T5,T6
Phase3St	233	Covered	T4,T5,T6
TerminalSt	249	Covered	T4,T5,T6
TimeoutSt	159	Covered	T1,T2,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T14,T15,T16
IdleSt->Phase0St	152	Covered	T4,T5,T6
IdleSt->TimeoutSt	159	Covered	T1,T2,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T82,T80,T83
Phase0St->Phase1St	198	Covered	T4,T5,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T22,T31,T71
Phase1St->Phase2St	215	Covered	T4,T5,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T84,T85
Phase2St->Phase3St	233	Covered	T4,T5,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T33,T81,T86
Phase3St->TerminalSt	249	Covered	T4,T5,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T6,T22
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T20
TimeoutSt->Phase0St	172	Covered	T18,T26,T30

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T26,T30
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T82,T80,T83
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T22,T31,T71
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T84,T85
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T81,T86
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T6,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	711093775	240	0	0
CheckAccumTrig0_A	711093775	526	0	0
CheckAccumTrig1_A	711093775	28	0	0
CheckClr_A	711093775	261	0	0
CheckEn_A	710915653	264171781	0	0
CheckPhase0_A	711093775	624	0	0
CheckPhase1_A	711093775	609	0	0
CheckPhase2_A	711093775	594	0	0
CheckPhase3_A	711093775	578	0	0
CheckTimeout0_A	711093775	1571	0	0
CheckTimeoutSt1_A	711093775	163377	0	0
CheckTimeoutSt2_A	711093775	1465	0	0
CheckTimeoutStTrig_A	711093775	77	0	0
ErrorStAllEscAsserted_A	711093775	1410	0	0
ErrorStIsTerminal_A	711093775	1170	0	0
EscStateOut_A	710914142	710842289	0	0
u_state_regs_A	711093775	710920382	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	240	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T14	30966	60	0	0
T15	0	32	0	0
T16	0	62	0	0
T17	279213	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	971146	0	0	0
T35	0	27	0	0
T36	0	59	0	0
T37	5989	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	526	0	0
T4	826655	1	0	0
T5	913621	1	0	0
T6	371356	4	0	0
T7	30426	0	0	0
T9	0	1	0	0
T14	30966	0	0	0
T18	0	3	0	0
T19	0	3	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	5	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	0	5	0	0
T33	0	3	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	28	0	0
T30	165989	2	0	0
T32	373394	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T54	0	1	0	0
T61	29415	0	0	0
T69	114717	0	0	0
T70	654444	0	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	248123	0	0	0
T91	59327	0	0	0
T92	102810	0	0	0
T93	923626	0	0	0
T94	21114	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	261	0	0
T4	826655	1	0	0
T5	913621	0	0	0
T6	371356	3	0	0
T7	30426	0	0	0
T14	30966	0	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	4	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T26	0	6	0	0
T29	0	2	0	0
T31	0	1	0	0
T33	0	2	0	0
T41	0	1	0	0
T63	0	1	0	0
T66	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710915653	264171781	0	0
T1	31546	24370	0	0
T2	13862	12780	0	0
T3	94871	90456	0	0
T4	826655	824222	0	0
T5	913621	1940	0	0
T6	371356	2470	0	0
T14	172	107	0	0
T20	26823	1812	0	0
T21	52661	52589	0	0
T22	82335	7678	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	624	0	0
T4	826655	1	0	0
T5	913621	1	0	0
T6	371356	4	0	0
T7	30426	0	0	0
T9	0	1	0	0
T14	30966	0	0	0
T18	0	4	0	0
T19	0	3	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	5	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	0	5	0	0
T33	0	3	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	609	0	0
T4	826655	1	0	0
T5	913621	1	0	0
T6	371356	4	0	0
T7	30426	0	0	0
T9	0	1	0	0
T14	30966	0	0	0
T18	0	4	0	0
T19	0	3	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	4	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	0	5	0	0
T33	0	3	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	594	0	0
T4	826655	1	0	0
T5	913621	1	0	0
T6	371356	4	0	0
T7	30426	0	0	0
T9	0	1	0	0
T14	30966	0	0	0
T18	0	4	0	0
T19	0	3	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	4	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	0	5	0	0
T33	0	3	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	578	0	0
T4	826655	1	0	0
T5	913621	1	0	0
T6	371356	4	0	0
T7	30426	0	0	0
T9	0	1	0	0
T14	30966	0	0	0
T18	0	4	0	0
T19	0	3	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	4	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	0	5	0	0
T33	0	2	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1571	0	0
T1	31546	2	0	0
T2	13862	1	0	0
T3	94871	0	0	0
T4	826655	0	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T14	30966	0	0	0
T18	0	10	0	0
T19	0	2	0	0
T20	26823	7	0	0
T21	52661	0	0	0
T22	82335	1	0	0
T24	0	8	0	0
T29	0	5	0	0
T39	0	1	0	0
T57	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	163377	0	0
T1	31546	138	0	0
T2	13862	51	0	0
T3	94871	0	0	0
T4	826655	0	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T14	30966	0	0	0
T18	0	1447	0	0
T19	0	247	0	0
T20	26823	386	0	0
T21	52661	0	0	0
T22	82335	45	0	0
T24	0	1989	0	0
T29	0	632	0	0
T39	0	94	0	0
T57	0	509	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1465	0	0
T1	31546	2	0	0
T2	13862	1	0	0
T3	94871	0	0	0
T4	826655	0	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T14	30966	0	0	0
T18	0	9	0	0
T19	0	1	0	0
T20	26823	7	0	0
T21	52661	0	0	0
T22	82335	1	0	0
T24	0	8	0	0
T29	0	5	0	0
T39	0	1	0	0
T57	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	77	0	0
T9	128090	0	0	0
T10	133478	0	0	0
T18	477118	1	0	0
T19	476699	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T32	0	4	0	0
T33	20695	0	0	0
T38	7316	0	0	0
T39	272719	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T58	20614	0	0	0
T59	4631	0	0	0
T60	26220	0	0	0
T61	0	1	0	0
T71	0	1	0	0
T74	0	1	0	0
T80	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1410	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T14	30966	386	0	0
T15	0	158	0	0
T16	0	357	0	0
T17	279213	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	971146	0	0	0
T35	0	165	0	0
T36	0	344	0	0
T37	5989	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1170	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T14	30966	326	0	0
T15	0	128	0	0
T16	0	297	0	0
T17	279213	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	971146	0	0	0
T35	0	135	0	0
T36	0	284	0	0
T37	5989	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710914142	710842289	0	0
T1	31546	31482	0	0
T2	13862	13809	0	0
T3	94871	94783	0	0
T4	826655	826569	0	0
T5	913621	913543	0	0
T6	371356	371348	0	0
T14	64	0	0	0
T20	26823	26735	0	0
T21	52661	52590	0	0
T22	82335	82284	0	0
T23	0	96221	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	710920382	0	0
T1	31546	31482	0	0
T2	13862	13809	0	0
T3	94871	94783	0	0
T4	826655	826569	0	0
T5	913621	913543	0	0
T6	371356	371348	0	0
T14	30966	5532	0	0
T20	26823	26735	0	0
T21	52661	52590	0	0
T22	82335	82284	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Covered	T4,T5,T29
1	1	0	Covered	T1,T2,T20
1	1	1	Covered	T1,T2,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T23,T24,T18
1	0	Covered	T32,T73,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T32,T73,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T26
1	1	Covered	T23,T24,T18

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T23,T29

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T22
1	Covered	T6,T24,T29

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T6,T22
1	Covered	T4,T17,T29

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T22
1	Covered	T5,T22,T24

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T5,T6,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T5,T6,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T6,T22,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T14,T15,T16
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T5,T6
Phase1St	198	Covered	T4,T5,T6
Phase2St	215	Covered	T4,T5,T6
Phase3St	233	Covered	T4,T5,T6
TerminalSt	249	Covered	T4,T5,T6
TimeoutSt	159	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T14,T15,T16
IdleSt->Phase0St	152	Covered	T4,T5,T6
IdleSt->TimeoutSt	159	Covered	T1,T2,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T30,T95
Phase0St->Phase1St	198	Covered	T4,T5,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T29,T96
Phase1St->Phase2St	215	Covered	T4,T5,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T17,T30,T97
Phase2St->Phase3St	233	Covered	T4,T5,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T6,T22,T23
Phase3St->TerminalSt	249	Covered	T4,T5,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T6,T22
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T6
TimeoutSt->Phase0St	172	Covered	T23,T24,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T95,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T29,T96
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T17,T30,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T22,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T6,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	711093775	364	0	0
CheckAccumTrig0_A	711093775	510	0	0
CheckAccumTrig1_A	711093775	23	0	0
CheckClr_A	711093775	256	0	0
CheckEn_A	710915653	320627481	0	0
CheckPhase0_A	711093775	612	0	0
CheckPhase1_A	711093775	603	0	0
CheckPhase2_A	711093775	592	0	0
CheckPhase3_A	711093775	574	0	0
CheckTimeout0_A	711093775	1149	0	0
CheckTimeoutSt1_A	711093775	107749	0	0
CheckTimeoutSt2_A	711093775	1036	0	0
CheckTimeoutStTrig_A	711093775	89	0	0
ErrorStAllEscAsserted_A	711093775	1512	0	0
ErrorStIsTerminal_A	711093775	1272	0	0
EscStateOut_A	710914142	710842289	0	0
u_state_regs_A	711093775	710920382	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	364	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T14	30966	93	0	0
T15	0	35	0	0
T16	0	85	0	0
T17	279213	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	971146	0	0	0
T35	0	37	0	0
T36	0	114	0	0
T37	5989	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	510	0	0
T4	826655	3	0	0
T5	913621	1	0	0
T6	371356	11	0	0
T7	30426	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T14	30966	0	0	0
T17	0	7	0	0
T18	0	6	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	3	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	0	7	0	0
T33	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	23	0	0
T32	373394	1	0	0
T34	81796	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T71	28320	0	0	0
T73	0	1	0	0
T77	165454	0	0	0
T89	0	1	0	0
T93	923626	0	0	0
T94	21114	0	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	217951	0	0	0
T105	29396	0	0	0
T106	381605	0	0	0
T107	579674	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	256	0	0
T4	826655	2	0	0
T5	913621	0	0	0
T6	371356	10	0	0
T7	30426	0	0	0
T10	0	1	0	0
T14	30966	0	0	0
T17	0	6	0	0
T18	0	3	0	0
T19	0	4	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	3	0	0
T23	96314	5	0	0
T24	33836	2	0	0
T29	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710915653	320627481	0	0
T1	31546	12461	0	0
T2	13862	12741	0	0
T3	94871	94782	0	0
T4	826655	1986	0	0
T5	913621	1951	0	0
T6	371356	2483	0	0
T14	172	107	0	0
T20	26823	26734	0	0
T21	52661	47090	0	0
T22	82335	69577	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	612	0	0
T4	826655	3	0	0
T5	913621	1	0	0
T6	371356	10	0	0
T7	30426	0	0	0
T8	0	1	0	0
T14	30966	0	0	0
T17	0	7	0	0
T18	0	7	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	3	0	0
T23	96314	5	0	0
T24	33836	3	0	0
T29	0	7	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	603	0	0
T4	826655	3	0	0
T5	913621	1	0	0
T6	371356	9	0	0
T7	30426	0	0	0
T8	0	1	0	0
T14	30966	0	0	0
T17	0	7	0	0
T18	0	7	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	3	0	0
T23	96314	5	0	0
T24	33836	3	0	0
T29	0	6	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	592	0	0
T4	826655	3	0	0
T5	913621	1	0	0
T6	371356	9	0	0
T7	30426	0	0	0
T8	0	1	0	0
T14	30966	0	0	0
T17	0	6	0	0
T18	0	7	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	3	0	0
T23	96314	5	0	0
T24	33836	3	0	0
T29	0	6	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	574	0	0
T4	826655	3	0	0
T5	913621	1	0	0
T6	371356	7	0	0
T7	30426	0	0	0
T8	0	1	0	0
T14	30966	0	0	0
T17	0	4	0	0
T18	0	7	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	1	0	0
T23	96314	4	0	0
T24	33836	3	0	0
T29	0	6	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1149	0	0
T1	31546	7	0	0
T2	13862	1	0	0
T3	94871	0	0	0
T4	826655	0	0	0
T5	913621	0	0	0
T6	371356	1	0	0
T14	30966	0	0	0
T18	0	7	0	0
T20	26823	0	0	0
T21	52661	1	0	0
T22	82335	0	0	0
T23	0	5	0	0
T24	0	3	0	0
T29	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	107749	0	0
T1	31546	474	0	0
T2	13862	62	0	0
T3	94871	0	0	0
T4	826655	0	0	0
T5	913621	0	0	0
T6	371356	148	0	0
T14	30966	0	0	0
T18	0	673	0	0
T20	26823	0	0	0
T21	52661	148	0	0
T22	82335	0	0	0
T23	0	350	0	0
T24	0	395	0	0
T29	0	63	0	0
T33	0	140	0	0
T38	0	359	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1036	0	0
T1	31546	7	0	0
T2	13862	1	0	0
T3	94871	0	0	0
T4	826655	0	0	0
T5	913621	0	0	0
T6	371356	1	0	0
T14	30966	0	0	0
T18	0	6	0	0
T19	0	1	0	0
T20	26823	0	0	0
T21	52661	1	0	0
T22	82335	0	0	0
T29	0	2	0	0
T33	0	1	0	0
T39	0	129	0	0
T64	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	89	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T9	128090	0	0	0
T17	279213	0	0	0
T18	477118	1	0	0
T19	0	1	0	0
T23	96314	5	0	0
T24	33836	3	0	0
T29	971146	0	0	0
T32	0	1	0	0
T37	5989	0	0	0
T38	0	1	0	0
T42	0	1	0	0
T57	80691	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T108	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1512	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T14	30966	349	0	0
T15	0	176	0	0
T16	0	377	0	0
T17	279213	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	971146	0	0	0
T35	0	200	0	0
T36	0	410	0	0
T37	5989	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1272	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T14	30966	289	0	0
T15	0	146	0	0
T16	0	317	0	0
T17	279213	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	971146	0	0	0
T35	0	170	0	0
T36	0	350	0	0
T37	5989	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710914142	710842289	0	0
T1	31546	31482	0	0
T2	13862	13809	0	0
T3	94871	94783	0	0
T4	826655	826569	0	0
T5	913621	913543	0	0
T6	371356	371348	0	0
T14	64	0	0	0
T20	26823	26735	0	0
T21	52661	52590	0	0
T22	82335	82284	0	0
T23	0	96221	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	710920382	0	0
T1	31546	31482	0	0
T2	13862	13809	0	0
T3	94871	94783	0	0
T4	826655	826569	0	0
T5	913621	913543	0	0
T6	371356	371348	0	0
T14	30966	5532	0	0
T20	26823	26735	0	0
T21	52661	52590	0	0
T22	82335	82284	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T25
1	1	1	Covered	T4,T5,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T18,T10
1	1	0	Covered	T2,T23,T24
1	1	1	Covered	T1,T2,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T20
0	1	Covered	T21,T23,T29
1	0	Covered	T22,T19,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T19,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Covered	T28
1	1	Covered	T21,T23,T29

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T4,T23,T29

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T18,T38

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T21
1	Covered	T5,T22,T29

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T22
1	Covered	T6,T21,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T22,T23,T29

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T4,T5,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T4,T6,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T6,T21,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T14,T15,T16
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T5,T6
Phase1St	198	Covered	T4,T5,T6
Phase2St	215	Covered	T4,T5,T6
Phase3St	233	Covered	T4,T5,T6
TerminalSt	249	Covered	T4,T5,T6
TimeoutSt	159	Covered	T1,T2,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T14,T15,T16
IdleSt->Phase0St	152	Covered	T4,T5,T6
IdleSt->TimeoutSt	159	Covered	T1,T2,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T19,T70,T47
Phase0St->Phase1St	198	Covered	T4,T5,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T62,T97
Phase1St->Phase2St	215	Covered	T4,T5,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T53,T109,T110
Phase2St->Phase3St	233	Covered	T4,T5,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T4,T22,T111
Phase3St->TerminalSt	249	Covered	T4,T5,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T6,T23
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T20
TimeoutSt->Phase0St	172	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T47,T112,T113
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T62,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T53,T109,T110
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T22,T111
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T6,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	711093775	276	0	0
CheckAccumTrig0_A	711093775	501	0	0
CheckAccumTrig1_A	711093775	20	0	0
CheckClr_A	711093775	213	0	0
CheckEn_A	710915653	342781969	0	0
CheckPhase0_A	711093775	575	0	0
CheckPhase1_A	711093775	565	0	0
CheckPhase2_A	711093775	558	0	0
CheckPhase3_A	711093775	548	0	0
CheckTimeout0_A	711093775	855	0	0
CheckTimeoutSt1_A	711093775	99456	0	0
CheckTimeoutSt2_A	711093775	773	0	0
CheckTimeoutStTrig_A	711093775	62	0	0
ErrorStAllEscAsserted_A	711093775	1460	0	0
ErrorStIsTerminal_A	711093775	1220	0	0
EscStateOut_A	710914142	710842289	0	0
u_state_regs_A	711093775	710920382	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	276	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T14	30966	57	0	0
T15	0	40	0	0
T16	0	69	0	0
T17	279213	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	971146	0	0	0
T35	0	42	0	0
T36	0	68	0	0
T37	5989	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	501	0	0
T4	826655	4	0	0
T5	913621	1	0	0
T6	371356	8	0	0
T7	30426	0	0	0
T8	0	2	0	0
T10	0	2	0	0
T14	30966	0	0	0
T17	0	1	0	0
T18	0	4	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	1	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	0	4	0	0
T33	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	20	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T17	279213	0	0	0
T18	477118	0	0	0
T19	0	1	0	0
T22	82335	1	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T26	0	1	0	0
T29	971146	0	0	0
T30	0	1	0	0
T37	5989	0	0	0
T42	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	80691	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	213	0	0
T4	826655	3	0	0
T5	913621	0	0	0
T6	371356	7	0	0
T7	30426	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T14	30966	0	0	0
T19	0	1	0	0
T20	26823	0	0	0
T21	52661	0	0	0
T22	82335	1	0	0
T23	96314	1	0	0
T24	33836	0	0	0
T29	0	1	0	0
T39	0	1	0	0
T62	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710915653	342781969	0	0
T1	31546	5584	0	0
T2	13862	10733	0	0
T3	94871	90451	0	0
T4	826655	1978	0	0
T5	913621	3293	0	0
T6	371356	2455	0	0
T14	172	107	0	0
T20	26823	586	0	0
T21	52661	3050	0	0
T22	82335	19375	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	575	0	0
T4	826655	4	0	0
T5	913621	1	0	0
T6	371356	8	0	0
T7	30426	0	0	0
T8	0	2	0	0
T14	30966	0	0	0
T17	0	1	0	0
T18	0	6	0	0
T20	26823	0	0	0
T21	52661	1	0	0
T22	82335	2	0	0
T23	96314	2	0	0
T24	33836	0	0	0
T29	0	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	565	0	0
T4	826655	4	0	0
T5	913621	1	0	0
T6	371356	7	0	0
T7	30426	0	0	0
T8	0	2	0	0
T14	30966	0	0	0
T17	0	1	0	0
T18	0	6	0	0
T20	26823	0	0	0
T21	52661	1	0	0
T22	82335	2	0	0
T23	96314	2	0	0
T24	33836	0	0	0
T29	0	5	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	558	0	0
T4	826655	4	0	0
T5	913621	1	0	0
T6	371356	7	0	0
T7	30426	0	0	0
T8	0	2	0	0
T14	30966	0	0	0
T17	0	1	0	0
T18	0	6	0	0
T20	26823	0	0	0
T21	52661	1	0	0
T22	82335	2	0	0
T23	96314	2	0	0
T24	33836	0	0	0
T29	0	5	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	548	0	0
T4	826655	3	0	0
T5	913621	1	0	0
T6	371356	7	0	0
T7	30426	0	0	0
T8	0	2	0	0
T14	30966	0	0	0
T17	0	1	0	0
T18	0	6	0	0
T20	26823	0	0	0
T21	52661	1	0	0
T22	82335	1	0	0
T23	96314	2	0	0
T24	33836	0	0	0
T29	0	5	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	855	0	0
T1	31546	7	0	0
T2	13862	2	0	0
T3	94871	0	0	0
T4	826655	0	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T14	30966	0	0	0
T17	0	1	0	0
T20	26823	10	0	0
T21	52661	1	0	0
T22	82335	2	0	0
T23	0	2	0	0
T24	0	6	0	0
T29	0	3	0	0
T57	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	99456	0	0
T1	31546	505	0	0
T2	13862	112	0	0
T3	94871	0	0	0
T4	826655	0	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T14	30966	0	0	0
T17	0	195	0	0
T20	26823	655	0	0
T21	52661	66	0	0
T22	82335	131	0	0
T23	0	50	0	0
T24	0	1237	0	0
T29	0	240	0	0
T57	0	1023	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	773	0	0
T1	31546	7	0	0
T2	13862	2	0	0
T3	94871	0	0	0
T4	826655	0	0	0
T5	913621	0	0	0
T6	371356	0	0	0
T14	30966	0	0	0
T17	0	1	0	0
T18	0	7	0	0
T20	26823	10	0	0
T21	52661	0	0	0
T22	82335	1	0	0
T24	0	6	0	0
T29	0	2	0	0
T39	0	7	0	0
T57	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	62	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T17	279213	0	0	0
T18	0	2	0	0
T21	52661	1	0	0
T22	82335	0	0	0
T23	96314	2	0	0
T24	33836	0	0	0
T26	0	1	0	0
T29	971146	1	0	0
T32	0	1	0	0
T37	5989	0	0	0
T39	0	2	0	0
T57	80691	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T73	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1460	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T14	30966	359	0	0
T15	0	164	0	0
T16	0	382	0	0
T17	279213	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	971146	0	0	0
T35	0	187	0	0
T36	0	368	0	0
T37	5989	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	1220	0	0
T7	30426	0	0	0
T8	251566	0	0	0
T14	30966	299	0	0
T15	0	134	0	0
T16	0	322	0	0
T17	279213	0	0	0
T21	52661	0	0	0
T22	82335	0	0	0
T23	96314	0	0	0
T24	33836	0	0	0
T29	971146	0	0	0
T35	0	157	0	0
T36	0	308	0	0
T37	5989	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710914142	710842289	0	0
T1	31546	31482	0	0
T2	13862	13809	0	0
T3	94871	94783	0	0
T4	826655	826569	0	0
T5	913621	913543	0	0
T6	371356	371348	0	0
T14	64	0	0	0
T20	26823	26735	0	0
T21	52661	52590	0	0
T22	82335	82284	0	0
T23	0	96221	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711093775	710920382	0	0
T1	31546	31482	0	0
T2	13862	13809	0	0
T3	94871	94783	0	0
T4	826655	826569	0	0
T5	913621	913543	0	0
T6	371356	371348	0	0
T14	30966	5532	0	0
T20	26823	26735	0	0
T21	52661	52590	0	0
T22	82335	82284	0	0