Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T10
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T61,T191
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14220	0	0
DisabledNoTrigBkwd_A	2147483647	831625	0	0
DisabledNoTrigFwd_A	2147483647	1506819055	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14220	0	0
T1	4016	624	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T6	127329	0	0	0
T10	33351	0	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T15	75144	0	0	0
T22	67091	0	0	0
T45	237009	0	0	0
T61	0	459	0	0
T67	79060	0	0	0
T68	142114	0	0	0
T75	21192	0	0	0
T177	0	1581	0	0
T191	4007	530	0	0
T192	0	333	0	0
T193	4118	796	0	0
T194	0	552	0	0
T195	0	1370	0	0
T196	0	398	0	0
T197	0	610	0	0
T198	0	678	0	0
T199	0	444	0	0
T200	0	802	0	0
T201	0	514	0	0
T202	0	540	0	0
T203	0	1553	0	0
T204	0	405	0	0
T205	0	783	0	0
T206	0	769	0	0
T207	0	479	0	0
T208	470963	0	0	0
T209	11281	0	0	0
T210	18812	0	0	0
T211	994902	0	0	0
T212	146240	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	831625	0	0
T1	4016	8	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T5	0	2376	0	0
T6	254658	3647	0	0
T10	133404	136	0	0
T11	1165856	3545	0	0
T12	924396	28	0	0
T13	135396	0	0	0
T14	984987	6253	0	0
T15	300576	6	0	0
T16	0	1240	0	0
T17	0	474	0	0
T20	428366	3194	0	0
T21	0	2861	0	0
T22	268364	75	0	0
T24	252798	0	0	0
T25	0	379	0	0
T26	0	301	0	0
T28	1136244	662	0	0
T41	0	137	0	0
T42	0	25	0	0
T43	0	421	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1506819055	0	0
T1	16064	12955	0	0
T2	351028	5444	0	0
T3	3539784	3416036	0	0
T6	509316	263399	0	0
T10	133404	4538	0	0
T11	1165856	594040	0	0
T12	924396	701585	0	0
T13	135396	73669	0	0
T15	300576	230751	0	0
T22	268364	208717	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T3,T6,T12
1	1	Covered	T1,T6,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T61,T177
1	1	Covered	T1,T6,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	671291291	3433	0	0
DisabledNoTrigBkwd_A	671291291	281938	0	0
DisabledNoTrigFwd_A	671291291	347240903	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	3433	0	0
T1	4016	624	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T6	127329	0	0	0
T10	33351	0	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T15	75144	0	0	0
T22	67091	0	0	0
T61	0	459	0	0
T177	0	1581	0	0
T206	0	769	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	281938	0	0
T1	4016	8	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T6	127329	1826	0	0
T10	33351	22	0	0
T11	291464	2141	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	0	1612	0	0
T15	75144	6	0	0
T16	0	426	0	0
T20	0	1	0	0
T22	67091	75	0	0
T28	0	198	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	347240903	0	0
T1	4016	3220	0	0
T2	87757	1355	0	0
T3	884946	884850	0	0
T6	127329	3669	0	0
T10	33351	582	0	0
T11	291464	2072	0	0
T12	231099	231027	0	0
T13	33849	3644	0	0
T15	75144	5586	0	0
T22	67091	7630	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T10
1	1	Covered	T2,T3,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T191,T195,T196
1	1	Covered	T2,T3,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	671291291	5826	0	0
DisabledNoTrigBkwd_A	671291291	181467	0	0
DisabledNoTrigFwd_A	671291291	380401164	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	5826	0	0
T45	237009	0	0	0
T67	79060	0	0	0
T68	142114	0	0	0
T75	21192	0	0	0
T191	4007	530	0	0
T195	0	1370	0	0
T196	0	398	0	0
T198	0	678	0	0
T201	0	514	0	0
T203	0	1553	0	0
T205	0	783	0	0
T208	470963	0	0	0
T209	11281	0	0	0
T210	18812	0	0	0
T211	994902	0	0	0
T212	146240	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	181467	0	0
T5	0	2238	0	0
T10	33351	38	0	0
T11	291464	0	0	0
T12	231099	28	0	0
T13	33849	0	0	0
T14	328329	2276	0	0
T15	75144	0	0	0
T20	214183	0	0	0
T21	0	1156	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	207	0	0
T26	0	200	0	0
T28	378748	238	0	0
T42	0	25	0	0
T43	0	421	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	380401164	0	0
T1	4016	3230	0	0
T2	87757	1359	0	0
T3	884946	819370	0	0
T6	127329	127323	0	0
T10	33351	2772	0	0
T11	291464	291083	0	0
T12	231099	8504	0	0
T13	33849	2523	0	0
T15	75144	75055	0	0
T22	67091	67029	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T6,T11,T12
1	1	Covered	T10,T11,T14

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T193,T199,T207
1	1	Covered	T10,T11,T14

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T14,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T11,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	671291291	1719	0	0
DisabledNoTrigBkwd_A	671291291	175217	0	0
DisabledNoTrigFwd_A	671291291	399470712	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	1719	0	0
T111	36203	0	0	0
T193	4118	796	0	0
T199	0	444	0	0
T207	0	479	0	0
T213	238582	0	0	0
T214	52088	0	0	0
T215	25078	0	0	0
T216	32251	0	0	0
T217	30500	0	0	0
T218	11352	0	0	0
T219	133814	0	0	0
T220	583365	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	175217	0	0
T5	0	112	0	0
T10	33351	30	0	0
T11	291464	1404	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T17	0	474	0	0
T20	214183	8	0	0
T21	0	1701	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	2	0	0
T26	0	29	0	0
T28	378748	226	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	399470712	0	0
T1	4016	3240	0	0
T2	87757	1363	0	0
T3	884946	884850	0	0
T6	127329	127323	0	0
T10	33351	590	0	0
T11	291464	9429	0	0
T12	231099	231027	0	0
T13	33849	33751	0	0
T15	75144	75055	0	0
T22	67091	67029	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T11
1	1	Covered	T6,T10,T14

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T192,T194,T197
1	1	Covered	T6,T10,T14

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T14,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T10,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	671291291	3242	0	0
DisabledNoTrigBkwd_A	671291291	193003	0	0
DisabledNoTrigFwd_A	671291291	379706276	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	3242	0	0
T83	139406	0	0	0
T84	503565	0	0	0
T90	876250	0	0	0
T98	259500	0	0	0
T105	32379	0	0	0
T192	1051	333	0	0
T194	0	552	0	0
T197	0	610	0	0
T200	0	802	0	0
T202	0	540	0	0
T204	0	405	0	0
T221	13475	0	0	0
T222	5920	0	0	0
T223	16965	0	0	0
T224	103754	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	193003	0	0
T5	0	26	0	0
T6	127329	1821	0	0
T10	33351	46	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	2364	0	0
T15	75144	0	0	0
T16	0	814	0	0
T20	0	3185	0	0
T21	0	4	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	170	0	0
T26	0	72	0	0
T28	378748	0	0	0
T41	0	137	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	379706276	0	0
T1	4016	3265	0	0
T2	87757	1367	0	0
T3	884946	826966	0	0
T6	127329	5084	0	0
T10	33351	594	0	0
T11	291464	291456	0	0
T12	231099	231027	0	0
T13	33849	33751	0	0
T15	75144	75055	0	0
T22	67091	67029	0	0