Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_alert_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alerts[0].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[1].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[2].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[3].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[4].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[5].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[6].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[7].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[8].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[9].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[10].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[11].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[12].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[13].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[14].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[15].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[16].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[17].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[18].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[19].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[20].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[21].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[22].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[23].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[24].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[25].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[26].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[27].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[28].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[29].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[30].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[31].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[32].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[33].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[34].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[35].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[36].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[37].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[38].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[39].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[40].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[41].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[42].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[43].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[44].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[45].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[46].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[47].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[48].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[49].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[50].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[51].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[52].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[53].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[54].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[55].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[56].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[57].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[58].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[59].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[60].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[61].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[62].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[63].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[64].u_alert_receiver 100.00 100.00



Module Instance : tb.dut.gen_alerts[0].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[1].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[2].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[3].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[4].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[5].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[6].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[7].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[8].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[9].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[10].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[11].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[12].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[13].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[14].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[15].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[16].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[17].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[18].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[19].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[20].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[21].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[22].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[23].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[24].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[25].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[26].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[27].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[28].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[29].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[30].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[31].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[32].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[33].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[34].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[35].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[36].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[37].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[38].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[39].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[40].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[41].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[42].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[43].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[44].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[45].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[46].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[47].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[48].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[49].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[50].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[51].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[52].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[53].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[54].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[55].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[56].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[57].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[58].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[59].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[60].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[61].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[62].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[63].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[64].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T11 Yes T2,T6,T11 INPUT
ping_ok_o Yes Yes T2,T6,T11 Yes T2,T6,T11 OUTPUT
integ_fail_o Yes Yes T6,T20,T5 Yes T6,T20,T5 OUTPUT
alert_o Yes Yes T1,T6,T10 Yes T1,T6,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T11 Yes T2,T3,T11 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T3,T11 Yes T2,T6,T11 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T6 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[0].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T4,T29 Yes T2,T4,T29 INPUT
ping_ok_o Yes Yes T2,T4,T29 Yes T2,T4,T29 OUTPUT
integ_fail_o Yes Yes T6,T20,T25 Yes T6,T20,T25 OUTPUT
alert_o Yes Yes T1,T6,T10 Yes T1,T6,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T29 Yes T2,T4,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T29 Yes T2,T4,T29 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T6 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[1].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T11,T20 Yes T2,T11,T20 INPUT
ping_ok_o Yes Yes T2,T11,T20 Yes T2,T11,T20 OUTPUT
integ_fail_o Yes Yes T20,T5,T29 Yes T20,T5,T29 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T11,T20 Yes T2,T4,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T29 Yes T2,T11,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[2].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T14 Yes T2,T6,T14 INPUT
ping_ok_o Yes Yes T2,T6,T14 Yes T2,T6,T14 OUTPUT
integ_fail_o Yes Yes T6,T20,T5 Yes T6,T20,T5 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T14 Yes T2,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T5 Yes T2,T6,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[3].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T20,T4 Yes T2,T20,T4 INPUT
ping_ok_o Yes Yes T2,T20,T4 Yes T2,T20,T4 OUTPUT
integ_fail_o Yes Yes T42,T29,T72 Yes T42,T29,T72 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T20,T4 Yes T2,T20,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T20,T4 Yes T2,T20,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[4].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T17 Yes T2,T3,T17 INPUT
ping_ok_o Yes Yes T2,T17,T4 Yes T2,T17,T4 OUTPUT
integ_fail_o Yes Yes T6,T26,T29 Yes T6,T26,T29 OUTPUT
alert_o Yes Yes T1,T6,T10 Yes T1,T6,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T6 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[5].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T4,T5 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T11,T4 Yes T2,T11,T4 INPUT
ping_ok_o Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
integ_fail_o Yes Yes T6,T20,T5 Yes T6,T20,T5 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[6].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T6 Yes T2,T3,T6 INPUT
ping_ok_o Yes Yes T2,T6,T16 Yes T2,T6,T16 OUTPUT
integ_fail_o Yes Yes T6,T20,T5 Yes T6,T20,T5 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T6 Yes T2,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T5 Yes T2,T3,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[7].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T4,T5 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T14,T4 Yes T2,T14,T4 INPUT
ping_ok_o Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
integ_fail_o Yes Yes T6,T225,T66 Yes T6,T225,T66 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[8].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T4 Yes T2,T6,T4 INPUT
ping_ok_o Yes Yes T2,T6,T4 Yes T2,T6,T4 OUTPUT
integ_fail_o Yes Yes T20,T5,T26 Yes T20,T5,T26 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T4 Yes T2,T4,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T29 Yes T2,T6,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[9].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T4,T29 Yes T2,T4,T29 INPUT
ping_ok_o Yes Yes T2,T4,T29 Yes T2,T4,T29 OUTPUT
integ_fail_o Yes Yes T20,T25,T30 Yes T20,T25,T30 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T29 Yes T2,T4,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T29 Yes T2,T4,T29 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[10].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T14 Yes T2,T3,T14 INPUT
ping_ok_o Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
integ_fail_o Yes Yes T6,T26,T29 Yes T6,T26,T29 OUTPUT
alert_o Yes Yes T1,T6,T10 Yes T1,T6,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T14 Yes T2,T4,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T30 Yes T2,T3,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T6 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[11].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T6 Yes T2,T3,T6 INPUT
ping_ok_o Yes Yes T2,T6,T4 Yes T2,T6,T4 OUTPUT
integ_fail_o Yes Yes T26,T42,T29 Yes T26,T42,T29 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T6 Yes T2,T4,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T26 Yes T2,T3,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[12].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T11 Yes T2,T3,T11 INPUT
ping_ok_o Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
integ_fail_o Yes Yes T5,T26,T45 Yes T5,T26,T45 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T11 Yes T2,T4,T226 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T226 Yes T2,T3,T11 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[13].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T16,T4 Yes T2,T16,T4 INPUT
ping_ok_o Yes Yes T2,T16,T4 Yes T2,T16,T4 OUTPUT
integ_fail_o Yes Yes T5,T25,T30 Yes T5,T25,T30 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T26 Yes T2,T4,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T26 Yes T2,T4,T26 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[14].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T20,T4 Yes T2,T20,T4 INPUT
ping_ok_o Yes Yes T2,T20,T4 Yes T2,T20,T4 OUTPUT
integ_fail_o Yes Yes T20,T5,T26 Yes T20,T5,T26 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T20,T4 Yes T2,T4,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T29 Yes T2,T20,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[15].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T11 Yes T2,T6,T11 INPUT
ping_ok_o Yes Yes T2,T6,T11 Yes T2,T6,T11 OUTPUT
integ_fail_o Yes Yes T6,T20,T25 Yes T6,T20,T25 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T11 Yes T2,T4,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T29 Yes T2,T6,T11 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[16].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T11,T4 Yes T2,T11,T4 INPUT
ping_ok_o Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
integ_fail_o Yes Yes T5,T26,T72 Yes T5,T26,T72 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T11,T4 Yes T2,T4,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T26 Yes T2,T11,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[17].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T11 Yes T2,T3,T11 INPUT
ping_ok_o Yes Yes T2,T11,T20 Yes T2,T11,T20 OUTPUT
integ_fail_o Yes Yes T20,T25,T26 Yes T20,T25,T26 OUTPUT
alert_o Yes Yes T1,T6,T10 Yes T1,T6,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T11 Yes T2,T4,T226 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T226 Yes T2,T3,T11 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T6 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[18].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T11,T14 Yes T2,T11,T14 INPUT
ping_ok_o Yes Yes T2,T11,T14 Yes T2,T11,T14 OUTPUT
integ_fail_o Yes Yes T25,T30,T225 Yes T25,T30,T225 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T11,T14 Yes T2,T4,T226 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T226 Yes T2,T11,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[19].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T4,T5 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T4 Yes T2,T6,T4 INPUT
ping_ok_o Yes Yes T2,T6,T4 Yes T2,T6,T4 OUTPUT
integ_fail_o Yes Yes T6,T225,T32 Yes T6,T225,T32 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T4 Yes T2,T6,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T6,T4 Yes T2,T6,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[20].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T20,T4 Yes T2,T20,T4 INPUT
ping_ok_o Yes Yes T2,T20,T4 Yes T2,T20,T4 OUTPUT
integ_fail_o Yes Yes T6,T20,T25 Yes T6,T20,T25 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T20,T4 Yes T2,T20,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T20,T4 Yes T2,T20,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[21].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T14,T4 Yes T2,T14,T4 INPUT
ping_ok_o Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
integ_fail_o Yes Yes T5,T26,T42 Yes T5,T26,T42 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[22].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
ping_ok_o Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
integ_fail_o Yes Yes T20,T5,T42 Yes T20,T5,T42 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[23].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
ping_ok_o Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
integ_fail_o Yes Yes T6,T20,T42 Yes T6,T20,T42 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[24].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
ping_ok_o Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
integ_fail_o Yes Yes T6,T5,T25 Yes T6,T5,T25 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[25].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T20,T16 Yes T2,T20,T16 INPUT
ping_ok_o Yes Yes T2,T20,T16 Yes T2,T20,T16 OUTPUT
integ_fail_o Yes Yes T6,T5,T25 Yes T6,T5,T25 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T20,T4 Yes T2,T20,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T20,T4 Yes T2,T20,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[26].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T11 Yes T2,T3,T11 INPUT
ping_ok_o Yes Yes T2,T11,T17 Yes T2,T11,T17 OUTPUT
integ_fail_o Yes Yes T6,T20,T5 Yes T6,T20,T5 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T11 Yes T2,T4,T21 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T21 Yes T2,T3,T11 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[27].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T11,T4 Yes T2,T11,T4 INPUT
ping_ok_o Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
integ_fail_o Yes Yes T30,T225,T32 Yes T30,T225,T32 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[28].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T4,T5 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T11 Yes T2,T6,T11 INPUT
ping_ok_o Yes Yes T2,T6,T11 Yes T2,T6,T11 OUTPUT
integ_fail_o Yes Yes T5,T25,T26 Yes T5,T25,T26 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T11 Yes T2,T6,T11 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T6,T11 Yes T2,T6,T11 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[29].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T4,T5 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T11 Yes T2,T6,T11 INPUT
ping_ok_o Yes Yes T2,T6,T11 Yes T2,T6,T11 OUTPUT
integ_fail_o Yes Yes T20,T5,T42 Yes T20,T5,T42 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T11 Yes T2,T4,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T26 Yes T2,T6,T11 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[30].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T6 Yes T2,T3,T6 INPUT
ping_ok_o Yes Yes T2,T6,T11 Yes T2,T6,T11 OUTPUT
integ_fail_o Yes Yes T72,T32,T104 Yes T72,T32,T104 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T6 Yes T2,T4,T226 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T226 Yes T2,T3,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[31].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T20,T17 Yes T2,T20,T17 INPUT
ping_ok_o Yes Yes T2,T20,T4 Yes T2,T20,T4 OUTPUT
integ_fail_o Yes Yes T6,T20,T26 Yes T6,T20,T26 OUTPUT
alert_o Yes Yes T1,T6,T10 Yes T1,T6,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T20,T17 Yes T2,T20,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T20,T4 Yes T2,T20,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T6 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[32].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T4,T43 Yes T2,T4,T43 INPUT
ping_ok_o Yes Yes T2,T4,T43 Yes T2,T4,T43 OUTPUT
integ_fail_o Yes Yes T42,T29,T30 Yes T42,T29,T30 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T64 Yes T2,T4,T64 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T64 Yes T2,T4,T64 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[33].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T4,T29 Yes T2,T4,T29 INPUT
ping_ok_o Yes Yes T2,T4,T29 Yes T2,T4,T29 OUTPUT
integ_fail_o Yes Yes T26,T29,T32 Yes T26,T29,T32 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T29 Yes T2,T4,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T29 Yes T2,T4,T29 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[34].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T4,T5 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T4,T64 Yes T2,T4,T64 INPUT
ping_ok_o Yes Yes T2,T4,T64 Yes T2,T4,T64 OUTPUT
integ_fail_o Yes Yes T6,T5,T25 Yes T6,T5,T25 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T64 Yes T2,T4,T226 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T226 Yes T2,T4,T64 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[35].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T14 Yes T2,T3,T14 INPUT
ping_ok_o Yes Yes T2,T14,T20 Yes T2,T14,T20 OUTPUT
integ_fail_o Yes Yes T6,T20,T5 Yes T6,T20,T5 OUTPUT
alert_o Yes Yes T1,T6,T10 Yes T1,T6,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T14 Yes T2,T20,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T20,T4 Yes T2,T3,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T6 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[36].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T11,T14 Yes T2,T11,T14 INPUT
ping_ok_o Yes Yes T2,T11,T14 Yes T2,T11,T14 OUTPUT
integ_fail_o Yes Yes T6,T5,T25 Yes T6,T5,T25 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T11,T14 Yes T2,T4,T226 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T226 Yes T2,T11,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[37].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T20,T4 Yes T2,T20,T4 INPUT
ping_ok_o Yes Yes T2,T20,T4 Yes T2,T20,T4 OUTPUT
integ_fail_o Yes Yes T20,T5,T26 Yes T20,T5,T26 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T20,T4 Yes T2,T4,T226 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T226 Yes T2,T20,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[38].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T11 Yes T2,T3,T11 INPUT
ping_ok_o Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
integ_fail_o Yes Yes T5,T30,T32 Yes T5,T30,T32 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T11 Yes T2,T4,T226 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T226 Yes T2,T3,T11 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[39].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T11,T20 Yes T2,T11,T20 INPUT
ping_ok_o Yes Yes T2,T11,T20 Yes T2,T11,T20 OUTPUT
integ_fail_o Yes Yes T20,T225,T32 Yes T20,T225,T32 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T11,T20 Yes T2,T4,T37 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T37 Yes T2,T11,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[40].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T4,T5 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T14 Yes T2,T3,T14 INPUT
ping_ok_o Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
integ_fail_o Yes Yes T6,T26,T225 Yes T6,T26,T225 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T14 Yes T2,T4,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T26 Yes T2,T3,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[41].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T14,T4 Yes T2,T14,T4 INPUT
ping_ok_o Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
integ_fail_o Yes Yes T6,T20,T5 Yes T6,T20,T5 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T14,T4 Yes T2,T4,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T29 Yes T2,T14,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[42].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T14 Yes T2,T6,T14 INPUT
ping_ok_o Yes Yes T2,T6,T14 Yes T2,T6,T14 OUTPUT
integ_fail_o Yes Yes T25,T29,T30 Yes T25,T29,T30 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T14 Yes T2,T14,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T14,T4 Yes T2,T6,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[43].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T11,T17 Yes T2,T11,T17 INPUT
ping_ok_o Yes Yes T2,T11,T17 Yes T2,T11,T17 OUTPUT
integ_fail_o Yes Yes T20,T5,T29 Yes T20,T5,T29 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T11,T4 Yes T2,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T5 Yes T2,T11,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[44].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T4,T5 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T14 Yes T2,T6,T14 INPUT
ping_ok_o Yes Yes T2,T6,T14 Yes T2,T6,T14 OUTPUT
integ_fail_o Yes Yes T6,T42,T32 Yes T6,T42,T32 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T14 Yes T2,T4,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T26 Yes T2,T6,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[45].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T20 Yes T2,T6,T20 INPUT
ping_ok_o Yes Yes T2,T6,T20 Yes T2,T6,T20 OUTPUT
integ_fail_o Yes Yes T20,T25,T26 Yes T20,T25,T26 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T20 Yes T2,T20,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T20,T4 Yes T2,T6,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[46].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T14,T4 Yes T2,T14,T4 INPUT
ping_ok_o Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
integ_fail_o Yes Yes T26,T30,T32 Yes T26,T30,T32 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T14,T4 Yes T2,T4,T226 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T226 Yes T2,T14,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[47].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T4,T5 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T14,T16 Yes T2,T14,T16 INPUT
ping_ok_o Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
integ_fail_o Yes Yes T6,T20,T5 Yes T6,T20,T5 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T14,T16 Yes T2,T14,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T14,T4 Yes T2,T14,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[48].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T4,T5 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T14,T4 Yes T2,T14,T4 INPUT
ping_ok_o Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
integ_fail_o Yes Yes T6,T29,T32 Yes T6,T29,T32 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[49].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T3,T14 Yes T2,T3,T14 INPUT
ping_ok_o Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
integ_fail_o Yes Yes T5,T25,T42 Yes T5,T25,T42 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T3,T14 Yes T2,T4,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T30 Yes T2,T3,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[50].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T11,T4 Yes T2,T11,T4 INPUT
ping_ok_o Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
integ_fail_o Yes Yes T20,T5,T72 Yes T20,T5,T72 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[51].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T4,T21 Yes T2,T4,T21 INPUT
ping_ok_o Yes Yes T2,T4,T21 Yes T2,T4,T21 OUTPUT
integ_fail_o Yes Yes T20,T26,T42 Yes T20,T26,T42 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T21 Yes T2,T4,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T26 Yes T2,T4,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[52].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T20 Yes T2,T6,T20 INPUT
ping_ok_o Yes Yes T2,T6,T20 Yes T2,T6,T20 OUTPUT
integ_fail_o Yes Yes T6,T20,T5 Yes T6,T20,T5 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T20 Yes T2,T6,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T6,T4 Yes T2,T6,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[53].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T20,T4 Yes T2,T20,T4 INPUT
ping_ok_o Yes Yes T2,T20,T4 Yes T2,T20,T4 OUTPUT
integ_fail_o Yes Yes T42,T29,T30 Yes T42,T29,T30 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T20,T4 Yes T2,T4,T21 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T21 Yes T2,T20,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[54].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T14,T4 Yes T2,T14,T4 INPUT
ping_ok_o Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
integ_fail_o Yes Yes T6,T20,T225 Yes T6,T20,T225 OUTPUT
alert_o Yes Yes T1,T6,T10 Yes T1,T6,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T6 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[55].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T20 Yes T2,T6,T20 INPUT
ping_ok_o Yes Yes T2,T6,T20 Yes T2,T6,T20 OUTPUT
integ_fail_o Yes Yes T26,T30,T68 Yes T26,T30,T68 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T20 Yes T2,T20,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T20,T4 Yes T2,T6,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[56].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T20 Yes T2,T6,T20 INPUT
ping_ok_o Yes Yes T2,T6,T20 Yes T2,T6,T20 OUTPUT
integ_fail_o Yes Yes T20,T26,T29 Yes T20,T26,T29 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T20 Yes T2,T20,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T20,T4 Yes T2,T6,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[57].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T11,T4 Yes T2,T11,T4 INPUT
ping_ok_o Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
integ_fail_o Yes Yes T20,T5,T29 Yes T20,T5,T29 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T11,T4 Yes T2,T4,T5 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T5 Yes T2,T11,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[58].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T4 Yes T2,T6,T4 INPUT
ping_ok_o Yes Yes T2,T6,T4 Yes T2,T6,T4 OUTPUT
integ_fail_o Yes Yes T6,T20,T25 Yes T6,T20,T25 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T4 Yes T2,T4,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T26 Yes T2,T6,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[59].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T11 Yes T2,T6,T11 INPUT
ping_ok_o Yes Yes T2,T6,T11 Yes T2,T6,T11 OUTPUT
integ_fail_o Yes Yes T26,T42,T29 Yes T26,T42,T29 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T11 Yes T2,T4,T226 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T226 Yes T2,T6,T11 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[60].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T14,T20 Yes T2,T14,T20 INPUT
ping_ok_o Yes Yes T2,T14,T20 Yes T2,T14,T20 OUTPUT
integ_fail_o Yes Yes T29,T66,T227 Yes T29,T66,T227 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T14,T20 Yes T2,T4,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T26 Yes T2,T14,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[61].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T6,T20 Yes T2,T6,T20 INPUT
ping_ok_o Yes Yes T2,T6,T20 Yes T2,T6,T20 OUTPUT
integ_fail_o Yes Yes T20,T25,T42 Yes T20,T25,T42 OUTPUT
alert_o Yes Yes T1,T6,T10 Yes T1,T6,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T6,T20 Yes T2,T4,T64 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T64 Yes T2,T6,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T6 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[62].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T11,T14 Yes T2,T11,T14 INPUT
ping_ok_o Yes Yes T2,T11,T14 Yes T2,T11,T14 OUTPUT
integ_fail_o Yes Yes T5,T26,T225 Yes T5,T26,T225 OUTPUT
alert_o Yes Yes T1,T6,T10 Yes T1,T6,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T11,T14 Yes T2,T14,T4 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T14,T4 Yes T2,T11,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T6 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[63].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T11,T4 Yes T2,T11,T4 INPUT
ping_ok_o Yes Yes T2,T11,T4 Yes T2,T11,T4 OUTPUT
integ_fail_o Yes Yes T20,T5,T25 Yes T20,T5,T25 OUTPUT
alert_o Yes Yes T1,T6,T10 Yes T1,T6,T10 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T6 Yes T1,T2,T6 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T11,T4 Yes T2,T4,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T26 Yes T2,T11,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T6 Yes T1,T2,T6 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[64].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T2,T16,T4 Yes T2,T3,T6 INPUT
ping_req_i Yes Yes T2,T4,T26 Yes T2,T4,T26 INPUT
ping_ok_o Yes Yes T2,T4,T26 Yes T2,T4,T26 OUTPUT
integ_fail_o Yes Yes T6,T20,T5 Yes T6,T20,T5 OUTPUT
alert_o Yes Yes T6,T10,T11 Yes T6,T10,T11 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T6,T10 Yes T2,T6,T10 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T26 Yes T2,T4,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T2,T4,T26 Yes T2,T4,T26 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T6,T10 Yes T2,T6,T10 INPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%