Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.39	100.00	97.78	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T23
1	1	1	Covered	T1,T2,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T15,T13
1	0	1	Covered	T1,T3,T11
1	1	0	Covered	T13,T24,T20
1	1	1	Covered	T10,T15,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T15,T13,T24
0	1	Covered	T15,T5,T25
1	0	Covered	T10,T5,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T13,T24
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T5,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T13
1	0	Covered	T27
1	1	Covered	T15,T5,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T10,T11
1	Covered	T1,T10,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T6,T14,T28

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T6,T11,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T10,T11,T28

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T6,T10

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T6,T10
Phase1St	198	Covered	T1,T6,T10
Phase2St	215	Covered	T1,T6,T10
Phase3St	233	Covered	T1,T6,T10
TerminalSt	249	Covered	T1,T6,T10
TimeoutSt	159	Covered	T10,T15,T13

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T6,T10
IdleSt->TimeoutSt	159	Covered	T10,T15,T13
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T29,T30,T31
Phase0St->Phase1St	198	Covered	T1,T6,T10
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T5,T25,T26
Phase1St->Phase2St	215	Covered	T1,T6,T10
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T14,T25,T32
Phase2St->Phase3St	233	Covered	T1,T6,T10
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T10,T5,T25
Phase3St->TerminalSt	249	Covered	T1,T6,T10
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T10,T15,T21
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T13,T24,T20
TimeoutSt->Phase0St	172	Covered	T10,T15,T5

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T15,T13,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T24,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T31,T32
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T6,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T6,T10,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T25,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T6,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T6,T10,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T25,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T6,T10
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T10,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T10,T5,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T6,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T10,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T15,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T6,T10
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	815	0	0
CheckAccumTrig0_A	2147483647	2356	0	0
CheckAccumTrig1_A	2147483647	115	0	0
CheckClr_A	2147483647	1131	0	0
CheckEn_A	2147483647	1163980242	0	0
CheckPhase0_A	2147483647	2700	0	0
CheckPhase1_A	2147483647	2646	0	0
CheckPhase2_A	2147483647	2589	0	0
CheckPhase3_A	2147483647	2536	0	0
CheckTimeout0_A	2147483647	5824	0	0
CheckTimeoutSt1_A	2147483647	557721	0	0
CheckTimeoutSt2_A	2147483647	5423	0	0
CheckTimeoutStTrig_A	2147483647	282	0	0
ErrorStAllEscAsserted_A	2147483647	4486	0	0
ErrorStIsTerminal_A	2147483647	3646	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	815	0	0
T7	82332	115	0	0
T8	0	125	0	0
T9	0	112	0	0
T19	3538940	0	0	0
T30	431968	0	0	0
T31	221740	0	0	0
T33	0	244	0	0
T34	0	219	0	0
T35	195824	0	0	0
T36	96780	0	0	0
T37	1459800	0	0	0
T38	1338776	0	0	0
T39	358048	0	0	0
T40	132096	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2356	0	0
T1	4016	1	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T5	0	22	0	0
T6	254658	2	0	0
T10	133404	21	0	0
T11	1165856	2	0	0
T12	924396	1	0	0
T13	135396	0	0	0
T14	984987	4	0	0
T15	300576	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T20	428366	3	0	0
T21	0	5	0	0
T22	268364	1	0	0
T24	252798	0	0	0
T25	0	7	0	0
T26	0	15	0	0
T28	1136244	3	0	0
T29	0	7	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115	0	0
T5	976652	3	0	0
T10	33351	2	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	0	0	0
T15	75144	0	0	0
T18	126420	0	0	0
T20	214183	0	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T26	269266	3	0	0
T28	378748	0	0	0
T29	736192	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T42	60914	0	0	0
T43	332248	0	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	186138	0	0	0
T60	15698	0	0	0
T61	3360	0	0	0
T62	81590	0	0	0
T63	21468	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1131	0	0
T5	0	23	0	0
T10	133404	19	0	0
T11	1165856	0	0	0
T12	924396	0	0	0
T13	135396	0	0	0
T14	1313316	1	0	0
T15	300576	1	0	0
T20	856732	0	0	0
T21	0	2	0	0
T22	268364	0	0	0
T24	337064	0	0	0
T25	0	15	0	0
T26	0	13	0	0
T28	1514992	0	0	0
T29	0	16	0	0
T30	0	3	0	0
T31	0	1	0	0
T32	0	10	0	0
T38	0	1	0	0
T42	0	2	0	0
T43	0	8	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	6	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1163980242	0	0
T1	16064	12955	0	0
T2	351028	5440	0	0
T3	3539784	3416032	0	0
T6	509316	255876	0	0
T10	133404	3051	0	0
T11	1165856	590430	0	0
T12	924396	701582	0	0
T13	135396	73667	0	0
T15	300576	230748	0	0
T22	268364	208714	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2700	0	0
T1	4016	1	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T5	0	25	0	0
T6	254658	2	0	0
T10	133404	23	0	0
T11	1165856	2	0	0
T12	924396	1	0	0
T13	135396	0	0	0
T14	984987	4	0	0
T15	300576	2	0	0
T16	0	2	0	0
T17	0	1	0	0
T20	428366	3	0	0
T21	0	5	0	0
T22	268364	1	0	0
T24	252798	0	0	0
T25	0	11	0	0
T26	0	18	0	0
T28	1136244	3	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2646	0	0
T1	4016	1	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T5	0	24	0	0
T6	254658	2	0	0
T10	133404	23	0	0
T11	1165856	2	0	0
T12	924396	1	0	0
T13	135396	0	0	0
T14	984987	4	0	0
T15	300576	2	0	0
T16	0	2	0	0
T17	0	1	0	0
T20	428366	3	0	0
T21	0	5	0	0
T22	268364	1	0	0
T24	252798	0	0	0
T25	0	10	0	0
T26	0	18	0	0
T28	1136244	3	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2589	0	0
T1	4016	1	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T5	0	24	0	0
T6	254658	2	0	0
T10	133404	23	0	0
T11	1165856	2	0	0
T12	924396	1	0	0
T13	135396	0	0	0
T14	984987	3	0	0
T15	300576	2	0	0
T16	0	2	0	0
T17	0	1	0	0
T20	428366	3	0	0
T21	0	5	0	0
T22	268364	1	0	0
T24	252798	0	0	0
T25	0	10	0	0
T26	0	18	0	0
T28	1136244	3	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2536	0	0
T1	4016	1	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T5	0	23	0	0
T6	254658	2	0	0
T10	133404	20	0	0
T11	1165856	2	0	0
T12	924396	1	0	0
T13	135396	0	0	0
T14	984987	3	0	0
T15	300576	2	0	0
T16	0	2	0	0
T17	0	1	0	0
T20	428366	3	0	0
T21	0	5	0	0
T22	268364	1	0	0
T24	252798	0	0	0
T25	0	9	0	0
T26	0	18	0	0
T28	1136244	3	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5824	0	0
T4	18107	0	0	0
T5	976652	32	0	0
T10	33351	2	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	67698	18	0	0
T14	656658	0	0	0
T15	75144	1	0	0
T16	170928	0	0	0
T17	244768	0	0	0
T20	428366	1	0	0
T21	195375	0	0	0
T22	134182	0	0	0
T24	168532	7	0	0
T25	974423	34	0	0
T26	0	33	0	0
T28	757496	0	0	0
T29	0	85	0	0
T35	0	5	0	0
T41	330723	0	0	0
T42	0	3	0	0
T59	0	11	0	0
T60	0	3	0	0
T63	0	5	0	0
T69	153972	14	0	0
T70	88170	8	0	0
T71	0	4	0	0
T72	0	2	0	0
T73	43222	0	0	0
T74	4418	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	557721	0	0
T4	36214	0	0	0
T5	1953304	2179	0	0
T12	231099	0	0	0
T13	67698	2065	0	0
T14	656658	0	0	0
T15	75144	41	0	0
T16	341856	0	0	0
T17	367152	0	0	0
T20	428366	72	0	0
T21	390750	0	0	0
T22	134182	0	0	0
T24	168532	866	0	0
T25	1948846	5416	0	0
T26	0	3788	0	0
T28	757496	0	0	0
T29	0	11786	0	0
T30	0	221	0	0
T35	0	795	0	0
T41	661446	0	0	0
T42	0	1243	0	0
T59	0	2298	0	0
T60	0	185	0	0
T63	0	304	0	0
T69	230958	1895	0	0
T70	176340	1270	0	0
T71	17498	612	0	0
T72	0	558	0	0
T73	86444	0	0	0
T74	8836	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5423	0	0
T4	36214	0	0	0
T5	1953304	27	0	0
T13	67698	18	0	0
T14	656658	0	0	0
T16	341856	0	0	0
T17	489536	0	0	0
T20	428366	1	0	0
T21	390750	0	0	0
T22	134182	0	0	0
T24	168532	7	0	0
T25	1948846	29	0	0
T26	0	29	0	0
T28	757496	0	0	0
T29	0	81	0	0
T30	0	2	0	0
T32	0	140	0	0
T35	0	7	0	0
T40	0	1	0	0
T41	661446	0	0	0
T42	0	1	0	0
T59	0	11	0	0
T60	0	2	0	0
T63	0	4	0	0
T69	307944	14	0	0
T70	176340	8	0	0
T71	17498	4	0	0
T73	86444	0	0	0
T74	8836	0	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	282	0	0
T5	1953304	2	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	0	0	0
T15	75144	1	0	0
T16	170928	0	0	0
T18	126420	0	0	0
T20	214183	0	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	1948846	5	0	0
T26	269266	0	0	0
T28	378748	0	0	0
T29	1104288	4	0	0
T31	0	2	0	0
T32	0	11	0	0
T39	0	1	0	0
T41	330723	0	0	0
T42	60914	2	0	0
T43	332248	0	0	0
T46	0	3	0	0
T48	0	8	0	0
T59	186138	0	0	0
T63	0	1	0	0
T71	17498	0	0	0
T72	0	1	0	0
T73	86444	0	0	0
T74	8836	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	4	0	0
T79	0	3	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4486	0	0
T7	82332	595	0	0
T8	0	654	0	0
T9	0	658	0	0
T19	3538940	0	0	0
T30	431968	0	0	0
T31	221740	0	0	0
T33	0	1253	0	0
T34	0	1326	0	0
T35	195824	0	0	0
T36	96780	0	0	0
T37	1459800	0	0	0
T38	1338776	0	0	0
T39	358048	0	0	0
T40	132096	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3646	0	0
T7	82332	475	0	0
T8	0	534	0	0
T9	0	538	0	0
T19	3538940	0	0	0
T30	431968	0	0	0
T31	221740	0	0	0
T33	0	1013	0	0
T34	0	1086	0	0
T35	195824	0	0	0
T36	96780	0	0	0
T37	1459800	0	0	0
T38	1338776	0	0	0
T39	358048	0	0	0
T40	132096	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16064	15712	0	0
T2	351028	350360	0	0
T3	3539784	3539400	0	0
T6	509316	509292	0	0
T10	133404	133040	0	0
T11	1165856	1165824	0	0
T12	924396	924108	0	0
T13	135396	135004	0	0
T15	300576	300220	0	0
T22	268364	268116	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16064	15712	0	0
T2	351028	350360	0	0
T3	3539784	3539400	0	0
T6	509316	509292	0	0
T10	133404	133040	0	0
T11	1165856	1165824	0	0
T12	924396	924108	0	0
T13	135396	135004	0	0
T15	300576	300220	0	0
T22	268364	268116	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T6,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T15,T13
1	0	1	Covered	T1,T28,T29
1	1	0	Covered	T13,T24,T20
1	1	1	Covered	T10,T15,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T15,T13,T24
0	1	Covered	T15,T29,T31
1	0	Covered	T10,T5,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T15,T13,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T10,T5,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T13
1	0	Not Covered
1	1	Covered	T15,T29,T31

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T11,T15
1	Covered	T1,T10,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T16,T21,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T10,T11
1	Covered	T6,T15,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T11,T28,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T22,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T10,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T6,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T6,T10
Phase1St	198	Covered	T1,T6,T10
Phase2St	215	Covered	T1,T6,T10
Phase3St	233	Covered	T1,T6,T10
TerminalSt	249	Covered	T1,T6,T10
TimeoutSt	159	Covered	T10,T15,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T6,T10
IdleSt->TimeoutSt	159	Covered	T10,T15,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T30,T31
Phase0St->Phase1St	198	Covered	T1,T6,T10
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T5,T26,T40
Phase1St->Phase2St	215	Covered	T1,T6,T10
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T25,T32,T85
Phase2St->Phase3St	233	Covered	T1,T6,T10
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T10,T85,T86
Phase3St->TerminalSt	249	Covered	T1,T6,T10
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T15,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T24,T69
TimeoutSt->Phase0St	172	Covered	T10,T15,T5

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T15,T13,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T24,T69
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T31,T32
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T6,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T6,T10,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T26,T40
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T6,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T6,T10,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T25,T32,T85
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T6,T10
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T10,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T10,T85,T86
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T6,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T10,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T15,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T6,T10
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	671291291	209	0	0
CheckAccumTrig0_A	671291291	895	0	0
CheckAccumTrig1_A	671291291	50	0	0
CheckClr_A	671291291	477	0	0
CheckEn_A	671148474	258052543	0	0
CheckPhase0_A	671291291	1000	0	0
CheckPhase1_A	671291291	976	0	0
CheckPhase2_A	671291291	953	0	0
CheckPhase3_A	671291291	929	0	0
CheckTimeout0_A	671291291	2210	0	0
CheckTimeoutSt1_A	671291291	188373	0	0
CheckTimeoutSt2_A	671291291	2086	0	0
CheckTimeoutStTrig_A	671291291	73	0	0
ErrorStAllEscAsserted_A	671291291	1135	0	0
ErrorStIsTerminal_A	671291291	925	0	0
EscStateOut_A	671147307	671077984	0	0
u_state_regs_A	671291291	671132237	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	209	0	0
T7	20583	26	0	0
T8	0	31	0	0
T9	0	21	0	0
T19	884735	0	0	0
T30	107992	0	0	0
T31	55435	0	0	0
T33	0	75	0	0
T34	0	56	0	0
T35	48956	0	0	0
T36	24195	0	0	0
T37	364950	0	0	0
T38	334694	0	0	0
T39	89512	0	0	0
T40	33024	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	895	0	0
T1	4016	1	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T6	127329	1	0	0
T10	33351	3	0	0
T11	291464	1	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	0	1	0	0
T15	75144	1	0	0
T16	0	1	0	0
T20	0	1	0	0
T22	67091	1	0	0
T28	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	50	0	0
T5	0	2	0	0
T10	33351	2	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	0	0	0
T15	75144	0	0	0
T20	214183	0	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T26	0	1	0	0
T28	378748	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T44	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T52	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	477	0	0
T5	0	6	0	0
T10	33351	4	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	0	0	0
T15	75144	1	0	0
T20	214183	0	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	5	0	0
T26	0	4	0	0
T28	378748	0	0	0
T29	0	8	0	0
T30	0	1	0	0
T31	0	1	0	0
T43	0	6	0	0
T64	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671148474	258052543	0	0
T1	4016	3220	0	0
T2	87757	1354	0	0
T3	884946	884849	0	0
T6	127329	609	0	0
T10	33351	582	0	0
T11	291464	2072	0	0
T12	231099	231026	0	0
T13	33849	3644	0	0
T15	75144	5586	0	0
T22	67091	7630	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	1000	0	0
T1	4016	1	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T6	127329	1	0	0
T10	33351	5	0	0
T11	291464	1	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	0	1	0	0
T15	75144	2	0	0
T16	0	1	0	0
T20	0	1	0	0
T22	67091	1	0	0
T28	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	976	0	0
T1	4016	1	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T6	127329	1	0	0
T10	33351	5	0	0
T11	291464	1	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	0	1	0	0
T15	75144	2	0	0
T16	0	1	0	0
T20	0	1	0	0
T22	67091	1	0	0
T28	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	953	0	0
T1	4016	1	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T6	127329	1	0	0
T10	33351	5	0	0
T11	291464	1	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	0	1	0	0
T15	75144	2	0	0
T16	0	1	0	0
T20	0	1	0	0
T22	67091	1	0	0
T28	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	929	0	0
T1	4016	1	0	0
T2	87757	0	0	0
T3	884946	0	0	0
T6	127329	1	0	0
T10	33351	4	0	0
T11	291464	1	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	0	1	0	0
T15	75144	2	0	0
T16	0	1	0	0
T20	0	1	0	0
T22	67091	1	0	0
T28	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	2210	0	0
T5	0	6	0	0
T10	33351	2	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	6	0	0
T14	328329	0	0	0
T15	75144	1	0	0
T20	214183	0	0	0
T22	67091	0	0	0
T24	84266	1	0	0
T25	0	1	0	0
T26	0	10	0	0
T28	378748	0	0	0
T29	0	12	0	0
T63	0	2	0	0
T69	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	188373	0	0
T5	0	307	0	0
T12	231099	0	0	0
T13	33849	778	0	0
T14	328329	0	0	0
T15	75144	41	0	0
T16	170928	0	0	0
T20	214183	0	0	0
T22	67091	0	0	0
T24	84266	114	0	0
T25	0	219	0	0
T26	0	850	0	0
T28	378748	0	0	0
T29	0	3243	0	0
T30	0	221	0	0
T41	330723	0	0	0
T63	0	110	0	0
T69	0	730	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	2086	0	0
T5	0	4	0	0
T13	33849	6	0	0
T14	328329	0	0	0
T16	170928	0	0	0
T17	122384	0	0	0
T20	214183	0	0	0
T22	67091	0	0	0
T24	84266	1	0	0
T25	0	1	0	0
T26	0	9	0	0
T28	378748	0	0	0
T29	0	10	0	0
T30	0	1	0	0
T40	0	1	0	0
T41	330723	0	0	0
T63	0	2	0	0
T69	76986	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	73	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	0	0	0
T15	75144	1	0	0
T16	170928	0	0	0
T20	214183	0	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T28	378748	0	0	0
T29	0	1	0	0
T31	0	2	0	0
T32	0	5	0	0
T41	330723	0	0	0
T48	0	7	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	1135	0	0
T7	20583	156	0	0
T8	0	156	0	0
T9	0	177	0	0
T19	884735	0	0	0
T30	107992	0	0	0
T31	55435	0	0	0
T33	0	322	0	0
T34	0	324	0	0
T35	48956	0	0	0
T36	24195	0	0	0
T37	364950	0	0	0
T38	334694	0	0	0
T39	89512	0	0	0
T40	33024	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	925	0	0
T7	20583	126	0	0
T8	0	126	0	0
T9	0	147	0	0
T19	884735	0	0	0
T30	107992	0	0	0
T31	55435	0	0	0
T33	0	262	0	0
T34	0	264	0	0
T35	48956	0	0	0
T36	24195	0	0	0
T37	364950	0	0	0
T38	334694	0	0	0
T39	89512	0	0	0
T40	33024	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671147307	671077984	0	0
T1	4016	3928	0	0
T2	87757	87590	0	0
T3	884946	884850	0	0
T6	127329	127323	0	0
T10	33351	33260	0	0
T11	291464	291456	0	0
T12	231099	231027	0	0
T13	33849	33751	0	0
T15	75144	75055	0	0
T22	67091	67029	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	671132237	0	0
T1	4016	3928	0	0
T2	87757	87590	0	0
T3	884946	884850	0	0
T6	127329	127323	0	0
T10	33351	33260	0	0
T11	291464	291456	0	0
T12	231099	231027	0	0
T13	33849	33751	0	0
T15	75144	75055	0	0
T22	67091	67029	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T10,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T13,T24
1	0	1	Covered	T3,T11,T12
1	1	0	Covered	T13,T20,T69
1	1	1	Covered	T13,T24,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T24,T20
0	1	Covered	T5,T25,T42
1	0	Covered	T26,T45,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T24,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T45,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T24,T20
1	0	Not Covered
1	1	Covered	T5,T25,T42

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T14,T28
1	Covered	T10,T12,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T12,T21
1	Covered	T14,T28,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T12,T14
1	Covered	T29,T30,T87

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T12,T14
1	Covered	T10,T21,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T12,T14,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T10,T12,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T10,T12,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T10,T12,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T10,T12,T14
Phase1St	198	Covered	T10,T12,T14
Phase2St	215	Covered	T10,T12,T14
Phase3St	233	Covered	T10,T12,T14
TerminalSt	249	Covered	T10,T12,T14
TimeoutSt	159	Covered	T13,T24,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T10,T12,T14
IdleSt->TimeoutSt	159	Covered	T13,T24,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T88,T89,T79
Phase0St->Phase1St	198	Covered	T10,T12,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T5,T25,T29
Phase1St->Phase2St	215	Covered	T10,T12,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T90,T53,T91
Phase2St->Phase3St	233	Covered	T10,T12,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T92,T93,T94
Phase3St->TerminalSt	249	Covered	T10,T12,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T21,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T24,T20
TimeoutSt->Phase0St	172	Covered	T5,T25,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T24,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T25,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T24,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T24,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T88,T89,T79
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T10,T12,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T12,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T25,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T10,T12,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T12,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T90,T53,T91
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T10,T12,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T12,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T92,T93,T94
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T10,T12,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T12,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T21,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T12,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	671291291	228	0	0
CheckAccumTrig0_A	671291291	459	0	0
CheckAccumTrig1_A	671291291	18	0	0
CheckClr_A	671291291	198	0	0
CheckEn_A	671148474	291570933	0	0
CheckPhase0_A	671291291	542	0	0
CheckPhase1_A	671291291	529	0	0
CheckPhase2_A	671291291	518	0	0
CheckPhase3_A	671291291	512	0	0
CheckTimeout0_A	671291291	1251	0	0
CheckTimeoutSt1_A	671291291	123726	0	0
CheckTimeoutSt2_A	671291291	1154	0	0
CheckTimeoutStTrig_A	671291291	77	0	0
ErrorStAllEscAsserted_A	671291291	1115	0	0
ErrorStIsTerminal_A	671291291	905	0	0
EscStateOut_A	671147307	671077984	0	0
u_state_regs_A	671291291	671132237	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	228	0	0
T7	20583	15	0	0
T8	0	43	0	0
T9	0	42	0	0
T19	884735	0	0	0
T30	107992	0	0	0
T31	55435	0	0	0
T33	0	57	0	0
T34	0	71	0	0
T35	48956	0	0	0
T36	24195	0	0	0
T37	364950	0	0	0
T38	334694	0	0	0
T39	89512	0	0	0
T40	33024	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	459	0	0
T5	0	11	0	0
T10	33351	2	0	0
T11	291464	0	0	0
T12	231099	1	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T20	214183	0	0	0
T21	0	2	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T26	0	6	0	0
T28	378748	1	0	0
T29	0	7	0	0
T42	0	1	0	0
T43	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	18	0	0
T18	126420	0	0	0
T26	134633	1	0	0
T29	368096	0	0	0
T42	30457	0	0	0
T43	166124	0	0	0
T45	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	93069	0	0	0
T60	15698	0	0	0
T61	3360	0	0	0
T62	81590	0	0	0
T63	21468	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	198	0	0
T5	0	9	0	0
T10	33351	1	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	0	0	0
T15	75144	0	0	0
T20	214183	0	0	0
T21	0	1	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	4	0	0
T26	0	4	0	0
T28	378748	0	0	0
T29	0	4	0	0
T30	0	2	0	0
T32	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671148474	291570933	0	0
T1	4016	3230	0	0
T2	87757	1358	0	0
T3	884946	819369	0	0
T6	127329	127323	0	0
T10	33351	1285	0	0
T11	291464	291083	0	0
T12	231099	8504	0	0
T13	33849	2523	0	0
T15	75144	75054	0	0
T22	67091	67028	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	542	0	0
T5	0	12	0	0
T10	33351	2	0	0
T11	291464	0	0	0
T12	231099	1	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T20	214183	0	0	0
T21	0	2	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	5	0	0
T26	0	7	0	0
T28	378748	1	0	0
T42	0	2	0	0
T43	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	529	0	0
T5	0	11	0	0
T10	33351	2	0	0
T11	291464	0	0	0
T12	231099	1	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T20	214183	0	0	0
T21	0	2	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	4	0	0
T26	0	7	0	0
T28	378748	1	0	0
T42	0	2	0	0
T43	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	518	0	0
T5	0	11	0	0
T10	33351	2	0	0
T11	291464	0	0	0
T12	231099	1	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T20	214183	0	0	0
T21	0	2	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	4	0	0
T26	0	7	0	0
T28	378748	1	0	0
T42	0	2	0	0
T43	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	512	0	0
T5	0	11	0	0
T10	33351	2	0	0
T11	291464	0	0	0
T12	231099	1	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T20	214183	0	0	0
T21	0	2	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	4	0	0
T26	0	7	0	0
T28	378748	1	0	0
T42	0	2	0	0
T43	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	1251	0	0
T5	0	15	0	0
T13	33849	12	0	0
T14	328329	0	0	0
T16	170928	0	0	0
T17	122384	0	0	0
T20	214183	1	0	0
T22	67091	0	0	0
T24	84266	6	0	0
T25	0	8	0	0
T26	0	5	0	0
T28	378748	0	0	0
T41	330723	0	0	0
T42	0	2	0	0
T59	0	6	0	0
T69	76986	0	0	0
T70	0	5	0	0
T71	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	123726	0	0
T5	0	1235	0	0
T13	33849	1287	0	0
T14	328329	0	0	0
T16	170928	0	0	0
T17	122384	0	0	0
T20	214183	72	0	0
T22	67091	0	0	0
T24	84266	752	0	0
T25	0	889	0	0
T26	0	259	0	0
T28	378748	0	0	0
T41	330723	0	0	0
T42	0	681	0	0
T59	0	1287	0	0
T69	76986	0	0	0
T70	0	769	0	0
T71	0	612	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	1154	0	0
T5	0	14	0	0
T13	33849	12	0	0
T14	328329	0	0	0
T16	170928	0	0	0
T17	122384	0	0	0
T20	214183	1	0	0
T22	67091	0	0	0
T24	84266	6	0	0
T25	0	3	0	0
T26	0	4	0	0
T28	378748	0	0	0
T41	330723	0	0	0
T42	0	1	0	0
T59	0	6	0	0
T69	76986	0	0	0
T70	0	5	0	0
T71	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	77	0	0
T5	976652	1	0	0
T25	974423	5	0	0
T26	134633	0	0	0
T29	368096	3	0	0
T42	30457	1	0	0
T43	166124	0	0	0
T46	0	2	0	0
T48	0	1	0	0
T59	93069	0	0	0
T71	8749	0	0	0
T73	43222	0	0	0
T74	4418	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T79	0	3	0	0
T82	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	1115	0	0
T7	20583	128	0	0
T8	0	180	0	0
T9	0	167	0	0
T19	884735	0	0	0
T30	107992	0	0	0
T31	55435	0	0	0
T33	0	318	0	0
T34	0	322	0	0
T35	48956	0	0	0
T36	24195	0	0	0
T37	364950	0	0	0
T38	334694	0	0	0
T39	89512	0	0	0
T40	33024	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	905	0	0
T7	20583	98	0	0
T8	0	150	0	0
T9	0	137	0	0
T19	884735	0	0	0
T30	107992	0	0	0
T31	55435	0	0	0
T33	0	258	0	0
T34	0	262	0	0
T35	48956	0	0	0
T36	24195	0	0	0
T37	364950	0	0	0
T38	334694	0	0	0
T39	89512	0	0	0
T40	33024	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671147307	671077984	0	0
T1	4016	3928	0	0
T2	87757	87590	0	0
T3	884946	884850	0	0
T6	127329	127323	0	0
T10	33351	33260	0	0
T11	291464	291456	0	0
T12	231099	231027	0	0
T13	33849	33751	0	0
T15	75144	75055	0	0
T22	67091	67029	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	671132237	0	0
T1	4016	3928	0	0
T2	87757	87590	0	0
T3	884946	884850	0	0
T6	127329	127323	0	0
T10	33351	33260	0	0
T11	291464	291456	0	0
T12	231099	231027	0	0
T13	33849	33751	0	0
T15	75144	75055	0	0
T22	67091	67029	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T10,T14
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T10,T14

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T10,T14

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T20,T69
1	0	1	Covered	T6,T28,T41
1	1	0	Covered	T13,T24,T69
1	1	1	Covered	T69,T70,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T69,T70,T5
0	1	Covered	T29,T60,T32
1	0	Covered	T26,T29,T72

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T69,T70,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T29,T72

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T69,T70,T5
1	0	Not Covered
1	1	Covered	T29,T60,T32

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T10,T20
1	Covered	T14,T26,T29

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T14,T20
1	Covered	T6,T41,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T10,T14
1	Covered	T5,T29,T32

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T14,T41
1	Covered	T10,T20,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T10,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T14,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T20,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T6,T10,T41

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T6,T10,T14
Phase1St	198	Covered	T6,T10,T14
Phase2St	215	Covered	T6,T10,T14
Phase3St	233	Covered	T6,T10,T14
TerminalSt	249	Covered	T6,T10,T14
TimeoutSt	159	Covered	T69,T70,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T6,T10,T14
IdleSt->TimeoutSt	159	Covered	T69,T70,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T25,T47,T95
Phase0St->Phase1St	198	Covered	T6,T10,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T96,T81,T97
Phase1St->Phase2St	215	Covered	T6,T10,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T98,T99
Phase2St->Phase3St	233	Covered	T6,T10,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T48,T100,T90
Phase3St->TerminalSt	249	Covered	T6,T10,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T21,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T69,T70,T5
TimeoutSt->Phase0St	172	Covered	T26,T29,T60

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T69,T70,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T29,T60
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T69,T70,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T69,T70,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T47,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T6,T10,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T6,T10,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T96,T81,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T6,T10,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T6,T10,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T98,T99
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T6,T10,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T10,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T48,T100,T90
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T6,T10,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T10,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T21,T25
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T10,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	671291291	198	0	0
CheckAccumTrig0_A	671291291	480	0	0
CheckAccumTrig1_A	671291291	24	0	0
CheckClr_A	671291291	192	0	0
CheckEn_A	671148474	290421465	0	0
CheckPhase0_A	671291291	548	0	0
CheckPhase1_A	671291291	542	0	0
CheckPhase2_A	671291291	531	0	0
CheckPhase3_A	671291291	522	0	0
CheckTimeout0_A	671291291	1323	0	0
CheckTimeoutSt1_A	671291291	141076	0	0
CheckTimeoutSt2_A	671291291	1242	0	0
CheckTimeoutStTrig_A	671291291	56	0	0
ErrorStAllEscAsserted_A	671291291	1114	0	0
ErrorStIsTerminal_A	671291291	904	0	0
EscStateOut_A	671147307	671077984	0	0
u_state_regs_A	671291291	671132237	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	198	0	0
T7	20583	48	0	0
T8	0	23	0	0
T9	0	17	0	0
T19	884735	0	0	0
T30	107992	0	0	0
T31	55435	0	0	0
T33	0	49	0	0
T34	0	61	0	0
T35	48956	0	0	0
T36	24195	0	0	0
T37	364950	0	0	0
T38	334694	0	0	0
T39	89512	0	0	0
T40	33024	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	480	0	0
T5	0	2	0	0
T6	127329	1	0	0
T10	33351	6	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T16	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	6	0	0
T26	0	3	0	0
T28	378748	0	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	24	0	0
T18	126420	0	0	0
T26	134633	1	0	0
T29	368096	1	0	0
T32	0	1	0	0
T42	30457	0	0	0
T43	166124	0	0	0
T48	0	1	0	0
T59	93069	0	0	0
T60	15698	0	0	0
T61	3360	0	0	0
T62	81590	0	0	0
T63	21468	0	0	0
T66	0	1	0	0
T72	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	192	0	0
T10	33351	5	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	0	0	0
T15	75144	0	0	0
T20	214183	0	0	0
T21	0	1	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	5	0	0
T26	0	1	0	0
T28	378748	0	0	0
T29	0	1	0	0
T32	0	3	0	0
T38	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671148474	290421465	0	0
T1	4016	3265	0	0
T2	87757	1366	0	0
T3	884946	826965	0	0
T6	127329	621	0	0
T10	33351	594	0	0
T11	291464	291456	0	0
T12	231099	231026	0	0
T13	33849	33750	0	0
T15	75144	75054	0	0
T22	67091	67028	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	548	0	0
T5	0	2	0	0
T6	127329	1	0	0
T10	33351	6	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T16	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	5	0	0
T26	0	4	0	0
T28	378748	0	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	542	0	0
T5	0	2	0	0
T6	127329	1	0	0
T10	33351	6	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T16	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	5	0	0
T26	0	4	0	0
T28	378748	0	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	531	0	0
T5	0	2	0	0
T6	127329	1	0	0
T10	33351	6	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T16	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	5	0	0
T26	0	4	0	0
T28	378748	0	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	522	0	0
T5	0	2	0	0
T6	127329	1	0	0
T10	33351	6	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T16	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	5	0	0
T26	0	4	0	0
T28	378748	0	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	1323	0	0
T4	18107	0	0	0
T5	976652	2	0	0
T17	122384	0	0	0
T21	195375	0	0	0
T25	974423	7	0	0
T26	0	9	0	0
T29	0	71	0	0
T59	0	5	0	0
T60	0	3	0	0
T63	0	2	0	0
T69	76986	8	0	0
T70	88170	2	0	0
T71	8749	0	0	0
T72	0	1	0	0
T73	43222	0	0	0
T74	4418	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	141076	0	0
T4	18107	0	0	0
T5	976652	131	0	0
T17	122384	0	0	0
T21	195375	0	0	0
T25	974423	1319	0	0
T26	0	1243	0	0
T29	0	8384	0	0
T59	0	1011	0	0
T60	0	185	0	0
T63	0	120	0	0
T69	76986	1042	0	0
T70	88170	338	0	0
T71	8749	0	0	0
T72	0	7	0	0
T73	43222	0	0	0
T74	4418	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	1242	0	0
T4	18107	0	0	0
T5	976652	2	0	0
T17	122384	0	0	0
T21	195375	0	0	0
T25	974423	7	0	0
T26	0	8	0	0
T29	0	69	0	0
T35	0	2	0	0
T59	0	5	0	0
T60	0	2	0	0
T63	0	2	0	0
T69	76986	8	0	0
T70	88170	2	0	0
T71	8749	0	0	0
T73	43222	0	0	0
T74	4418	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	56	0	0
T18	126420	0	0	0
T29	368096	1	0	0
T32	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T60	15698	1	0	0
T61	3360	0	0	0
T62	81590	0	0	0
T63	21468	0	0	0
T64	321394	0	0	0
T65	113715	0	0	0
T67	0	1	0	0
T72	14402	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	7988	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	1114	0	0
T7	20583	143	0	0
T8	0	175	0	0
T9	0	183	0	0
T19	884735	0	0	0
T30	107992	0	0	0
T31	55435	0	0	0
T33	0	286	0	0
T34	0	327	0	0
T35	48956	0	0	0
T36	24195	0	0	0
T37	364950	0	0	0
T38	334694	0	0	0
T39	89512	0	0	0
T40	33024	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	904	0	0
T7	20583	113	0	0
T8	0	145	0	0
T9	0	153	0	0
T19	884735	0	0	0
T30	107992	0	0	0
T31	55435	0	0	0
T33	0	226	0	0
T34	0	267	0	0
T35	48956	0	0	0
T36	24195	0	0	0
T37	364950	0	0	0
T38	334694	0	0	0
T39	89512	0	0	0
T40	33024	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671147307	671077984	0	0
T1	4016	3928	0	0
T2	87757	87590	0	0
T3	884946	884850	0	0
T6	127329	127323	0	0
T10	33351	33260	0	0
T11	291464	291456	0	0
T12	231099	231027	0	0
T13	33849	33751	0	0
T15	75144	75055	0	0
T22	67091	67029	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	671132237	0	0
T1	4016	3928	0	0
T2	87757	87590	0	0
T3	884946	884850	0	0
T6	127329	127323	0	0
T10	33351	33260	0	0
T11	291464	291456	0	0
T12	231099	231027	0	0
T13	33849	33751	0	0
T15	75144	75055	0	0
T22	67091	67029	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T10,T11,T14
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T11,T14

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T23
1	1	1	Covered	T10,T11,T14

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T24,T20
1	0	1	Covered	T11,T14,T28
1	1	0	Covered	T13,T24,T69
1	1	1	Covered	T69,T70,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T69,T70,T5
0	1	Covered	T5,T42,T63
1	0	Covered	T5,T26,T46

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T69,T70,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T26,T46

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T69,T70,T5
1	0	Covered	T27
1	1	Covered	T5,T42,T63

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T11,T14
1	Covered	T5,T29,T63

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T11,T14
1	Covered	T17,T21,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T20,T17
1	Covered	T11,T14,T28

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T28,T17
1	Covered	T10,T20,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T10,T11,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T14,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T28,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T10,T28,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T10,T11,T14
Phase1St	198	Covered	T10,T11,T14
Phase2St	215	Covered	T10,T11,T14
Phase3St	233	Covered	T10,T11,T28
TerminalSt	249	Covered	T10,T11,T28
TimeoutSt	159	Covered	T69,T70,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T10,T11,T14
IdleSt->TimeoutSt	159	Covered	T69,T70,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T95,T99,T107
Phase0St->Phase1St	198	Covered	T10,T11,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T65,T108,T109
Phase1St->Phase2St	215	Covered	T10,T11,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T14,T110,T84
Phase2St->Phase3St	233	Covered	T10,T11,T28
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T10,T5,T25
Phase3St->TerminalSt	249	Covered	T10,T11,T28
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T5,T26
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T69,T70,T5
TimeoutSt->Phase0St	172	Covered	T5,T26,T42

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T69,T70,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T26,T42
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T69,T70,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T69,T70,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T99,T107,T54
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T10,T11,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T11,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T65,T108,T109
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T10,T11,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T11,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T110,T103
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T10,T11,T28
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T11,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T10,T5,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T10,T11,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T11,T28
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T5,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T11,T28
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	671291291	180	0	0
CheckAccumTrig0_A	671291291	522	0	0
CheckAccumTrig1_A	671291291	23	0	0
CheckClr_A	671291291	264	0	0
CheckEn_A	671148474	323935301	0	0
CheckPhase0_A	671291291	610	0	0
CheckPhase1_A	671291291	599	0	0
CheckPhase2_A	671291291	587	0	0
CheckPhase3_A	671291291	573	0	0
CheckTimeout0_A	671291291	1040	0	0
CheckTimeoutSt1_A	671291291	104546	0	0
CheckTimeoutSt2_A	671291291	941	0	0
CheckTimeoutStTrig_A	671291291	76	0	0
ErrorStAllEscAsserted_A	671291291	1122	0	0
ErrorStIsTerminal_A	671291291	912	0	0
EscStateOut_A	671147307	671077984	0	0
u_state_regs_A	671291291	671132237	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	180	0	0
T7	20583	26	0	0
T8	0	28	0	0
T9	0	32	0	0
T19	884735	0	0	0
T30	107992	0	0	0
T31	55435	0	0	0
T33	0	63	0	0
T34	0	31	0	0
T35	48956	0	0	0
T36	24195	0	0	0
T37	364950	0	0	0
T38	334694	0	0	0
T39	89512	0	0	0
T40	33024	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	522	0	0
T5	0	9	0	0
T10	33351	10	0	0
T11	291464	1	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T17	0	1	0	0
T20	214183	1	0	0
T21	0	1	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	1	0	0
T26	0	6	0	0
T28	378748	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	23	0	0
T5	976652	1	0	0
T25	974423	0	0	0
T26	134633	1	0	0
T29	368096	0	0	0
T42	30457	0	0	0
T43	166124	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T59	93069	0	0	0
T71	8749	0	0	0
T73	43222	0	0	0
T74	4418	0	0	0
T82	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	4	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	264	0	0
T5	0	8	0	0
T10	33351	9	0	0
T11	291464	0	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T20	214183	0	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	1	0	0
T26	0	4	0	0
T28	378748	0	0	0
T29	0	3	0	0
T32	0	5	0	0
T42	0	1	0	0
T65	0	2	0	0
T66	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671148474	323935301	0	0
T1	4016	3240	0	0
T2	87757	1362	0	0
T3	884946	884849	0	0
T6	127329	127323	0	0
T10	33351	590	0	0
T11	291464	5819	0	0
T12	231099	231026	0	0
T13	33849	33750	0	0
T15	75144	75054	0	0
T22	67091	67028	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	610	0	0
T5	0	11	0	0
T10	33351	10	0	0
T11	291464	1	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T17	0	1	0	0
T20	214183	1	0	0
T21	0	1	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	1	0	0
T26	0	7	0	0
T28	378748	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	599	0	0
T5	0	11	0	0
T10	33351	10	0	0
T11	291464	1	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	1	0	0
T15	75144	0	0	0
T17	0	1	0	0
T20	214183	1	0	0
T21	0	1	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	1	0	0
T26	0	7	0	0
T28	378748	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	587	0	0
T5	0	11	0	0
T10	33351	10	0	0
T11	291464	1	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	0	0	0
T15	75144	0	0	0
T17	0	1	0	0
T20	214183	1	0	0
T21	0	1	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T25	0	1	0	0
T26	0	7	0	0
T28	378748	1	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	573	0	0
T5	0	10	0	0
T10	33351	8	0	0
T11	291464	1	0	0
T12	231099	0	0	0
T13	33849	0	0	0
T14	328329	0	0	0
T15	75144	0	0	0
T17	0	1	0	0
T20	214183	1	0	0
T21	0	1	0	0
T22	67091	0	0	0
T24	84266	0	0	0
T26	0	7	0	0
T28	378748	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	1040	0	0
T4	18107	0	0	0
T5	976652	9	0	0
T17	122384	0	0	0
T21	195375	0	0	0
T25	974423	18	0	0
T26	0	9	0	0
T29	0	2	0	0
T35	0	5	0	0
T42	0	1	0	0
T63	0	1	0	0
T69	76986	1	0	0
T70	88170	1	0	0
T71	8749	0	0	0
T72	0	1	0	0
T73	43222	0	0	0
T74	4418	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	104546	0	0
T4	18107	0	0	0
T5	976652	506	0	0
T17	122384	0	0	0
T21	195375	0	0	0
T25	974423	2989	0	0
T26	0	1436	0	0
T29	0	159	0	0
T35	0	795	0	0
T42	0	562	0	0
T63	0	74	0	0
T69	76986	123	0	0
T70	88170	163	0	0
T71	8749	0	0	0
T72	0	551	0	0
T73	43222	0	0	0
T74	4418	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	941	0	0
T4	18107	0	0	0
T5	976652	7	0	0
T17	122384	0	0	0
T21	195375	0	0	0
T25	974423	18	0	0
T26	0	8	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	0	140	0	0
T35	0	5	0	0
T69	76986	1	0	0
T70	88170	1	0	0
T71	8749	0	0	0
T73	43222	0	0	0
T74	4418	0	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	76	0	0
T5	976652	1	0	0
T25	974423	0	0	0
T26	134633	0	0	0
T29	368096	0	0	0
T32	0	6	0	0
T39	0	1	0	0
T42	30457	1	0	0
T43	166124	0	0	0
T46	0	1	0	0
T59	93069	0	0	0
T63	0	1	0	0
T68	0	3	0	0
T71	8749	0	0	0
T72	0	1	0	0
T73	43222	0	0	0
T74	4418	0	0	0
T78	0	3	0	0
T110	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	1122	0	0
T7	20583	168	0	0
T8	0	143	0	0
T9	0	131	0	0
T19	884735	0	0	0
T30	107992	0	0	0
T31	55435	0	0	0
T33	0	327	0	0
T34	0	353	0	0
T35	48956	0	0	0
T36	24195	0	0	0
T37	364950	0	0	0
T38	334694	0	0	0
T39	89512	0	0	0
T40	33024	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	912	0	0
T7	20583	138	0	0
T8	0	113	0	0
T9	0	101	0	0
T19	884735	0	0	0
T30	107992	0	0	0
T31	55435	0	0	0
T33	0	267	0	0
T34	0	293	0	0
T35	48956	0	0	0
T36	24195	0	0	0
T37	364950	0	0	0
T38	334694	0	0	0
T39	89512	0	0	0
T40	33024	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671147307	671077984	0	0
T1	4016	3928	0	0
T2	87757	87590	0	0
T3	884946	884850	0	0
T6	127329	127323	0	0
T10	33351	33260	0	0
T11	291464	291456	0	0
T12	231099	231027	0	0
T13	33849	33751	0	0
T15	75144	75055	0	0
T22	67091	67029	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671291291	671132237	0	0
T1	4016	3928	0	0
T2	87757	87590	0	0
T3	884946	884850	0	0
T6	127329	127323	0	0
T10	33351	33260	0	0
T11	291464	291456	0	0
T12	231099	231027	0	0
T13	33849	33751	0	0
T15	75144	75055	0	0
T22	67091	67029	0	0