Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67240690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32505219

1

T1

3692

T2

2265

T3

2609

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15076232	1			T1	2433		T2	935		T3	1038
values[0x0]	41327632	1			T1	4086		T2	3209		T3	3641
values[0x1]	43342045	1			T1	4074		T2	3173		T3	3641

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57473642	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42272267

1

T1

4572

T2

2882

T3

3353

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	780818	1			T1	36		T2	28		T4	4733
valid_sources[0x01]	322718	1			T1	52		T2	29		T4	4923
valid_sources[0x02]	322108	1			T1	47		T2	30		T4	4733
valid_sources[0x03]	323696	1			T1	45		T2	22		T4	5068
valid_sources[0x04]	321660	1			T1	38		T2	24		T4	5023
valid_sources[0x05]	323343	1			T1	32		T2	21		T4	4886
valid_sources[0x06]	358538	1			T1	40		T2	32		T4	4982
valid_sources[0x07]	323157	1			T1	52		T2	23		T4	4959
valid_sources[0x08]	330825	1			T1	41		T2	23		T4	4721
valid_sources[0x09]	321941	1			T1	34		T2	32		T4	4789
valid_sources[0x0a]	324459	1			T1	29		T2	33		T4	4858
valid_sources[0x0b]	325774	1			T1	33		T2	42		T4	4724
valid_sources[0x0c]	335520	1			T1	44		T2	37		T4	4901
valid_sources[0x0d]	326412	1			T1	42		T2	37		T4	4995
valid_sources[0x0e]	358885	1			T1	45		T2	35		T4	4934
valid_sources[0x0f]	332719	1			T1	49		T2	27		T4	4812
valid_sources[0x10]	331094	1			T1	44		T2	41		T4	4861
valid_sources[0x11]	323355	1			T1	34		T2	26		T4	4865
valid_sources[0x12]	326872	1			T1	41		T2	32		T4	4828
valid_sources[0x13]	844395	1			T1	35		T2	33		T4	4880
valid_sources[0x14]	329514	1			T1	38		T2	26		T4	4851
valid_sources[0x15]	654142	1			T1	34		T2	22		T4	4947
valid_sources[0x16]	330559	1			T1	39		T2	34		T4	4778
valid_sources[0x17]	325072	1			T1	39		T2	28		T4	4877
valid_sources[0x18]	321579	1			T1	52		T2	26		T4	4934
valid_sources[0x19]	325330	1			T1	37		T2	28		T4	5040
valid_sources[0x1a]	324380	1			T1	42		T2	25		T4	4575
valid_sources[0x1b]	330669	1			T1	38		T2	29		T4	5075
valid_sources[0x1c]	332536	1			T1	42		T2	28		T4	4793
valid_sources[0x1d]	324189	1			T1	41		T2	38		T4	4548
valid_sources[0x1e]	326248	1			T1	45		T2	38		T4	4806
valid_sources[0x1f]	674757	1			T1	44		T2	36		T4	5032
valid_sources[0x20]	331059	1			T1	37		T2	28		T4	4870
valid_sources[0x21]	674101	1			T1	55		T2	24		T4	5024
valid_sources[0x22]	328121	1			T1	36		T2	20		T4	5029
valid_sources[0x23]	331993	1			T1	35		T2	40		T4	5111
valid_sources[0x24]	333055	1			T1	43		T2	28		T4	5021
valid_sources[0x25]	664188	1			T1	39		T2	30		T4	4839
valid_sources[0x26]	326612	1			T1	47		T2	28		T4	5030
valid_sources[0x27]	330013	1			T1	42		T2	27		T4	4637
valid_sources[0x28]	329881	1			T1	35		T2	35		T4	4911
valid_sources[0x29]	328050	1			T1	50		T2	25		T4	4932
valid_sources[0x2a]	622821	1			T1	47		T2	26		T4	4783
valid_sources[0x2b]	328199	1			T1	31		T2	25		T4	5095
valid_sources[0x2c]	335316	1			T1	32		T2	41		T4	4900
valid_sources[0x2d]	366474	1			T1	41		T2	25		T4	4829
valid_sources[0x2e]	322577	1			T1	49		T2	29		T4	4884
valid_sources[0x2f]	327128	1			T1	41		T2	25		T4	4730
valid_sources[0x30]	332592	1			T1	49		T2	26		T4	4870
valid_sources[0x31]	774040	1			T1	48		T2	28		T4	4673
valid_sources[0x32]	326289	1			T1	41		T2	29		T4	5004
valid_sources[0x33]	318749	1			T1	48		T2	26		T4	4998
valid_sources[0x34]	323277	1			T1	47		T2	31		T4	5036
valid_sources[0x35]	330673	1			T1	45		T2	26		T4	5041
valid_sources[0x36]	337110	1			T1	51		T2	17		T4	4948
valid_sources[0x37]	331265	1			T1	44		T2	29		T4	4882
valid_sources[0x38]	320082	1			T1	48		T2	34		T4	4926
valid_sources[0x39]	323438	1			T1	42		T2	31		T4	4870
valid_sources[0x3a]	327012	1			T1	43		T2	37		T4	4925
valid_sources[0x3b]	331350	1			T1	53		T2	32		T4	4752
valid_sources[0x3c]	778788	1			T1	36		T2	30		T4	4774
valid_sources[0x3d]	331449	1			T1	31		T2	24		T4	4689
valid_sources[0x3e]	325092	1			T1	34		T2	19		T4	5181
valid_sources[0x3f]	539670	1			T1	41		T2	32		T4	4902
valid_sources[0x40]	319526	1			T1	62		T2	20		T4	4896
valid_sources[0x41]	334224	1			T1	49		T2	27		T4	4756
valid_sources[0x42]	341013	1			T1	42		T2	22		T4	4824
valid_sources[0x43]	372307	1			T1	35		T2	29		T4	4989
valid_sources[0x44]	326639	1			T1	47		T2	37		T4	4788
valid_sources[0x45]	327291	1			T1	44		T2	21		T4	4831
valid_sources[0x46]	327832	1			T1	38		T2	24		T4	5012
valid_sources[0x47]	770249	1			T1	35		T2	31		T4	5192
valid_sources[0x48]	330505	1			T1	37		T2	38		T4	4805
valid_sources[0x49]	647357	1			T1	33		T2	23		T4	4771
valid_sources[0x4a]	326275	1			T1	38		T2	36		T4	4908
valid_sources[0x4b]	322048	1			T1	39		T2	25		T4	4561
valid_sources[0x4c]	330906	1			T1	50		T2	35		T4	4981
valid_sources[0x4d]	342367	1			T1	36		T2	34		T4	4810
valid_sources[0x4e]	582891	1			T1	41		T2	26		T4	4885
valid_sources[0x4f]	325717	1			T1	38		T2	33		T4	4866
valid_sources[0x50]	331515	1			T1	51		T2	27		T4	4869
valid_sources[0x51]	336608	1			T1	37		T2	20		T4	4846
valid_sources[0x52]	749127	1			T1	43		T2	36		T4	4926
valid_sources[0x53]	601006	1			T1	58		T2	36		T4	5076
valid_sources[0x54]	325197	1			T1	38		T2	26		T4	4676
valid_sources[0x55]	330904	1			T1	39		T2	35		T4	5067
valid_sources[0x56]	325241	1			T1	34		T2	28		T4	4760
valid_sources[0x57]	332422	1			T1	33		T2	25		T4	4780
valid_sources[0x58]	340881	1			T1	49		T2	27		T4	4999
valid_sources[0x59]	815508	1			T1	39		T2	14		T4	4954
valid_sources[0x5a]	346595	1			T1	48		T2	32		T4	5012
valid_sources[0x5b]	321649	1			T1	39		T2	17		T4	4792
valid_sources[0x5c]	344695	1			T1	40		T2	37		T4	4856
valid_sources[0x5d]	328734	1			T1	35		T2	23		T4	4872
valid_sources[0x5e]	795779	1			T1	39		T2	21		T4	4935
valid_sources[0x5f]	323467	1			T1	47		T2	30		T4	4923
valid_sources[0x60]	329179	1			T1	43		T2	35		T4	4664
valid_sources[0x61]	326983	1			T1	60		T2	26		T4	4947
valid_sources[0x62]	320943	1			T1	47		T2	32		T4	4940
valid_sources[0x63]	324043	1			T1	44		T2	26		T4	4925
valid_sources[0x64]	328485	1			T1	40		T2	35		T4	5009
valid_sources[0x65]	326634	1			T1	31		T2	42		T4	4994
valid_sources[0x66]	326369	1			T1	37		T2	25		T4	4560
valid_sources[0x67]	373497	1			T1	52		T2	21		T4	4767
valid_sources[0x68]	339583	1			T1	31		T2	26		T4	4610
valid_sources[0x69]	322052	1			T1	38		T2	27		T4	4907
valid_sources[0x6a]	328449	1			T1	37		T2	31		T4	4915
valid_sources[0x6b]	531720	1			T1	55		T2	28		T4	4788
valid_sources[0x6c]	330599	1			T1	52		T2	25		T4	4791
valid_sources[0x6d]	321085	1			T1	43		T2	28		T4	4873
valid_sources[0x6e]	332768	1			T1	37		T2	23		T4	4858
valid_sources[0x6f]	330812	1			T1	43		T2	26		T4	4665
valid_sources[0x70]	331142	1			T1	43		T2	39		T4	5061
valid_sources[0x71]	322590	1			T1	41		T2	30		T4	4697
valid_sources[0x72]	329789	1			T1	42		T2	37		T4	4902
valid_sources[0x73]	331711	1			T1	40		T2	31		T4	5006
valid_sources[0x74]	325639	1			T1	34		T2	27		T4	4935
valid_sources[0x75]	324494	1			T1	42		T2	21		T4	4943
valid_sources[0x76]	335682	1			T1	32		T2	24		T4	4878
valid_sources[0x77]	325777	1			T1	41		T2	25		T4	4915
valid_sources[0x78]	329392	1			T1	49		T2	23		T4	4784
valid_sources[0x79]	770753	1			T1	36		T2	22		T4	4906
valid_sources[0x7a]	328029	1			T1	51		T2	27		T4	4921
valid_sources[0x7b]	328441	1			T1	41		T2	38		T4	4974
valid_sources[0x7c]	324813	1			T1	44		T2	18		T4	5056
valid_sources[0x7d]	327534	1			T1	32		T2	30		T4	4928
valid_sources[0x7e]	339796	1			T1	43		T2	31		T4	4912
valid_sources[0x7f]	335324	1			T1	47		T2	29		T4	5088
valid_sources[0x80]	323259	1			T1	34		T2	18		T4	5015

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7470446

1

T1

1191

T2

445

T3

516

values[0x0]

all_enables

biggest_size

15804649

1

T1

1595

T2

1171

T3

1341

values[0x1]

all_enables

biggest_size

9230124

1

T1

906

T2

649

T3

752