Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T47,T198,T199
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15308	0	0
DisabledNoTrigBkwd_A	2147483647	826219	0	0
DisabledNoTrigFwd_A	2147483647	1484862827	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15308	0	0
T9	20546	0	0	0
T16	763504	0	0	0
T17	299418	0	0	0
T18	108152	0	0	0
T19	104225	0	0	0
T26	445387	0	0	0
T47	4592	1029	0	0
T55	840906	0	0	0
T77	79764	0	0	0
T78	86848	0	0	0
T85	257223	0	0	0
T180	10934	0	0	0
T181	946475	0	0	0
T182	272251	0	0	0
T198	0	1826	0	0
T199	2711	558	0	0
T200	0	212	0	0
T201	3984	473	0	0
T202	0	947	0	0
T203	0	1623	0	0
T204	0	816	0	0
T205	0	426	0	0
T206	0	609	0	0
T207	0	837	0	0
T208	0	279	0	0
T209	0	343	0	0
T210	0	1311	0	0
T211	0	599	0	0
T212	0	497	0	0
T213	0	729	0	0
T214	0	352	0	0
T215	0	705	0	0
T216	0	1137	0	0
T217	170997	0	0	0
T218	34898	0	0	0
T219	608991	0	0	0
T220	11333	0	0	0
T221	29274	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	826219	0	0
T1	973479	10	0	0
T2	195162	78	0	0
T3	154752	39	0	0
T4	1875564	8321	0	0
T5	115632	0	0	0
T6	0	173	0	0
T7	2779292	2786	0	0
T8	948068	0	0	0
T12	343536	0	0	0
T13	1857272	588	0	0
T14	6128	0	0	0
T16	0	16	0	0
T17	0	25	0	0
T20	158064	33	0	0
T24	0	252	0	0
T26	0	1491	0	0
T41	21658	6	0	0
T42	0	25	0	0
T43	0	229	0	0
T44	0	38	0	0
T45	0	503	0	0
T46	0	24	0	0
T47	0	12	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1484862827	0	0
T1	3893916	1966821	0	0
T2	260216	134114	0	0
T3	154752	105913	0	0
T4	1875564	1174649	0	0
T7	2779292	1391472	0	0
T8	948068	242040	0	0
T12	343536	229852	0	0
T13	1857272	500953	0	0
T14	6128	4893	0	0
T20	158064	127206	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T204
1	1	Covered	T3,T4,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	680599942	1289	0	0
DisabledNoTrigBkwd_A	680599942	215146	0	0
DisabledNoTrigFwd_A	680599942	371842830	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1289	0	0
T55	840906	0	0	0
T180	10934	0	0	0
T181	946475	0	0	0
T182	272251	0	0	0
T201	3984	473	0	0
T204	0	816	0	0
T217	170997	0	0	0
T218	34898	0	0	0
T219	608991	0	0	0
T220	11333	0	0	0
T221	29274	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	215146	0	0
T3	38688	4	0	0
T4	468891	2411	0	0
T5	38544	0	0	0
T6	0	4	0	0
T7	694823	1770	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T24	0	252	0	0
T41	21658	6	0	0
T42	0	25	0	0
T44	0	38	0	0
T45	0	191	0	0
T46	0	24	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	371842830	0	0
T1	973479	106263	0	0
T2	65054	64970	0	0
T3	38688	34109	0	0
T4	468891	288908	0	0
T7	694823	2027	0	0
T8	237017	587	0	0
T12	85884	80436	0	0
T13	464318	451284	0	0
T14	1532	582	0	0
T20	39516	37448	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T47,T198,T205
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	680599942	4521	0	0
DisabledNoTrigBkwd_A	680599942	214209	0	0
DisabledNoTrigFwd_A	680599942	350416769	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	4521	0	0
T9	20546	0	0	0
T16	763504	0	0	0
T17	299418	0	0	0
T18	108152	0	0	0
T19	104225	0	0	0
T26	445387	0	0	0
T47	4592	1029	0	0
T77	79764	0	0	0
T78	86848	0	0	0
T85	257223	0	0	0
T198	0	1826	0	0
T205	0	426	0	0
T206	0	609	0	0
T208	0	279	0	0
T214	0	352	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	214209	0	0
T2	65054	34	0	0
T3	38688	33	0	0
T4	468891	2697	0	0
T5	38544	0	0	0
T6	0	89	0	0
T7	694823	1014	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	73	0	0
T14	1532	0	0	0
T16	0	11	0	0
T20	39516	0	0	0
T26	0	300	0	0
T45	0	229	0	0
T47	0	12	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	350416769	0	0
T1	973479	810741	0	0
T2	65054	2150	0	0
T3	38688	7097	0	0
T4	468891	293377	0	0
T7	694823	1008	0	0
T8	237017	3932	0	0
T12	85884	8439	0	0
T13	464318	16958	0	0
T14	1532	1437	0	0
T20	39516	39459	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T202,T203
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	680599942	6304	0	0
DisabledNoTrigBkwd_A	680599942	198133	0	0
DisabledNoTrigFwd_A	680599942	375662992	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	6304	0	0
T51	10753	0	0	0
T82	31174	0	0	0
T199	2711	558	0	0
T202	0	947	0	0
T203	0	1623	0	0
T207	0	837	0	0
T212	0	497	0	0
T215	0	705	0	0
T216	0	1137	0	0
T222	96835	0	0	0
T223	687901	0	0	0
T224	108682	0	0	0
T225	53992	0	0	0
T226	288196	0	0	0
T227	351196	0	0	0
T228	324046	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	198133	0	0
T2	65054	44	0	0
T3	38688	2	0	0
T4	468891	1589	0	0
T5	38544	0	0	0
T6	0	76	0	0
T7	694823	2	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	274	0	0
T14	1532	0	0	0
T20	39516	7	0	0
T26	0	238	0	0
T43	0	207	0	0
T45	0	47	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	375662992	0	0
T1	973479	973415	0	0
T2	65054	5734	0	0
T3	38688	29299	0	0
T4	468891	244983	0	0
T7	694823	693707	0	0
T8	237017	236922	0	0
T12	85884	85802	0	0
T13	464318	15835	0	0
T14	1532	1437	0	0
T20	39516	34813	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T209,T210
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	680599942	3194	0	0
DisabledNoTrigBkwd_A	680599942	198731	0	0
DisabledNoTrigFwd_A	680599942	386940236	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	3194	0	0
T53	75897	0	0	0
T86	31908	0	0	0
T117	419094	0	0	0
T200	2421	212	0	0
T209	0	343	0	0
T210	0	1311	0	0
T211	0	599	0	0
T213	0	729	0	0
T229	118426	0	0	0
T230	12747	0	0	0
T231	105618	0	0	0
T232	962353	0	0	0
T233	36539	0	0	0
T234	18125	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	198731	0	0
T1	973479	10	0	0
T2	65054	0	0	0
T3	38688	0	0	0
T4	468891	1624	0	0
T6	0	4	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	241	0	0
T14	1532	0	0	0
T16	0	5	0	0
T17	0	25	0	0
T20	39516	26	0	0
T26	0	953	0	0
T43	0	22	0	0
T45	0	36	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	386940236	0	0
T1	973479	76402	0	0
T2	65054	61260	0	0
T3	38688	35408	0	0
T4	468891	347381	0	0
T7	694823	694730	0	0
T8	237017	599	0	0
T12	85884	55175	0	0
T13	464318	16876	0	0
T14	1532	1437	0	0
T20	39516	15486	0	0