Module Definition
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Module : prim_alert_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alerts[0].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[1].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[2].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[3].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[4].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[5].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[6].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[7].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[8].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[9].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[10].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[11].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[12].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[13].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[14].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[15].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[16].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[17].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[18].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[19].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[20].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[21].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[22].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[23].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[24].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[25].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[26].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[27].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[28].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[29].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[30].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[31].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[32].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[33].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[34].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[35].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[36].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[37].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[38].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[39].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[40].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[41].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[42].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[43].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[44].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[45].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[46].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[47].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[48].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[49].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[50].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[51].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[52].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[53].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[54].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[55].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[56].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[57].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[58].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[59].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[60].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[61].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[62].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[63].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[64].u_alert_receiver 100.00 100.00



Module Instance : tb.dut.gen_alerts[0].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[1].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[2].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[3].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[4].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[5].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[6].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[7].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[8].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[9].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[10].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[11].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[12].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[13].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[14].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[15].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[16].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[17].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[18].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[19].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[20].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[21].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[22].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[23].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[24].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[25].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[26].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[27].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[28].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[29].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[30].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[31].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[32].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[33].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[34].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[35].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[36].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[37].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[38].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[39].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[40].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[41].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[42].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[43].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[44].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[45].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[46].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[47].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[48].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[49].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[50].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[51].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[52].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[53].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[54].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[55].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[56].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[57].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[58].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[59].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[60].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[61].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[62].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[63].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[64].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T7,T5 Yes T1,T7,T5 INPUT
ping_ok_o Yes Yes T7,T5,T6 Yes T7,T5,T6 OUTPUT
integ_fail_o Yes Yes T4,T6,T24 Yes T4,T6,T24 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T7,T5 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T1,T7,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[0].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T6,T15 Yes T5,T6,T15 INPUT
ping_ok_o Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
integ_fail_o Yes Yes T6,T29,T25 Yes T6,T29,T25 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[1].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T7,T5,T15 Yes T7,T5,T15 INPUT
ping_ok_o Yes Yes T7,T5,T15 Yes T7,T5,T15 OUTPUT
integ_fail_o Yes Yes T4,T24,T26 Yes T4,T24,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T5,T15 Yes T5,T15,T75 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T75 Yes T7,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[2].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T15 Yes T1,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T29 Yes T5,T15,T29 OUTPUT
integ_fail_o Yes Yes T24,T26,T29 Yes T24,T26,T29 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T15 Yes T5,T15,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T29 Yes T1,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[3].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T85 Yes T5,T15,T85 INPUT
ping_ok_o Yes Yes T5,T15,T85 Yes T5,T15,T85 OUTPUT
integ_fail_o Yes Yes T4,T6,T25 Yes T4,T6,T25 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T25 Yes T5,T15,T28 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T28 Yes T5,T15,T25 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[4].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T27 Yes T5,T15,T27 INPUT
ping_ok_o Yes Yes T5,T15,T27 Yes T5,T15,T27 OUTPUT
integ_fail_o Yes Yes T4,T26,T25 Yes T4,T26,T25 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T27 Yes T5,T15,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T27 Yes T5,T15,T27 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[5].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T5,T6 Yes T8,T5,T6 INPUT
ping_ok_o Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
integ_fail_o Yes Yes T4,T6,T26 Yes T4,T6,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T5,T6 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T8,T5,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[6].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T85 Yes T5,T15,T85 INPUT
ping_ok_o Yes Yes T5,T15,T85 Yes T5,T15,T85 OUTPUT
integ_fail_o Yes Yes T6,T24,T26 Yes T6,T24,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T35 Yes T5,T15,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T30 Yes T5,T15,T35 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[7].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T17 Yes T5,T15,T17 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T4,T24,T29 Yes T4,T24,T29 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T17 Yes T5,T15,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T25 Yes T5,T15,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[8].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T37 Yes T5,T15,T37 INPUT
ping_ok_o Yes Yes T5,T15,T37 Yes T5,T15,T37 OUTPUT
integ_fail_o Yes Yes T43,T24,T45 Yes T43,T24,T45 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T37 Yes T5,T15,T236 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T236 Yes T5,T15,T37 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[9].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T15 Yes T1,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T4,T6,T45 Yes T4,T6,T45 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T15 Yes T5,T15,T37 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T37 Yes T1,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[10].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T5,T15 Yes T8,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T85 Yes T5,T15,T85 OUTPUT
integ_fail_o Yes Yes T43,T24,T45 Yes T43,T24,T45 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T5,T15 Yes T5,T15,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T30 Yes T8,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[11].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T18 Yes T5,T15,T18 INPUT
ping_ok_o Yes Yes T5,T15,T18 Yes T5,T15,T18 OUTPUT
integ_fail_o Yes Yes T68,T70,T75 Yes T68,T70,T75 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T25 Yes T5,T15,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T25 Yes T5,T15,T25 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[12].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T7,T5,T15 Yes T7,T5,T15 INPUT
ping_ok_o Yes Yes T7,T5,T15 Yes T7,T5,T15 OUTPUT
integ_fail_o Yes Yes T4,T43,T24 Yes T4,T43,T24 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T5,T15 Yes T5,T15,T17 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T17 Yes T7,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[13].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T7,T5,T15 Yes T7,T5,T15 INPUT
ping_ok_o Yes Yes T7,T5,T15 Yes T7,T5,T15 OUTPUT
integ_fail_o Yes Yes T26,T25,T237 Yes T26,T25,T237 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T5,T15 Yes T5,T15,T236 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T236 Yes T7,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[14].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T6,T15 Yes T5,T6,T15 INPUT
ping_ok_o Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
integ_fail_o Yes Yes T43,T24,T26 Yes T43,T24,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[15].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T5,T15 Yes T8,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T37 Yes T5,T15,T37 OUTPUT
integ_fail_o Yes Yes T4,T6,T24 Yes T4,T6,T24 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T5,T15 Yes T5,T15,T37 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T37 Yes T8,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[16].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T7,T5,T6 Yes T7,T5,T6 INPUT
ping_ok_o Yes Yes T7,T5,T6 Yes T7,T5,T6 OUTPUT
integ_fail_o Yes Yes T43,T24,T29 Yes T43,T24,T29 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T5,T6 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T7,T5,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[17].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T17 Yes T5,T15,T17 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T4,T6,T237 Yes T4,T6,T237 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[18].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T18 Yes T5,T15,T18 INPUT
ping_ok_o Yes Yes T5,T15,T18 Yes T5,T15,T18 OUTPUT
integ_fail_o Yes Yes T4,T6,T25 Yes T4,T6,T25 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T69 Yes T5,T15,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T30 Yes T5,T15,T69 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[19].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T5,T6 Yes T8,T5,T6 INPUT
ping_ok_o Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
integ_fail_o Yes Yes T45,T29,T237 Yes T45,T29,T237 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T5,T6 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T8,T5,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[20].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T19 Yes T5,T15,T19 INPUT
ping_ok_o Yes Yes T5,T15,T29 Yes T5,T15,T29 OUTPUT
integ_fail_o Yes Yes T24,T25,T79 Yes T24,T25,T79 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T19 Yes T5,T15,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T29 Yes T5,T15,T19 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[21].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T17 Yes T5,T15,T17 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T4,T24,T29 Yes T4,T24,T29 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[22].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T35 Yes T5,T15,T35 INPUT
ping_ok_o Yes Yes T5,T15,T35 Yes T5,T15,T35 OUTPUT
integ_fail_o Yes Yes T43,T25,T21 Yes T43,T25,T21 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T35 Yes T5,T15,T68 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T68 Yes T5,T15,T35 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[23].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T5,T15 Yes T8,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T25 Yes T5,T15,T25 OUTPUT
integ_fail_o Yes Yes T45,T29,T237 Yes T45,T29,T237 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T5,T15 Yes T5,T15,T68 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T68 Yes T8,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[24].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T17 Yes T5,T15,T17 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T6,T24,T26 Yes T6,T24,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T17 Yes T5,T15,T48 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T48 Yes T5,T15,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[25].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T17 Yes T5,T15,T17 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T43,T24,T25 Yes T43,T24,T25 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T17 Yes T5,T15,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T25 Yes T5,T15,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[26].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T15 Yes T1,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T35 Yes T5,T15,T35 OUTPUT
integ_fail_o Yes Yes T4,T24,T45 Yes T4,T24,T45 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T15 Yes T1,T5,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T5,T15 Yes T1,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[27].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T6 Yes T1,T5,T6 INPUT
ping_ok_o Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
integ_fail_o Yes Yes T4,T43,T24 Yes T4,T43,T24 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T6 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T1,T5,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[28].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T7,T8,T5 Yes T7,T8,T5 INPUT
ping_ok_o Yes Yes T7,T5,T15 Yes T7,T5,T15 OUTPUT
integ_fail_o Yes Yes T4,T45,T26 Yes T4,T45,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T5 Yes T5,T15,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T30 Yes T7,T8,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[29].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T15 Yes T1,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T85 Yes T5,T15,T85 OUTPUT
integ_fail_o Yes Yes T4,T43,T45 Yes T4,T43,T45 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T15 Yes T5,T15,T37 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T37 Yes T1,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[30].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T7,T5 Yes T1,T7,T5 INPUT
ping_ok_o Yes Yes T7,T5,T6 Yes T7,T5,T6 OUTPUT
integ_fail_o Yes Yes T6,T45,T29 Yes T6,T45,T29 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T7,T5 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T1,T7,T5 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[31].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T6,T15 Yes T5,T6,T15 INPUT
ping_ok_o Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
integ_fail_o Yes Yes T4,T45,T29 Yes T4,T45,T29 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[32].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T7,T5,T6 Yes T7,T5,T6 INPUT
ping_ok_o Yes Yes T7,T5,T6 Yes T7,T5,T6 OUTPUT
integ_fail_o Yes Yes T24,T29,T68 Yes T24,T29,T68 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T5,T6 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T7,T5,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[33].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T16 Yes T5,T15,T16 INPUT
ping_ok_o Yes Yes T5,T15,T68 Yes T5,T15,T68 OUTPUT
integ_fail_o Yes Yes T25,T65,T68 Yes T25,T65,T68 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T16 Yes T5,T15,T68 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T68 Yes T5,T15,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[34].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T6,T15 Yes T5,T6,T15 INPUT
ping_ok_o Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
integ_fail_o Yes Yes T4,T24,T45 Yes T4,T24,T45 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[35].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T17 Yes T5,T15,T17 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T25,T237,T70 Yes T25,T237,T70 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T17 Yes T5,T15,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T29 Yes T5,T15,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[36].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T17 Yes T5,T15,T17 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T6,T43,T24 Yes T6,T43,T24 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T17 Yes T5,T15,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T30 Yes T5,T15,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[37].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T17 Yes T5,T15,T17 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T4,T6,T43 Yes T4,T6,T43 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T17 Yes T5,T15,T75 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T75 Yes T5,T15,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[38].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T7,T5,T15 Yes T7,T5,T15 INPUT
ping_ok_o Yes Yes T7,T5,T15 Yes T7,T5,T15 OUTPUT
integ_fail_o Yes Yes T4,T26,T21 Yes T4,T26,T21 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T5,T15 Yes T5,T15,T236 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T236 Yes T7,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[39].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T64 Yes T5,T15,T64 INPUT
ping_ok_o Yes Yes T5,T15,T64 Yes T5,T15,T64 OUTPUT
integ_fail_o Yes Yes T6,T43,T24 Yes T6,T43,T24 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T64 Yes T5,T15,T79 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T79 Yes T5,T15,T64 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[40].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T17 Yes T5,T15,T17 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T6,T24,T45 Yes T6,T24,T45 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T17 Yes T5,T15,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T29 Yes T5,T15,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[41].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T8,T5,T15 Yes T8,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T29 Yes T5,T15,T29 OUTPUT
integ_fail_o Yes Yes T24,T29,T21 Yes T24,T29,T21 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T5,T15 Yes T5,T15,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T29 Yes T8,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[42].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T7,T5,T15 Yes T7,T5,T15 INPUT
ping_ok_o Yes Yes T7,T5,T15 Yes T7,T5,T15 OUTPUT
integ_fail_o Yes Yes T4,T24,T25 Yes T4,T24,T25 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T5,T15 Yes T5,T15,T68 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T68 Yes T7,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[43].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T15 Yes T1,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T4,T24,T45 Yes T4,T24,T45 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T15 Yes T1,T5,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T5,T15 Yes T1,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[44].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T15 Yes T1,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T29 Yes T5,T15,T29 OUTPUT
integ_fail_o Yes Yes T43,T45,T26 Yes T43,T45,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T15 Yes T5,T15,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T74 Yes T1,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[45].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T16 Yes T5,T15,T16 INPUT
ping_ok_o Yes Yes T5,T15,T29 Yes T5,T15,T29 OUTPUT
integ_fail_o Yes Yes T24,T45,T29 Yes T24,T45,T29 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T16 Yes T5,T15,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T25 Yes T5,T15,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[46].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T29 Yes T5,T15,T29 INPUT
ping_ok_o Yes Yes T5,T15,T29 Yes T5,T15,T29 OUTPUT
integ_fail_o Yes Yes T4,T24,T45 Yes T4,T24,T45 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T29 Yes T5,T15,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T29 Yes T5,T15,T29 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[47].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T17 Yes T5,T15,T17 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T4,T6,T26 Yes T4,T6,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T17 Yes T5,T15,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T25 Yes T5,T15,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[48].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T25 Yes T5,T15,T25 INPUT
ping_ok_o Yes Yes T5,T15,T25 Yes T5,T15,T25 OUTPUT
integ_fail_o Yes Yes T6,T45,T29 Yes T6,T45,T29 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T25 Yes T5,T15,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T25 Yes T5,T15,T25 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[49].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T18 Yes T5,T15,T18 INPUT
ping_ok_o Yes Yes T5,T15,T18 Yes T5,T15,T18 OUTPUT
integ_fail_o Yes Yes T6,T24,T45 Yes T6,T24,T45 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T19 Yes T5,T15,T69 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T69 Yes T5,T15,T19 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[50].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T6,T15 Yes T5,T6,T15 INPUT
ping_ok_o Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
integ_fail_o Yes Yes T24,T26,T29 Yes T24,T26,T29 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[51].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T16 Yes T5,T15,T16 INPUT
ping_ok_o Yes Yes T5,T15,T37 Yes T5,T15,T37 OUTPUT
integ_fail_o Yes Yes T26,T29,T25 Yes T26,T29,T25 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T16 Yes T5,T15,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T23 Yes T5,T15,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[52].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T15 Yes T1,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T25,T21,T65 Yes T25,T21,T65 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T15 Yes T5,T15,T17 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T17 Yes T1,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[53].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T25 Yes T5,T15,T25 INPUT
ping_ok_o Yes Yes T5,T15,T25 Yes T5,T15,T25 OUTPUT
integ_fail_o Yes Yes T4,T6,T24 Yes T4,T6,T24 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T25 Yes T5,T15,T64 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T64 Yes T5,T15,T25 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[54].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T37 Yes T5,T15,T37 INPUT
ping_ok_o Yes Yes T5,T15,T37 Yes T5,T15,T37 OUTPUT
integ_fail_o Yes Yes T4,T45,T25 Yes T4,T45,T25 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T37 Yes T5,T15,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T30 Yes T5,T15,T37 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[55].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T7,T5,T15 Yes T7,T5,T15 INPUT
ping_ok_o Yes Yes T7,T5,T15 Yes T7,T5,T15 OUTPUT
integ_fail_o Yes Yes T24,T45,T68 Yes T24,T45,T68 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T5,T15 Yes T5,T15,T90 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T90 Yes T7,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[56].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T16 Yes T5,T15,T16 INPUT
ping_ok_o Yes Yes T5,T15,T29 Yes T5,T15,T29 OUTPUT
integ_fail_o Yes Yes T4,T6,T25 Yes T4,T6,T25 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T16 Yes T5,T15,T29 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T29 Yes T5,T15,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[57].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T27 Yes T5,T15,T27 INPUT
ping_ok_o Yes Yes T5,T15,T27 Yes T5,T15,T27 OUTPUT
integ_fail_o Yes Yes T4,T6,T26 Yes T4,T6,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T27 Yes T5,T15,T75 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T75 Yes T5,T15,T27 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[58].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T15 Yes T1,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T6,T24,T26 Yes T6,T24,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T15 Yes T5,T15,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T25 Yes T1,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[59].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T37 Yes T5,T15,T37 INPUT
ping_ok_o Yes Yes T5,T15,T37 Yes T5,T15,T37 OUTPUT
integ_fail_o Yes Yes T4,T45,T26 Yes T4,T45,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T37 Yes T5,T15,T37 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T37 Yes T5,T15,T37 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[60].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T85 Yes T5,T15,T85 INPUT
ping_ok_o Yes Yes T5,T15,T85 Yes T5,T15,T85 OUTPUT
integ_fail_o Yes Yes T4,T6,T29 Yes T4,T6,T29 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T238 Yes T5,T15,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T23 Yes T5,T15,T238 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[61].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T15 Yes T1,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T17 Yes T5,T15,T17 OUTPUT
integ_fail_o Yes Yes T6,T43,T26 Yes T6,T43,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T15 Yes T5,T15,T79 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T79 Yes T1,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[62].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T5,T15 Yes T1,T5,T15 INPUT
ping_ok_o Yes Yes T5,T15,T85 Yes T5,T15,T85 OUTPUT
integ_fail_o Yes Yes T6,T45,T26 Yes T6,T45,T26 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T15 Yes T5,T15,T48 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T48 Yes T1,T5,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[63].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T6,T15 Yes T5,T6,T15 INPUT
ping_ok_o Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
integ_fail_o Yes Yes T4,T29,T25 Yes T4,T29,T25 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[64].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T5,T15,T16 Yes T5,T15,T16 INPUT
ping_ok_o Yes Yes T5,T15,T37 Yes T5,T15,T37 OUTPUT
integ_fail_o Yes Yes T4,T43,T45 Yes T4,T43,T45 OUTPUT
alert_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T15,T16 Yes T5,T15,T90 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T15,T90 Yes T5,T15,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT

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