Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T4,T13,T7
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T4,T14,T6
1	0	Covered	T3,T4,T21

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T21

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T22
1	1	Covered	T4,T14,T6

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T2,T3,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T13,T7

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T2,T3,T4
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T7,T6,T23
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T4,T24,T25
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T26,T27,T28
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T29,T30,T31
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T3,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T3,T4
TimeoutSt->Phase0St	172	Covered	T3,T4,T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T14
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T7,T23,T32
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T24,T25
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T27,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1056	0	0
CheckAccumTrig0_A	2147483647	2301	0	0
CheckAccumTrig1_A	2147483647	115	0	0
CheckClr_A	2147483647	1071	0	0
CheckEn_A	2147483647	1092205035	0	0
CheckPhase0_A	2147483647	2673	0	0
CheckPhase1_A	2147483647	2626	0	0
CheckPhase2_A	2147483647	2579	0	0
CheckPhase3_A	2147483647	2531	0	0
CheckTimeout0_A	2147483647	8139	0	0
CheckTimeoutSt1_A	2147483647	879657	0	0
CheckTimeoutSt2_A	2147483647	7720	0	0
CheckTimeoutStTrig_A	2147483647	298	0	0
ErrorStAllEscAsserted_A	2147483647	5737	0	0
ErrorStIsTerminal_A	2147483647	4657	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1056	0	0
T9	82184	125	0	0
T10	0	267	0	0
T11	0	206	0	0
T25	1471768	0	0	0
T27	592084	0	0	0
T29	1217540	0	0	0
T33	0	233	0	0
T34	0	225	0	0
T35	1089820	0	0	0
T36	596028	0	0	0
T37	992124	0	0	0
T38	125044	0	0	0
T39	1748232	0	0	0
T40	131688	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2301	0	0
T1	973479	4	0	0
T2	195162	2	0	0
T3	154752	3	0	0
T4	1875564	15	0	0
T5	115632	0	0	0
T6	0	6	0	0
T7	2779292	5	0	0
T8	948068	0	0	0
T12	343536	0	0	0
T13	1857272	3	0	0
T14	6128	0	0	0
T16	0	2	0	0
T17	0	2	0	0
T20	158064	4	0	0
T24	0	5	0	0
T26	0	14	0	0
T41	21658	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	17	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115	0	0
T3	38688	1	0	0
T4	937782	2	0	0
T5	77088	0	0	0
T6	118984	0	0	0
T7	1389646	0	0	0
T8	474034	0	0	0
T12	171768	0	0	0
T13	928636	0	0	0
T14	3064	0	0	0
T20	79032	0	0	0
T21	153565	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T41	43316	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	6	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	106432	0	0	0
T65	357324	0	0	0
T66	741175	0	0	0
T67	49911	0	0	0
T68	284604	0	0	0
T69	140654	0	0	0
T70	62032	0	0	0
T71	204839	0	0	0
T72	18562	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1071	0	0
T1	973479	0	0	0
T2	65054	0	0	0
T3	77376	2	0	0
T4	1406673	5	0	0
T5	115632	0	0	0
T6	237968	3	0	0
T7	2779292	3	0	0
T8	948068	0	0	0
T12	257652	0	0	0
T13	1392954	0	0	0
T14	4596	0	0	0
T20	158064	1	0	0
T24	200838	4	0	0
T25	0	4	0	0
T26	0	25	0	0
T27	0	2	0	0
T29	0	1	0	0
T31	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	64974	3	0	0
T42	34626	1	0	0
T43	15153	0	0	0
T45	0	5	0	0
T65	0	4	0	0
T68	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	4525	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1092205035	0	0
T1	3893916	1966819	0	0
T2	260216	134112	0	0
T3	154752	72786	0	0
T4	1875564	1715627	0	0
T7	2779292	1391470	0	0
T8	948068	242039	0	0
T12	343536	229850	0	0
T13	1857272	496326	0	0
T14	6128	4890	0	0
T20	158064	93923	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2673	0	0
T1	973479	4	0	0
T2	195162	2	0	0
T3	154752	4	0	0
T4	1875564	19	0	0
T5	115632	0	0	0
T6	0	9	0	0
T7	2779292	4	0	0
T8	948068	0	0	0
T12	343536	0	0	0
T13	1857272	3	0	0
T14	6128	1	0	0
T16	0	2	0	0
T17	0	2	0	0
T20	158064	4	0	0
T24	0	5	0	0
T26	0	24	0	0
T41	21658	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	18	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2626	0	0
T1	973479	2	0	0
T2	195162	2	0	0
T3	154752	4	0	0
T4	1875564	18	0	0
T5	115632	0	0	0
T6	0	9	0	0
T7	2779292	4	0	0
T8	948068	0	0	0
T12	343536	0	0	0
T13	1857272	3	0	0
T14	6128	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T20	158064	4	0	0
T24	0	3	0	0
T26	0	24	0	0
T41	21658	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	18	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2579	0	0
T1	973479	2	0	0
T2	195162	2	0	0
T3	154752	4	0	0
T4	1875564	17	0	0
T5	115632	0	0	0
T6	0	8	0	0
T7	2779292	4	0	0
T8	948068	0	0	0
T12	343536	0	0	0
T13	1857272	3	0	0
T14	6128	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T20	158064	4	0	0
T24	0	3	0	0
T26	0	23	0	0
T41	21658	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	18	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2531	0	0
T1	973479	2	0	0
T2	195162	2	0	0
T3	154752	4	0	0
T4	1875564	17	0	0
T5	115632	0	0	0
T6	0	8	0	0
T7	2779292	4	0	0
T8	948068	0	0	0
T12	343536	0	0	0
T13	1857272	3	0	0
T14	6128	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T20	158064	4	0	0
T24	0	3	0	0
T26	0	23	0	0
T41	21658	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	18	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8139	0	0
T2	130108	2	0	0
T3	116064	3	0	0
T4	1875564	234	0	0
T5	154176	0	0	0
T6	118984	9	0	0
T7	2779292	0	0	0
T8	948068	0	0	0
T12	343536	8	0	0
T13	1857272	0	0	0
T14	6128	1	0	0
T20	158064	1	0	0
T21	0	11	0	0
T24	0	51	0	0
T25	0	3	0	0
T26	0	282	0	0
T29	0	2	0	0
T40	0	2	0	0
T41	43316	0	0	0
T45	0	6	0	0
T67	0	4	0	0
T68	0	2	0	0
T73	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	879657	0	0
T2	130108	302	0	0
T3	116064	224	0	0
T4	1875564	21975	0	0
T5	154176	0	0	0
T6	118984	2536	0	0
T7	2779292	0	0	0
T8	948068	0	0	0
T12	343536	1642	0	0
T13	1857272	0	0	0
T14	6128	0	0	0
T20	158064	114	0	0
T21	0	751	0	0
T24	0	4175	0	0
T25	0	189	0	0
T26	0	34380	0	0
T29	0	286	0	0
T40	0	835	0	0
T41	43316	0	0	0
T45	0	631	0	0
T67	0	667	0	0
T68	0	267	0	0
T73	0	342	0	0
T76	0	62	0	0
T77	0	128	0	0
T78	0	785	0	0
T79	0	107	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7720	0	0
T2	130108	2	0	0
T3	116064	2	0	0
T4	1875564	230	0	0
T5	154176	0	0	0
T6	118984	4	0	0
T7	2779292	0	0	0
T8	948068	0	0	0
T12	343536	8	0	0
T13	1857272	0	0	0
T14	6128	0	0	0
T20	158064	1	0	0
T21	0	25	0	0
T24	0	51	0	0
T25	0	3	0	0
T26	0	268	0	0
T29	0	2	0	0
T40	0	2	0	0
T41	43316	0	0	0
T45	0	5	0	0
T67	0	4	0	0
T68	0	5	0	0
T73	0	1	0	0
T76	0	1	0	0
T78	0	6	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	298	0	0
T4	468891	2	0	0
T5	38544	0	0	0
T6	237968	3	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T9	20546	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	1	0	0
T16	763504	0	0	0
T17	299418	0	0	0
T18	108152	0	0	0
T19	104225	0	0	0
T20	39516	0	0	0
T21	0	1	0	0
T26	445387	11	0	0
T28	0	2	0	0
T30	0	3	0	0
T35	272455	0	0	0
T41	21658	0	0	0
T42	34626	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T68	0	1	0	0
T70	0	2	0	0
T75	0	1	0	0
T77	79764	1	0	0
T78	86848	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	5	0	0
T85	257223	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5737	0	0
T9	82184	616	0	0
T10	0	1275	0	0
T11	0	1230	0	0
T25	1471768	0	0	0
T27	592084	0	0	0
T29	1217540	0	0	0
T33	0	1348	0	0
T34	0	1268	0	0
T35	1089820	0	0	0
T36	596028	0	0	0
T37	992124	0	0	0
T38	125044	0	0	0
T39	1748232	0	0	0
T40	131688	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4657	0	0
T9	82184	496	0	0
T10	0	1035	0	0
T11	0	990	0	0
T25	1471768	0	0	0
T27	592084	0	0	0
T29	1217540	0	0	0
T33	0	1108	0	0
T34	0	1028	0	0
T35	1089820	0	0	0
T36	596028	0	0	0
T37	992124	0	0	0
T38	125044	0	0	0
T39	1748232	0	0	0
T40	131688	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3893916	3893660	0	0
T2	260216	259880	0	0
T3	154752	154548	0	0
T4	1875564	1875500	0	0
T7	2779292	2778920	0	0
T8	948068	947688	0	0
T12	343536	343208	0	0
T13	1857272	1857036	0	0
T14	6128	5748	0	0
T20	158064	157836	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3893916	3893660	0	0
T2	260216	259880	0	0
T3	154752	154548	0	0
T4	1875564	1875500	0	0
T7	2779292	2778920	0	0
T8	948068	947688	0	0
T12	343536	343208	0	0
T13	1857272	1857036	0	0
T14	6128	5748	0	0
T20	158064	157836	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T12
1	0	1	Covered	T4,T13,T7
1	1	0	Covered	T2,T4,T12
1	1	1	Covered	T4,T12,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T6
0	1	Covered	T4,T14,T6
1	0	Covered	T4,T23,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T12,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T23,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T6
1	0	Not Covered
1	1	Covered	T4,T14,T6

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T4,T14,T41

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T14
1	Covered	T24,T44,T45

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T14,T7
1	Covered	T3,T4,T42

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T14
1	Covered	T4,T7,T41

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T7,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T7,T41

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T4,T14
Phase1St	198	Covered	T3,T4,T14
Phase2St	215	Covered	T3,T4,T14
Phase3St	233	Covered	T3,T4,T14
TerminalSt	249	Covered	T3,T4,T14
TimeoutSt	159	Covered	T4,T12,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T3,T4,T7
IdleSt->TimeoutSt	159	Covered	T4,T12,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T7,T6,T23
Phase0St->Phase1St	198	Covered	T3,T4,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T24,T52,T86
Phase1St->Phase2St	215	Covered	T3,T4,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T81,T87,T88
Phase2St->Phase3St	233	Covered	T3,T4,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T30,T23,T89
Phase3St->TerminalSt	249	Covered	T3,T4,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T41,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T12,T6
TimeoutSt->Phase0St	172	Covered	T4,T14,T6

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T14,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T7,T23,T32
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T52,T86
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T81,T87,T88
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T23,T89
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T41,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	680599942	263	0	0
CheckAccumTrig0_A	680599942	796	0	0
CheckAccumTrig1_A	680599942	49	0	0
CheckClr_A	680599942	403	0	0
CheckEn_A	680307615	274883759	0	0
CheckPhase0_A	680599942	909	0	0
CheckPhase1_A	680599942	890	0	0
CheckPhase2_A	680599942	875	0	0
CheckPhase3_A	680599942	858	0	0
CheckTimeout0_A	680599942	2161	0	0
CheckTimeoutSt1_A	680599942	267682	0	0
CheckTimeoutSt2_A	680599942	2027	0	0
CheckTimeoutStTrig_A	680599942	83	0	0
ErrorStAllEscAsserted_A	680599942	1454	0	0
ErrorStIsTerminal_A	680599942	1184	0	0
EscStateOut_A	680306184	680236745	0	0
u_state_regs_A	680599942	680415214	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	263	0	0
T9	20546	32	0	0
T10	0	58	0	0
T11	0	54	0	0
T25	367942	0	0	0
T27	148021	0	0	0
T29	304385	0	0	0
T33	0	54	0	0
T34	0	65	0	0
T35	272455	0	0	0
T36	149007	0	0	0
T37	248031	0	0	0
T38	31261	0	0	0
T39	437058	0	0	0
T40	32922	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	796	0	0
T3	38688	1	0	0
T4	468891	2	0	0
T5	38544	0	0	0
T6	0	1	0	0
T7	694823	2	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T24	0	5	0	0
T41	21658	3	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	5	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	49	0	0
T4	468891	1	0	0
T5	38544	0	0	0
T6	118984	0	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T23	0	1	0	0
T41	21658	0	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	403	0	0
T4	468891	1	0	0
T5	38544	0	0	0
T6	118984	1	0	0
T7	694823	1	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T24	0	4	0	0
T26	0	11	0	0
T38	0	1	0	0
T41	21658	3	0	0
T42	0	1	0	0
T45	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680307615	274883759	0	0
T1	973479	106263	0	0
T2	65054	64969	0	0
T3	38688	984	0	0
T4	468891	288318	0	0
T7	694823	2027	0	0
T8	237017	587	0	0
T12	85884	80435	0	0
T13	464318	451283	0	0
T14	1532	582	0	0
T20	39516	37447	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	909	0	0
T3	38688	1	0	0
T4	468891	5	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	1	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	1	0	0
T20	39516	0	0	0
T24	0	5	0	0
T41	21658	3	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	6	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	890	0	0
T3	38688	1	0	0
T4	468891	5	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	1	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	1	0	0
T20	39516	0	0	0
T24	0	3	0	0
T41	21658	3	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	6	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	875	0	0
T3	38688	1	0	0
T4	468891	5	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	1	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	1	0	0
T20	39516	0	0	0
T24	0	3	0	0
T41	21658	3	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	6	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	858	0	0
T3	38688	1	0	0
T4	468891	5	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	1	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	1	0	0
T20	39516	0	0	0
T24	0	3	0	0
T41	21658	3	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	6	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	2161	0	0
T4	468891	43	0	0
T5	38544	0	0	0
T6	118984	6	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	1	0	0
T13	464318	0	0	0
T14	1532	1	0	0
T20	39516	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T26	0	50	0	0
T41	21658	0	0	0
T45	0	3	0	0
T67	0	1	0	0
T68	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	267682	0	0
T4	468891	3992	0	0
T5	38544	0	0	0
T6	118984	1823	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	192	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T21	0	133	0	0
T24	0	109	0	0
T26	0	6830	0	0
T41	21658	0	0	0
T45	0	438	0	0
T67	0	168	0	0
T68	0	267	0	0
T79	0	107	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	2027	0	0
T4	468891	40	0	0
T5	38544	0	0	0
T6	118984	3	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	1	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T26	0	46	0	0
T41	21658	0	0	0
T45	0	2	0	0
T67	0	1	0	0
T68	0	2	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	83	0	0
T4	468891	2	0	0
T5	38544	0	0	0
T6	118984	2	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	1	0	0
T20	39516	0	0	0
T26	0	3	0	0
T28	0	1	0	0
T30	0	2	0	0
T41	21658	0	0	0
T45	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1454	0	0
T9	20546	162	0	0
T10	0	320	0	0
T11	0	307	0	0
T25	367942	0	0	0
T27	148021	0	0	0
T29	304385	0	0	0
T33	0	342	0	0
T34	0	323	0	0
T35	272455	0	0	0
T36	149007	0	0	0
T37	248031	0	0	0
T38	31261	0	0	0
T39	437058	0	0	0
T40	32922	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1184	0	0
T9	20546	132	0	0
T10	0	260	0	0
T11	0	247	0	0
T25	367942	0	0	0
T27	148021	0	0	0
T29	304385	0	0	0
T33	0	282	0	0
T34	0	263	0	0
T35	272455	0	0	0
T36	149007	0	0	0
T37	248031	0	0	0
T38	31261	0	0	0
T39	437058	0	0	0
T40	32922	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680306184	680236745	0	0
T1	973479	973415	0	0
T2	65054	64970	0	0
T3	38688	38637	0	0
T4	468891	468875	0	0
T7	694823	694730	0	0
T8	237017	236922	0	0
T12	85884	85802	0	0
T13	464318	464259	0	0
T14	1532	1437	0	0
T20	39516	39459	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	680415214	0	0
T1	973479	973415	0	0
T2	65054	64970	0	0
T3	38688	38637	0	0
T4	468891	468875	0	0
T7	694823	694730	0	0
T8	237017	236922	0	0
T12	85884	85802	0	0
T13	464318	464259	0	0
T14	1532	1437	0	0
T20	39516	39459	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T4,T13,T8
1	1	0	Covered	T4,T12,T6
1	1	1	Covered	T2,T4,T12

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T12
0	1	Covered	T26,T77,T68
1	0	Covered	T21,T48,T22

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T48,T22

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T12
1	0	Not Covered
1	1	Covered	T26,T77,T68

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T13
1	Covered	T3,T47,T26

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T13
1	Covered	T2,T7,T26

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T6,T45

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T13,T45

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T13,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T45

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T4
Phase1St	198	Covered	T2,T3,T4
Phase2St	215	Covered	T2,T3,T4
Phase3St	233	Covered	T2,T3,T4
TerminalSt	249	Covered	T2,T3,T4
TimeoutSt	159	Covered	T2,T4,T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T2,T3,T4
IdleSt->TimeoutSt	159	Covered	T2,T4,T12
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T22,T90,T91
Phase0St->Phase1St	198	Covered	T2,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T65,T81,T92
Phase1St->Phase2St	215	Covered	T2,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T81,T93
Phase2St->Phase3St	233	Covered	T2,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T31,T94,T95
Phase3St->TerminalSt	249	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T7,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T12
TimeoutSt->Phase0St	172	Covered	T26,T77,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T12
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T77,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T12
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T12
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T90,T91,T58
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T65,T81,T92
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T81,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T94,T95
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T6,T45
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	680599942	235	0	0
CheckAccumTrig0_A	680599942	511	0	0
CheckAccumTrig1_A	680599942	17	0	0
CheckClr_A	680599942	227	0	0
CheckEn_A	680307615	258691656	0	0
CheckPhase0_A	680599942	601	0	0
CheckPhase1_A	680599942	592	0	0
CheckPhase2_A	680599942	579	0	0
CheckPhase3_A	680599942	566	0	0
CheckTimeout0_A	680599942	2056	0	0
CheckTimeoutSt1_A	680599942	206329	0	0
CheckTimeoutSt2_A	680599942	1956	0	0
CheckTimeoutStTrig_A	680599942	81	0	0
ErrorStAllEscAsserted_A	680599942	1391	0	0
ErrorStIsTerminal_A	680599942	1121	0	0
EscStateOut_A	680306184	680236745	0	0
u_state_regs_A	680599942	680415214	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	235	0	0
T9	20546	33	0	0
T10	0	62	0	0
T11	0	48	0	0
T25	367942	0	0	0
T27	148021	0	0	0
T29	304385	0	0	0
T33	0	51	0	0
T34	0	41	0	0
T35	272455	0	0	0
T36	149007	0	0	0
T37	248031	0	0	0
T38	31261	0	0	0
T39	437058	0	0	0
T40	32922	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	511	0	0
T2	65054	1	0	0
T3	38688	1	0	0
T4	468891	3	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	2	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T16	0	1	0	0
T20	39516	0	0	0
T26	0	8	0	0
T45	0	3	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	17	0	0
T21	153565	1	0	0
T22	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	106432	0	0	0
T65	357324	0	0	0
T66	741175	0	0	0
T67	49911	0	0	0
T68	284604	0	0	0
T69	140654	0	0	0
T70	62032	0	0	0
T71	204839	0	0	0
T72	18562	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	227	0	0
T5	38544	0	0	0
T6	118984	1	0	0
T7	694823	1	0	0
T8	237017	0	0	0
T20	39516	0	0	0
T24	200838	0	0	0
T26	0	6	0	0
T27	0	2	0	0
T31	0	2	0	0
T41	21658	0	0	0
T42	34626	0	0	0
T43	15153	0	0	0
T45	0	2	0	0
T65	0	4	0	0
T68	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	4525	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680307615	258691656	0	0
T1	973479	810740	0	0
T2	65054	2150	0	0
T3	38688	7097	0	0
T4	468891	144586	0	0
T7	694823	1008	0	0
T8	237017	3932	0	0
T12	85884	8439	0	0
T13	464318	16958	0	0
T14	1532	1436	0	0
T20	39516	39458	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	601	0	0
T2	65054	1	0	0
T3	38688	1	0	0
T4	468891	3	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	2	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T16	0	1	0	0
T20	39516	0	0	0
T26	0	9	0	0
T45	0	3	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	592	0	0
T2	65054	1	0	0
T3	38688	1	0	0
T4	468891	3	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	2	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T16	0	1	0	0
T20	39516	0	0	0
T26	0	9	0	0
T45	0	3	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	579	0	0
T2	65054	1	0	0
T3	38688	1	0	0
T4	468891	3	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	2	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T16	0	1	0	0
T20	39516	0	0	0
T26	0	9	0	0
T45	0	3	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	566	0	0
T2	65054	1	0	0
T3	38688	1	0	0
T4	468891	3	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	2	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T16	0	1	0	0
T20	39516	0	0	0
T26	0	9	0	0
T45	0	3	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	2056	0	0
T2	65054	1	0	0
T3	38688	0	0	0
T4	468891	105	0	0
T5	38544	0	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	6	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T21	0	2	0	0
T24	0	49	0	0
T26	0	7	0	0
T67	0	3	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	206329	0	0
T2	65054	151	0	0
T3	38688	0	0	0
T4	468891	9692	0	0
T5	38544	0	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	1287	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T21	0	67	0	0
T24	0	3957	0	0
T26	0	769	0	0
T67	0	499	0	0
T76	0	62	0	0
T77	0	128	0	0
T78	0	306	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1956	0	0
T2	65054	1	0	0
T3	38688	0	0	0
T4	468891	105	0	0
T5	38544	0	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	6	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T21	0	1	0	0
T24	0	49	0	0
T26	0	6	0	0
T67	0	3	0	0
T68	0	3	0	0
T76	0	1	0	0
T78	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	81	0	0
T9	20546	0	0	0
T16	763504	0	0	0
T17	299418	0	0	0
T18	108152	0	0	0
T19	104225	0	0	0
T26	445387	1	0	0
T28	0	1	0	0
T35	272455	0	0	0
T48	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0
T77	79764	1	0	0
T78	86848	0	0	0
T81	0	1	0	0
T85	257223	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1391	0	0
T9	20546	157	0	0
T10	0	282	0	0
T11	0	311	0	0
T25	367942	0	0	0
T27	148021	0	0	0
T29	304385	0	0	0
T33	0	319	0	0
T34	0	322	0	0
T35	272455	0	0	0
T36	149007	0	0	0
T37	248031	0	0	0
T38	31261	0	0	0
T39	437058	0	0	0
T40	32922	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1121	0	0
T9	20546	127	0	0
T10	0	222	0	0
T11	0	251	0	0
T25	367942	0	0	0
T27	148021	0	0	0
T29	304385	0	0	0
T33	0	259	0	0
T34	0	262	0	0
T35	272455	0	0	0
T36	149007	0	0	0
T37	248031	0	0	0
T38	31261	0	0	0
T39	437058	0	0	0
T40	32922	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680306184	680236745	0	0
T1	973479	973415	0	0
T2	65054	64970	0	0
T3	38688	38637	0	0
T4	468891	468875	0	0
T7	694823	694730	0	0
T8	237017	236922	0	0
T12	85884	85802	0	0
T13	464318	464259	0	0
T14	1532	1437	0	0
T20	39516	39459	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	680415214	0	0
T1	973479	973415	0	0
T2	65054	64970	0	0
T3	38688	38637	0	0
T4	468891	468875	0	0
T7	694823	694730	0	0
T8	237017	236922	0	0
T12	85884	85802	0	0
T13	464318	464259	0	0
T14	1532	1437	0	0
T20	39516	39459	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T4,T13,T43
1	1	0	Covered	T3,T4,T12
1	1	1	Covered	T3,T4,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T6,T26,T21
1	0	Covered	T3,T4,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Not Covered
1	1	Covered	T6,T26,T21

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T4,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T13
1	Covered	T2,T3,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T7,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T43,T45

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T13,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T4
Phase1St	198	Covered	T2,T3,T4
Phase2St	215	Covered	T2,T3,T4
Phase3St	233	Covered	T2,T3,T4
TerminalSt	249	Covered	T2,T3,T4
TimeoutSt	159	Covered	T3,T4,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T2,T3,T4
IdleSt->TimeoutSt	159	Covered	T3,T4,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T58,T96,T97
Phase0St->Phase1St	198	Covered	T2,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T25,T93
Phase1St->Phase2St	215	Covered	T2,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T26,T28,T98
Phase2St->Phase3St	233	Covered	T2,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T99,T100
Phase3St->TerminalSt	249	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T6
TimeoutSt->Phase0St	172	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T97,T101,T102
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T25,T93
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T28,T98
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T99,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	680599942	265	0	0
CheckAccumTrig0_A	680599942	489	0	0
CheckAccumTrig1_A	680599942	26	0	0
CheckClr_A	680599942	203	0	0
CheckEn_A	680307615	262363493	0	0
CheckPhase0_A	680599942	573	0	0
CheckPhase1_A	680599942	567	0	0
CheckPhase2_A	680599942	561	0	0
CheckPhase3_A	680599942	554	0	0
CheckTimeout0_A	680599942	1975	0	0
CheckTimeoutSt1_A	680599942	187587	0	0
CheckTimeoutSt2_A	680599942	1883	0	0
CheckTimeoutStTrig_A	680599942	66	0	0
ErrorStAllEscAsserted_A	680599942	1411	0	0
ErrorStIsTerminal_A	680599942	1141	0	0
EscStateOut_A	680306184	680236745	0	0
u_state_regs_A	680599942	680415214	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	265	0	0
T9	20546	37	0	0
T10	0	74	0	0
T11	0	47	0	0
T25	367942	0	0	0
T27	148021	0	0	0
T29	304385	0	0	0
T33	0	58	0	0
T34	0	49	0	0
T35	272455	0	0	0
T36	149007	0	0	0
T37	248031	0	0	0
T38	31261	0	0	0
T39	437058	0	0	0
T40	32922	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	489	0	0
T2	65054	1	0	0
T3	38688	1	0	0
T4	468891	7	0	0
T5	38544	0	0	0
T6	0	1	0	0
T7	694823	1	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T20	39516	2	0	0
T26	0	5	0	0
T43	0	1	0	0
T45	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	26	0	0
T3	38688	1	0	0
T4	468891	1	0	0
T5	38544	0	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T41	21658	0	0	0
T50	0	4	0	0
T96	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	3	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	203	0	0
T3	38688	2	0	0
T4	468891	4	0	0
T5	38544	0	0	0
T6	0	1	0	0
T7	694823	1	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	1	0	0
T25	0	4	0	0
T26	0	8	0	0
T29	0	1	0	0
T37	0	1	0	0
T41	21658	0	0	0
T45	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680307615	262363493	0	0
T1	973479	973414	0	0
T2	65054	5734	0	0
T3	38688	29298	0	0
T4	468891	941651	0	0
T7	694823	693706	0	0
T8	237017	236921	0	0
T12	85884	85801	0	0
T13	464318	11209	0	0
T14	1532	1436	0	0
T20	39516	2626	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	573	0	0
T2	65054	1	0	0
T3	38688	2	0	0
T4	468891	8	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	1	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T20	39516	2	0	0
T26	0	12	0	0
T43	0	1	0	0
T45	0	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	567	0	0
T2	65054	1	0	0
T3	38688	2	0	0
T4	468891	7	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	1	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T20	39516	2	0	0
T26	0	12	0	0
T43	0	1	0	0
T45	0	5	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	561	0	0
T2	65054	1	0	0
T3	38688	2	0	0
T4	468891	7	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	1	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T20	39516	2	0	0
T26	0	11	0	0
T43	0	1	0	0
T45	0	5	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	554	0	0
T2	65054	1	0	0
T3	38688	2	0	0
T4	468891	7	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	1	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T20	39516	2	0	0
T26	0	11	0	0
T43	0	1	0	0
T45	0	5	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1975	0	0
T3	38688	2	0	0
T4	468891	86	0	0
T5	38544	0	0	0
T6	0	2	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T21	0	7	0	0
T25	0	3	0	0
T26	0	12	0	0
T29	0	1	0	0
T40	0	2	0	0
T41	21658	0	0	0
T45	0	1	0	0
T78	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	187587	0	0
T3	38688	113	0	0
T4	468891	8291	0	0
T5	38544	0	0	0
T6	0	712	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T21	0	551	0	0
T25	0	189	0	0
T26	0	826	0	0
T29	0	168	0	0
T40	0	835	0	0
T41	21658	0	0	0
T45	0	78	0	0
T78	0	479	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1883	0	0
T3	38688	1	0	0
T4	468891	85	0	0
T5	38544	0	0	0
T6	0	1	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	0	0	0
T21	0	6	0	0
T25	0	3	0	0
T26	0	5	0	0
T29	0	1	0	0
T40	0	2	0	0
T41	21658	0	0	0
T45	0	1	0	0
T78	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	66	0	0
T6	118984	1	0	0
T15	17764	0	0	0
T21	0	1	0	0
T24	200838	0	0	0
T26	0	7	0	0
T30	0	1	0	0
T42	34626	0	0	0
T43	15153	0	0	0
T44	25809	0	0	0
T45	312473	0	0	0
T46	144474	0	0	0
T47	4592	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T70	0	1	0	0
T76	4525	0	0	0
T80	0	1	0	0
T84	0	4	0	0
T109	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1411	0	0
T9	20546	128	0	0
T10	0	340	0	0
T11	0	302	0	0
T25	367942	0	0	0
T27	148021	0	0	0
T29	304385	0	0	0
T33	0	354	0	0
T34	0	287	0	0
T35	272455	0	0	0
T36	149007	0	0	0
T37	248031	0	0	0
T38	31261	0	0	0
T39	437058	0	0	0
T40	32922	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1141	0	0
T9	20546	98	0	0
T10	0	280	0	0
T11	0	242	0	0
T25	367942	0	0	0
T27	148021	0	0	0
T29	304385	0	0	0
T33	0	294	0	0
T34	0	227	0	0
T35	272455	0	0	0
T36	149007	0	0	0
T37	248031	0	0	0
T38	31261	0	0	0
T39	437058	0	0	0
T40	32922	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680306184	680236745	0	0
T1	973479	973415	0	0
T2	65054	64970	0	0
T3	38688	38637	0	0
T4	468891	468875	0	0
T7	694823	694730	0	0
T8	237017	236922	0	0
T12	85884	85802	0	0
T13	464318	464259	0	0
T14	1532	1437	0	0
T20	39516	39459	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	680415214	0	0
T1	973479	973415	0	0
T2	65054	64970	0	0
T3	38688	38637	0	0
T4	468891	468875	0	0
T7	694823	694730	0	0
T8	237017	236922	0	0
T12	85884	85802	0	0
T13	464318	464259	0	0
T14	1532	1437	0	0
T20	39516	39459	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T13,T8
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T12

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T12
0	1	Covered	T26,T70,T23
1	0	Covered	T6,T68,T110

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T68,T110

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T22
1	1	Covered	T26,T70,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T13
1	Covered	T4,T45,T26

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T13
1	Covered	T6,T43,T45

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T13
1	Covered	T20,T6,T45

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T20,T6
1	Covered	T1,T4,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T6,T43

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T13,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T13,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T13
Phase1St	198	Covered	T1,T4,T13
Phase2St	215	Covered	T1,T4,T13
Phase3St	233	Covered	T1,T4,T13
TerminalSt	249	Covered	T1,T4,T13
TimeoutSt	159	Covered	T2,T3,T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T4,T13
IdleSt->TimeoutSt	159	Covered	T2,T3,T12
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T23,T32,T81
Phase0St->Phase1St	198	Covered	T1,T4,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T1,T17,T21
Phase1St->Phase2St	215	Covered	T1,T4,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T4,T6,T93
Phase2St->Phase3St	233	Covered	T1,T4,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T111,T93,T112
Phase3St->TerminalSt	249	Covered	T1,T4,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T3,T12
TimeoutSt->Phase0St	172	Covered	T6,T26,T68

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T26,T68
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T81,T113
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T17,T21
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T93,T84,T114
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T111,T93,T112
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T20,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	680599942	293	0	0
CheckAccumTrig0_A	680599942	505	0	0
CheckAccumTrig1_A	680599942	23	0	0
CheckClr_A	680599942	238	0	0
CheckEn_A	680307615	296266127	0	0
CheckPhase0_A	680599942	590	0	0
CheckPhase1_A	680599942	577	0	0
CheckPhase2_A	680599942	564	0	0
CheckPhase3_A	680599942	553	0	0
CheckTimeout0_A	680599942	1947	0	0
CheckTimeoutSt1_A	680599942	218059	0	0
CheckTimeoutSt2_A	680599942	1854	0	0
CheckTimeoutStTrig_A	680599942	68	0	0
ErrorStAllEscAsserted_A	680599942	1481	0	0
ErrorStIsTerminal_A	680599942	1211	0	0
EscStateOut_A	680306184	680236745	0	0
u_state_regs_A	680599942	680415214	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	293	0	0
T9	20546	23	0	0
T10	0	73	0	0
T11	0	57	0	0
T25	367942	0	0	0
T27	148021	0	0	0
T29	304385	0	0	0
T33	0	70	0	0
T34	0	70	0	0
T35	272455	0	0	0
T36	149007	0	0	0
T37	248031	0	0	0
T38	31261	0	0	0
T39	437058	0	0	0
T40	32922	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	505	0	0
T1	973479	4	0	0
T2	65054	0	0	0
T3	38688	0	0	0
T4	468891	3	0	0
T6	0	2	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T16	0	1	0	0
T17	0	2	0	0
T20	39516	2	0	0
T26	0	1	0	0
T43	0	1	0	0
T45	0	4	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	23	0	0
T6	118984	1	0	0
T15	17764	0	0	0
T24	200838	0	0	0
T28	0	1	0	0
T31	0	1	0	0
T42	34626	0	0	0
T43	15153	0	0	0
T44	25809	0	0	0
T45	312473	0	0	0
T46	144474	0	0	0
T47	4592	0	0	0
T68	0	2	0	0
T76	4525	0	0	0
T93	0	2	0	0
T105	0	1	0	0
T107	0	1	0	0
T110	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	238	0	0
T1	973479	3	0	0
T2	65054	0	0	0
T3	38688	0	0	0
T4	468891	0	0	0
T6	0	2	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T17	0	1	0	0
T20	39516	1	0	0
T21	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0
T30	0	2	0	0
T45	0	1	0	0
T68	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680307615	296266127	0	0
T1	973479	76402	0	0
T2	65054	61259	0	0
T3	38688	35407	0	0
T4	468891	341072	0	0
T7	694823	694729	0	0
T8	237017	599	0	0
T12	85884	55175	0	0
T13	464318	16876	0	0
T14	1532	1436	0	0
T20	39516	14392	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	590	0	0
T1	973479	4	0	0
T2	65054	0	0	0
T3	38688	0	0	0
T4	468891	3	0	0
T6	0	3	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T16	0	1	0	0
T17	0	2	0	0
T20	39516	2	0	0
T26	0	3	0	0
T43	0	1	0	0
T45	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	577	0	0
T1	973479	2	0	0
T2	65054	0	0	0
T3	38688	0	0	0
T4	468891	3	0	0
T6	0	3	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	39516	2	0	0
T26	0	3	0	0
T43	0	1	0	0
T45	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	564	0	0
T1	973479	2	0	0
T2	65054	0	0	0
T3	38688	0	0	0
T4	468891	2	0	0
T6	0	2	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	39516	2	0	0
T26	0	3	0	0
T43	0	1	0	0
T45	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	553	0	0
T1	973479	2	0	0
T2	65054	0	0	0
T3	38688	0	0	0
T4	468891	2	0	0
T6	0	2	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	0	0	0
T13	464318	1	0	0
T14	1532	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	39516	2	0	0
T26	0	3	0	0
T43	0	1	0	0
T45	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1947	0	0
T2	65054	1	0	0
T3	38688	1	0	0
T4	468891	0	0	0
T5	38544	0	0	0
T6	0	1	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	1	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	1	0	0
T24	0	1	0	0
T26	0	213	0	0
T29	0	1	0	0
T45	0	2	0	0
T73	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	218059	0	0
T2	65054	151	0	0
T3	38688	111	0	0
T4	468891	0	0	0
T5	38544	0	0	0
T6	0	1	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	163	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	114	0	0
T24	0	109	0	0
T26	0	25955	0	0
T29	0	118	0	0
T45	0	115	0	0
T73	0	342	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1854	0	0
T2	65054	1	0	0
T3	38688	1	0	0
T4	468891	0	0	0
T5	38544	0	0	0
T7	694823	0	0	0
T8	237017	0	0	0
T12	85884	1	0	0
T13	464318	0	0	0
T14	1532	0	0	0
T20	39516	1	0	0
T21	0	16	0	0
T24	0	1	0	0
T26	0	211	0	0
T29	0	1	0	0
T45	0	2	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	68	0	0
T9	20546	0	0	0
T16	763504	0	0	0
T17	299418	0	0	0
T18	108152	0	0	0
T19	104225	0	0	0
T22	0	2	0	0
T23	0	1	0	0
T26	445387	2	0	0
T28	0	1	0	0
T35	272455	0	0	0
T50	0	1	0	0
T52	0	1	0	0
T70	0	1	0	0
T77	79764	0	0	0
T78	86848	0	0	0
T80	0	2	0	0
T81	0	3	0	0
T85	257223	0	0	0
T117	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1481	0	0
T9	20546	169	0	0
T10	0	333	0	0
T11	0	310	0	0
T25	367942	0	0	0
T27	148021	0	0	0
T29	304385	0	0	0
T33	0	333	0	0
T34	0	336	0	0
T35	272455	0	0	0
T36	149007	0	0	0
T37	248031	0	0	0
T38	31261	0	0	0
T39	437058	0	0	0
T40	32922	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	1211	0	0
T9	20546	139	0	0
T10	0	273	0	0
T11	0	250	0	0
T25	367942	0	0	0
T27	148021	0	0	0
T29	304385	0	0	0
T33	0	273	0	0
T34	0	276	0	0
T35	272455	0	0	0
T36	149007	0	0	0
T37	248031	0	0	0
T38	31261	0	0	0
T39	437058	0	0	0
T40	32922	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680306184	680236745	0	0
T1	973479	973415	0	0
T2	65054	64970	0	0
T3	38688	38637	0	0
T4	468891	468875	0	0
T7	694823	694730	0	0
T8	237017	236922	0	0
T12	85884	85802	0	0
T13	464318	464259	0	0
T14	1532	1437	0	0
T20	39516	39459	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680599942	680415214	0	0
T1	973479	973415	0	0
T2	65054	64970	0	0
T3	38688	38637	0	0
T4	468891	468875	0	0
T7	694823	694730	0	0
T8	237017	236922	0	0
T12	85884	85802	0	0
T13	464318	464259	0	0
T14	1532	1437	0	0
T20	39516	39459	0	0