Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T67,T91
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T12

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15333	0	0
DisabledNoTrigBkwd_A	2147483647	765692	0	0
DisabledNoTrigFwd_A	2147483647	1608545978	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15333	0	0
T26	17982	0	0	0
T48	2902	399	0	0
T54	343791	0	0	0
T67	0	706	0	0
T78	28862	0	0	0
T91	0	1001	0	0
T95	36625	0	0	0
T115	20220	0	0	0
T124	763090	0	0	0
T133	33538	0	0	0
T198	91481	0	0	0
T199	22335	0	0	0
T200	475934	0	0	0
T201	94990	0	0	0
T202	79806	0	0	0
T203	134433	0	0	0
T204	61004	0	0	0
T219	3182	853	0	0
T220	0	284	0	0
T221	0	1223	0	0
T222	0	282	0	0
T223	0	705	0	0
T224	4837	1333	0	0
T225	0	1462	0	0
T226	0	687	0	0
T227	0	786	0	0
T228	0	997	0	0
T229	0	527	0	0
T230	0	1254	0	0
T231	0	452	0	0
T232	0	471	0	0
T233	0	833	0	0
T234	0	348	0	0
T235	0	730	0	0
T236	109349	0	0	0
T237	349191	0	0	0
T238	148173	0	0	0
T239	893096	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	765692	0	0
T1	320549	1	0	0
T2	35024	0	0	0
T3	157322	47	0	0
T4	629752	270	0	0
T5	0	1774	0	0
T7	1140272	914	0	0
T8	976500	6811	0	0
T12	53864	53	0	0
T13	162996	0	0	0
T14	799128	15	0	0
T15	297384	460	0	0
T16	0	560	0	0
T19	486456	13352	0	0
T20	0	5401	0	0
T22	204568	212	0	0
T23	0	6	0	0
T45	644769	1	0	0
T46	196916	70	0	0
T47	28598	23	0	0
T48	0	9	0	0
T49	0	3	0	0
T50	0	23	0	0
T51	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1608545978	0	0
T1	1282196	413638	0	0
T2	140096	96172	0	0
T3	314644	237472	0	0
T7	2280544	1160791	0	0
T8	976500	340904	0	0
T12	107728	82811	0	0
T13	162996	39174	0	0
T14	799128	794092	0	0
T15	297384	170943	0	0
T22	204568	149155	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T12,T8
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T219,T220,T225
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T12,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	695263121	5885	0	0
DisabledNoTrigBkwd_A	695263121	213197	0	0
DisabledNoTrigFwd_A	695263121	356909686	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	5885	0	0
T26	17982	0	0	0
T54	343791	0	0	0
T78	28862	0	0	0
T95	36625	0	0	0
T115	20220	0	0	0
T133	33538	0	0	0
T219	3182	853	0	0
T220	0	284	0	0
T225	0	1462	0	0
T226	0	687	0	0
T228	0	997	0	0
T230	0	1254	0	0
T234	0	348	0	0
T236	109349	0	0	0
T237	349191	0	0	0
T238	148173	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	213197	0	0
T3	78661	47	0	0
T4	0	118	0	0
T7	570136	914	0	0
T8	244125	16	0	0
T12	26932	53	0	0
T13	40749	0	0	0
T14	199782	4	0	0
T15	74346	15	0	0
T19	162152	3	0	0
T22	51142	0	0	0
T45	214923	0	0	0
T46	0	34	0	0
T47	0	15	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	356909686	0	0
T1	320549	45514	0	0
T2	35024	582	0	0
T3	78661	14491	0	0
T7	570136	10245	0	0
T8	244125	242224	0	0
T12	26932	2186	0	0
T13	40749	614	0	0
T14	199782	199290	0	0
T15	74346	25510	0	0
T22	51142	51063	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T13
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T8,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T224,T227,T231
1	1	Covered	T2,T8,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T14,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	695263121	3042	0	0
DisabledNoTrigBkwd_A	695263121	177840	0	0
DisabledNoTrigFwd_A	695263121	423685676	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	3042	0	0
T124	763090	0	0	0
T198	91481	0	0	0
T199	22335	0	0	0
T200	475934	0	0	0
T201	94990	0	0	0
T202	79806	0	0	0
T203	134433	0	0	0
T204	61004	0	0	0
T224	4837	1333	0	0
T227	0	786	0	0
T231	0	452	0	0
T232	0	471	0	0
T239	893096	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	177840	0	0
T4	314876	43	0	0
T8	244125	4124	0	0
T13	40749	0	0	0
T14	199782	5	0	0
T15	74346	0	0	0
T16	0	560	0	0
T19	162152	5	0	0
T20	0	5399	0	0
T22	51142	0	0	0
T23	0	6	0	0
T45	214923	0	0	0
T46	98458	6	0	0
T47	14299	0	0	0
T50	0	23	0	0
T51	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	423685676	0	0
T1	320549	320451	0	0
T2	35024	31246	0	0
T3	78661	78589	0	0
T7	570136	570129	0	0
T8	244125	26560	0	0
T12	26932	26875	0	0
T13	40749	618	0	0
T14	199782	198050	0	0
T15	74346	74283	0	0
T22	51142	51063	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T91,T222
1	1	Covered	T1,T2,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	695263121	3747	0	0
DisabledNoTrigBkwd_A	695263121	201137	0	0
DisabledNoTrigFwd_A	695263121	382365075	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	3747	0	0
T5	130303	0	0	0
T6	119121	0	0	0
T16	275928	0	0	0
T21	115482	0	0	0
T32	19677	0	0	0
T48	2902	399	0	0
T49	26002	0	0	0
T50	19708	0	0	0
T62	19551	0	0	0
T63	59363	0	0	0
T91	0	1001	0	0
T222	0	282	0	0
T223	0	705	0	0
T229	0	527	0	0
T233	0	833	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	201137	0	0
T1	320549	1	0	0
T2	35024	0	0	0
T3	78661	0	0	0
T4	0	6	0	0
T5	0	1774	0	0
T7	570136	0	0	0
T8	244125	1405	0	0
T12	26932	0	0	0
T13	40749	0	0	0
T14	199782	6	0	0
T15	74346	444	0	0
T19	0	16	0	0
T22	51142	200	0	0
T46	0	24	0	0
T48	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	382365075	0	0
T1	320549	2114	0	0
T2	35024	32066	0	0
T3	78661	72198	0	0
T7	570136	570129	0	0
T8	244125	40027	0	0
T12	26932	26875	0	0
T13	40749	37316	0	0
T14	199782	197669	0	0
T15	74346	2161	0	0
T22	51142	43886	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T7,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T67,T221,T235
1	1	Covered	T2,T7,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T15,T22

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	695263121	2659	0	0
DisabledNoTrigBkwd_A	695263121	173518	0	0
DisabledNoTrigFwd_A	695263121	445585541	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	2659	0	0
T18	101276	0	0	0
T25	149547	0	0	0
T67	3039	706	0	0
T68	201281	0	0	0
T69	231261	0	0	0
T70	15482	0	0	0
T75	12333	0	0	0
T88	53956	0	0	0
T89	20270	0	0	0
T90	130457	0	0	0
T221	0	1223	0	0
T235	0	730	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	173518	0	0
T4	314876	103	0	0
T8	244125	1266	0	0
T13	40749	0	0	0
T14	199782	0	0	0
T15	74346	1	0	0
T19	162152	13328	0	0
T20	0	2	0	0
T22	51142	12	0	0
T45	214923	1	0	0
T46	98458	6	0	0
T47	14299	8	0	0
T49	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	445585541	0	0
T1	320549	45559	0	0
T2	35024	32278	0	0
T3	78661	72194	0	0
T7	570136	10288	0	0
T8	244125	32093	0	0
T12	26932	26875	0	0
T13	40749	626	0	0
T14	199782	199083	0	0
T15	74346	68989	0	0
T22	51142	3143	0	0