Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T12
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T2,T12,T15
1	1	1	Covered	T2,T12,T8

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T8
0	1	Covered	T8,T13,T19
1	0	Covered	T20,T23,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T12,T8
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T20,T23,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T8
1	0	Not Covered
1	1	Covered	T8,T13,T19

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T8
1	Covered	T1,T7,T8

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T8,T15,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T12,T7
1	Covered	T3,T12,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T12,T13,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T12,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T8,T15

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T12
Phase1St	198	Covered	T1,T3,T12
Phase2St	215	Covered	T1,T3,T12
Phase3St	233	Covered	T1,T3,T12
TerminalSt	249	Covered	T1,T3,T12
TimeoutSt	159	Covered	T2,T12,T8

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T3,T12
IdleSt->TimeoutSt	159	Covered	T2,T12,T8
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T25,T26,T27
Phase0St->Phase1St	198	Covered	T1,T3,T12
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T28,T29,T30
Phase1St->Phase2St	215	Covered	T1,T3,T12
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T27,T31,T28
Phase2St->Phase3St	233	Covered	T1,T3,T12
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T16,T32,T33
Phase3St->TerminalSt	249	Covered	T1,T3,T12
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T12,T8,T15
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T12,T13
TimeoutSt->Phase0St	172	Covered	T8,T13,T19

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T8
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T26,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T29,T30
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T31,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T32,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T8,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	951	0	0
CheckAccumTrig0_A	2147483647	2321	0	0
CheckAccumTrig1_A	2147483647	120	0	0
CheckClr_A	2147483647	1088	0	0
CheckEn_A	2147483647	1237525643	0	0
CheckPhase0_A	2147483647	2707	0	0
CheckPhase1_A	2147483647	2661	0	0
CheckPhase2_A	2147483647	2604	0	0
CheckPhase3_A	2147483647	2560	0	0
CheckTimeout0_A	2147483647	6303	0	0
CheckTimeoutSt1_A	2147483647	651771	0	0
CheckTimeoutSt2_A	2147483647	5871	0	0
CheckTimeoutStTrig_A	2147483647	302	0	0
ErrorStAllEscAsserted_A	2147483647	5039	0	0
ErrorStIsTerminal_A	2147483647	4079	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	951	0	0
T9	171956	287	0	0
T10	0	118	0	0
T11	0	102	0	0
T34	0	239	0	0
T35	0	205	0	0
T36	822008	0	0	0
T37	127012	0	0	0
T38	3333856	0	0	0
T39	237240	0	0	0
T40	30144	0	0	0
T41	21448	0	0	0
T42	132048	0	0	0
T43	3501364	0	0	0
T44	2534148	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2321	0	0
T1	320549	1	0	0
T2	35024	0	0	0
T3	157322	1	0	0
T4	629752	8	0	0
T5	0	2	0	0
T7	1140272	1	0	0
T8	976500	4	0	0
T12	53864	3	0	0
T13	162996	0	0	0
T14	799128	3	0	0
T15	297384	6	0	0
T16	0	2	0	0
T19	486456	3	0	0
T20	0	3	0	0
T22	204568	2	0	0
T23	0	1	0	0
T45	644769	1	0	0
T46	196916	5	0	0
T47	28598	4	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	120	0	0
T5	130303	0	0	0
T6	119121	0	0	0
T16	275928	0	0	0
T17	382053	0	0	0
T20	126273	5	0	0
T21	115482	0	0	0
T23	11008	1	0	0
T24	0	1	0	0
T25	149547	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	3	0	0
T31	0	5	0	0
T32	19677	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T44	0	2	0	0
T48	2902	0	0	0
T49	26002	0	0	0
T52	116258	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	19551	0	0	0
T63	59363	0	0	0
T64	185641	0	0	0
T65	27155	0	0	0
T66	112650	0	0	0
T67	3039	0	0	0
T68	201281	0	0	0
T69	231261	0	0	0
T70	15482	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1088	0	0
T4	314876	1	0	0
T5	130303	2	0	0
T6	119121	0	0	0
T7	570136	0	0	0
T8	244125	1	0	0
T12	26932	2	0	0
T13	81498	3	0	0
T14	399564	0	0	0
T15	148692	3	0	0
T16	275928	1	0	0
T19	324304	1	0	0
T20	252546	6	0	0
T21	115482	0	0	0
T22	102284	0	0	0
T23	0	1	0	0
T32	19677	0	0	0
T33	0	2	0	0
T45	429846	0	0	0
T46	196916	1	0	0
T47	0	1	0	0
T48	2902	0	0	0
T49	26002	0	0	0
T51	0	5	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	2	0	0
T62	19551	0	0	0
T63	59363	0	0	0
T64	0	3	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1237525643	0	0
T1	1282196	413637	0	0
T2	140096	96169	0	0
T3	314644	237469	0	0
T7	2280544	1160791	0	0
T8	976500	34945	0	0
T12	107728	82808	0	0
T13	162996	39173	0	0
T14	799128	215971	0	0
T15	297384	155635	0	0
T22	204568	108393	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2707	0	0
T1	320549	1	0	0
T2	35024	0	0	0
T3	157322	1	0	0
T4	629752	9	0	0
T5	0	2	0	0
T7	1140272	1	0	0
T8	976500	5	0	0
T12	53864	3	0	0
T13	162996	3	0	0
T14	799128	3	0	0
T15	297384	6	0	0
T16	0	1	0	0
T19	486456	4	0	0
T20	0	8	0	0
T22	204568	2	0	0
T23	0	1	0	0
T45	644769	1	0	0
T46	196916	5	0	0
T47	28598	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2661	0	0
T1	320549	1	0	0
T2	35024	0	0	0
T3	157322	1	0	0
T4	629752	9	0	0
T5	0	2	0	0
T7	1140272	1	0	0
T8	976500	5	0	0
T12	53864	3	0	0
T13	162996	3	0	0
T14	799128	3	0	0
T15	297384	6	0	0
T16	0	1	0	0
T19	486456	4	0	0
T20	0	8	0	0
T22	204568	2	0	0
T23	0	1	0	0
T45	644769	1	0	0
T46	196916	5	0	0
T47	28598	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2604	0	0
T1	320549	1	0	0
T2	35024	0	0	0
T3	157322	1	0	0
T4	629752	9	0	0
T5	0	2	0	0
T7	1140272	1	0	0
T8	976500	5	0	0
T12	53864	3	0	0
T13	162996	3	0	0
T14	799128	3	0	0
T15	297384	6	0	0
T16	0	1	0	0
T19	486456	4	0	0
T20	0	8	0	0
T22	204568	2	0	0
T23	0	1	0	0
T45	644769	1	0	0
T46	196916	5	0	0
T47	28598	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2560	0	0
T1	320549	1	0	0
T2	35024	0	0	0
T3	157322	1	0	0
T4	629752	9	0	0
T5	0	2	0	0
T7	1140272	1	0	0
T8	976500	5	0	0
T12	53864	3	0	0
T13	162996	3	0	0
T14	799128	3	0	0
T15	297384	6	0	0
T16	0	1	0	0
T19	486456	4	0	0
T20	0	7	0	0
T22	204568	2	0	0
T23	0	2	0	0
T45	644769	1	0	0
T46	196916	5	0	0
T47	28598	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6303	0	0
T2	70048	12	0	0
T3	157322	0	0	0
T4	629752	5	0	0
T5	130303	0	0	0
T7	1140272	0	0	0
T8	488250	1	0	0
T12	53864	1	0	0
T13	122247	21	0	0
T14	599346	0	0	0
T15	148692	0	0	0
T16	275928	0	0	0
T19	648608	2	0	0
T20	252546	7	0	0
T21	115482	0	0	0
T22	153426	0	0	0
T23	0	1	0	0
T24	0	3	0	0
T25	0	20	0	0
T45	429846	0	0	0
T46	196916	2	0	0
T47	28598	1	0	0
T48	5804	0	0	0
T52	0	15	0	0
T53	0	2	0	0
T69	0	1	0	0
T70	0	7	0	0
T74	0	11	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	3	0	0
T78	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	651771	0	0
T2	70048	1931	0	0
T3	157322	0	0	0
T4	629752	687	0	0
T5	130303	0	0	0
T7	1140272	0	0	0
T8	488250	8	0	0
T12	53864	85	0	0
T13	122247	1928	0	0
T14	599346	0	0	0
T15	148692	0	0	0
T16	275928	0	0	0
T19	648608	68	0	0
T20	252546	90	0	0
T21	115482	0	0	0
T22	153426	0	0	0
T24	0	429	0	0
T25	0	1364	0	0
T45	429846	0	0	0
T46	196916	384	0	0
T47	28598	68	0	0
T48	5804	0	0	0
T52	0	907	0	0
T53	0	84	0	0
T54	0	389	0	0
T69	0	32	0	0
T70	0	345	0	0
T74	0	695	0	0
T75	0	115	0	0
T76	0	282	0	0
T77	0	803	0	0
T78	0	540	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5871	0	0
T2	35024	12	0	0
T3	78661	0	0	0
T4	629752	4	0	0
T5	130303	0	0	0
T7	570136	0	0	0
T8	244125	0	0	0
T12	26932	1	0	0
T13	81498	18	0	0
T14	399564	0	0	0
T15	74346	0	0	0
T16	275928	0	0	0
T19	324304	1	0	0
T20	252546	2	0	0
T21	115482	0	0	0
T22	102284	0	0	0
T24	0	1	0	0
T25	0	18	0	0
T32	19677	0	0	0
T45	214923	0	0	0
T46	196916	2	0	0
T47	28598	1	0	0
T48	5804	0	0	0
T52	0	13	0	0
T53	0	3	0	0
T54	0	3	0	0
T62	19551	0	0	0
T69	0	1	0	0
T70	0	7	0	0
T73	0	1	0	0
T74	0	11	0	0
T75	0	1	0	0
T76	0	5	0	0
T77	0	6	0	0
T78	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	302	0	0
T4	629752	0	0	0
T8	244125	1	0	0
T13	40749	3	0	0
T14	199782	0	0	0
T15	74346	0	0	0
T18	101276	0	0	0
T19	324304	1	0	0
T20	126273	0	0	0
T22	51142	0	0	0
T24	0	1	0	0
T25	149547	2	0	0
T29	0	6	0	0
T33	64710	0	0	0
T36	0	1	0	0
T44	0	2	0	0
T45	429846	0	0	0
T46	196916	0	0	0
T47	28598	0	0	0
T56	0	1	0	0
T58	0	4	0	0
T73	27093	0	0	0
T75	12333	0	0	0
T76	4680	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	8	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	53956	0	0	0
T89	20270	0	0	0
T90	130457	0	0	0
T91	3365	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5039	0	0
T9	171956	1243	0	0
T10	0	631	0	0
T11	0	631	0	0
T34	0	1271	0	0
T35	0	1263	0	0
T36	822008	0	0	0
T37	127012	0	0	0
T38	3333856	0	0	0
T39	237240	0	0	0
T40	30144	0	0	0
T41	21448	0	0	0
T42	132048	0	0	0
T43	3501364	0	0	0
T44	2534148	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4079	0	0
T9	171956	1003	0	0
T10	0	511	0	0
T11	0	511	0	0
T34	0	1031	0	0
T35	0	1023	0	0
T36	822008	0	0	0
T37	127012	0	0	0
T38	3333856	0	0	0
T39	237240	0	0	0
T40	30144	0	0	0
T41	21448	0	0	0
T42	132048	0	0	0
T43	3501364	0	0	0
T44	2534148	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1282196	1281804	0	0
T2	140096	139860	0	0
T3	314644	314356	0	0
T7	2280544	2280516	0	0
T8	976500	976480	0	0
T12	107728	107500	0	0
T13	162996	162760	0	0
T14	799128	799100	0	0
T15	297384	297132	0	0
T22	204568	204252	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1282196	1281804	0	0
T2	140096	139860	0	0
T3	314644	314356	0	0
T7	2280544	2280516	0	0
T8	976500	976480	0	0
T12	107728	107500	0	0
T13	162996	162760	0	0
T14	799128	799100	0	0
T15	297384	297132	0	0
T22	204568	204252	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T12,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T12
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T12,T15,T22
1	1	1	Covered	T2,T12,T8

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T8
0	1	Covered	T8,T13,T25
1	0	Covered	T52,T26,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T12,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T52,T26,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T8
1	0	Not Covered
1	1	Covered	T8,T13,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T8
1	Covered	T7,T8,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T7
1	Covered	T8,T15,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T7,T8
1	Covered	T3,T12,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T7
1	Covered	T12,T13,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T8,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T8,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T12,T7
Phase1St	198	Covered	T3,T12,T7
Phase2St	215	Covered	T3,T12,T7
Phase3St	233	Covered	T3,T12,T7
TerminalSt	249	Covered	T3,T12,T7
TimeoutSt	159	Covered	T2,T12,T8

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T3,T12,T7
IdleSt->TimeoutSt	159	Covered	T2,T12,T8
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T25,T92,T38
Phase0St->Phase1St	198	Covered	T3,T12,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T93,T94
Phase1St->Phase2St	215	Covered	T3,T12,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T31,T28
Phase2St->Phase3St	233	Covered	T3,T12,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T16,T32,T95
Phase3St->TerminalSt	249	Covered	T3,T12,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T12,T8,T15
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T12,T13
TimeoutSt->Phase0St	172	Covered	T8,T13,T52

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T8
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T52
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T92,T38
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T12,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T12,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T93,T94
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T12,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T12,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T31,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T12,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T12,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T32,T95
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T12,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T12,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T8,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T12,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	695263121	238	0	0
CheckAccumTrig0_A	695263121	837	0	0
CheckAccumTrig1_A	695263121	37	0	0
CheckClr_A	695263121	390	0	0
CheckEn_A	695102115	256063556	0	0
CheckPhase0_A	695263121	943	0	0
CheckPhase1_A	695263121	926	0	0
CheckPhase2_A	695263121	899	0	0
CheckPhase3_A	695263121	887	0	0
CheckTimeout0_A	695263121	1239	0	0
CheckTimeoutSt1_A	695263121	142715	0	0
CheckTimeoutSt2_A	695263121	1117	0	0
CheckTimeoutStTrig_A	695263121	84	0	0
ErrorStAllEscAsserted_A	695263121	1275	0	0
ErrorStIsTerminal_A	695263121	1035	0	0
EscStateOut_A	695100578	695028611	0	0
u_state_regs_A	695263121	695089685	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	238	0	0
T9	42989	62	0	0
T10	0	39	0	0
T11	0	30	0	0
T34	0	66	0	0
T35	0	41	0	0
T36	205502	0	0	0
T37	31753	0	0	0
T38	833464	0	0	0
T39	59310	0	0	0
T40	7536	0	0	0
T41	5362	0	0	0
T42	33012	0	0	0
T43	875341	0	0	0
T44	633537	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	837	0	0
T3	78661	1	0	0
T4	0	3	0	0
T7	570136	1	0	0
T8	244125	1	0	0
T12	26932	3	0	0
T13	40749	0	0	0
T14	199782	1	0	0
T15	74346	2	0	0
T19	162152	1	0	0
T22	51142	0	0	0
T45	214923	0	0	0
T46	0	2	0	0
T47	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	37	0	0
T17	382053	0	0	0
T25	149547	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	5	0	0
T52	116258	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T64	185641	0	0	0
T65	27155	0	0	0
T66	112650	0	0	0
T67	3039	0	0	0
T68	201281	0	0	0
T69	231261	0	0	0
T70	15482	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	390	0	0
T4	0	1	0	0
T5	0	1	0	0
T7	570136	0	0	0
T8	244125	1	0	0
T12	26932	2	0	0
T13	40749	3	0	0
T14	199782	0	0	0
T15	74346	1	0	0
T16	0	1	0	0
T19	162152	1	0	0
T22	51142	0	0	0
T45	214923	0	0	0
T46	98458	1	0	0
T47	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695102115	256063556	0	0
T1	320549	45514	0	0
T2	35024	582	0	0
T3	78661	14491	0	0
T7	570136	10245	0	0
T8	244125	5691	0	0
T12	26932	2186	0	0
T13	40749	614	0	0
T14	199782	5618	0	0
T15	74346	11660	0	0
T22	51142	51062	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	943	0	0
T3	78661	1	0	0
T4	0	3	0	0
T7	570136	1	0	0
T8	244125	2	0	0
T12	26932	3	0	0
T13	40749	3	0	0
T14	199782	1	0	0
T15	74346	2	0	0
T19	162152	1	0	0
T22	51142	0	0	0
T45	214923	0	0	0
T46	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	926	0	0
T3	78661	1	0	0
T4	0	3	0	0
T7	570136	1	0	0
T8	244125	2	0	0
T12	26932	3	0	0
T13	40749	3	0	0
T14	199782	1	0	0
T15	74346	2	0	0
T19	162152	1	0	0
T22	51142	0	0	0
T45	214923	0	0	0
T46	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	899	0	0
T3	78661	1	0	0
T4	0	3	0	0
T7	570136	1	0	0
T8	244125	2	0	0
T12	26932	3	0	0
T13	40749	3	0	0
T14	199782	1	0	0
T15	74346	2	0	0
T19	162152	1	0	0
T22	51142	0	0	0
T45	214923	0	0	0
T46	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	887	0	0
T3	78661	1	0	0
T4	0	3	0	0
T7	570136	1	0	0
T8	244125	2	0	0
T12	26932	3	0	0
T13	40749	3	0	0
T14	199782	1	0	0
T15	74346	2	0	0
T19	162152	1	0	0
T22	51142	0	0	0
T45	214923	0	0	0
T46	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1239	0	0
T2	35024	11	0	0
T3	78661	0	0	0
T7	570136	0	0	0
T8	244125	1	0	0
T12	26932	1	0	0
T13	40749	7	0	0
T14	199782	0	0	0
T15	74346	0	0	0
T19	162152	0	0	0
T22	51142	0	0	0
T25	0	3	0	0
T46	0	1	0	0
T52	0	3	0	0
T70	0	4	0	0
T74	0	3	0	0
T76	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	142715	0	0
T2	35024	1678	0	0
T3	78661	0	0	0
T7	570136	0	0	0
T8	244125	8	0	0
T12	26932	85	0	0
T13	40749	510	0	0
T14	199782	0	0	0
T15	74346	0	0	0
T19	162152	0	0	0
T22	51142	0	0	0
T25	0	228	0	0
T46	0	192	0	0
T52	0	203	0	0
T70	0	199	0	0
T74	0	184	0	0
T76	0	96	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1117	0	0
T2	35024	11	0	0
T3	78661	0	0	0
T7	570136	0	0	0
T8	244125	0	0	0
T12	26932	1	0	0
T13	40749	4	0	0
T14	199782	0	0	0
T15	74346	0	0	0
T19	162152	0	0	0
T22	51142	0	0	0
T25	0	2	0	0
T46	0	1	0	0
T52	0	2	0	0
T70	0	4	0	0
T73	0	1	0	0
T74	0	3	0	0
T76	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	84	0	0
T4	314876	0	0	0
T8	244125	1	0	0
T13	40749	3	0	0
T14	199782	0	0	0
T15	74346	0	0	0
T19	162152	0	0	0
T22	51142	0	0	0
T25	0	1	0	0
T29	0	2	0	0
T36	0	1	0	0
T45	214923	0	0	0
T46	98458	0	0	0
T47	14299	0	0	0
T58	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	2	0	0
T86	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1275	0	0
T9	42989	308	0	0
T10	0	158	0	0
T11	0	178	0	0
T34	0	319	0	0
T35	0	312	0	0
T36	205502	0	0	0
T37	31753	0	0	0
T38	833464	0	0	0
T39	59310	0	0	0
T40	7536	0	0	0
T41	5362	0	0	0
T42	33012	0	0	0
T43	875341	0	0	0
T44	633537	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1035	0	0
T9	42989	248	0	0
T10	0	128	0	0
T11	0	148	0	0
T34	0	259	0	0
T35	0	252	0	0
T36	205502	0	0	0
T37	31753	0	0	0
T38	833464	0	0	0
T39	59310	0	0	0
T40	7536	0	0	0
T41	5362	0	0	0
T42	33012	0	0	0
T43	875341	0	0	0
T44	633537	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695100578	695028611	0	0
T1	320549	320451	0	0
T2	35024	34965	0	0
T3	78661	78589	0	0
T7	570136	570129	0	0
T8	244125	244120	0	0
T12	26932	26875	0	0
T13	40749	40690	0	0
T14	199782	199775	0	0
T15	74346	74283	0	0
T22	51142	51063	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	695089685	0	0
T1	320549	320451	0	0
T2	35024	34965	0	0
T3	78661	78589	0	0
T7	570136	570129	0	0
T8	244125	244120	0	0
T12	26932	26875	0	0
T13	40749	40690	0	0
T14	199782	199775	0	0
T15	74346	74283	0	0
T22	51142	51063	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T8,T13,T14
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T13,T14

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T8,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T8,T14,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T8,T13
1	0	1	Covered	T4,T16,T49
1	1	0	Covered	T2,T15,T22
1	1	1	Covered	T13,T19,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T19,T4
0	1	Covered	T25,T77,T80
1	0	Covered	T20,T53,T27

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T19,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T53,T27

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T19,T4
1	0	Not Covered
1	1	Covered	T25,T77,T80

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T14,T19,T46
1	Covered	T8,T96,T52

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T8,T14,T19
1	Covered	T4,T51,T23

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T8,T14,T4
1	Covered	T19,T46,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T8,T19,T46
1	Covered	T14,T50,T52

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T14,T4,T71

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T8,T19,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T14,T46,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T14,T19,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T8,T14,T19
Phase1St	198	Covered	T8,T14,T19
Phase2St	215	Covered	T8,T14,T19
Phase3St	233	Covered	T8,T14,T19
TerminalSt	249	Covered	T8,T14,T19
TimeoutSt	159	Covered	T13,T19,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T8,T14,T19
IdleSt->TimeoutSt	159	Covered	T13,T19,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T97,T98,T99
Phase0St->Phase1St	198	Covered	T8,T14,T19
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T100,T101
Phase1St->Phase2St	215	Covered	T8,T14,T19
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T102,T103,T104
Phase2St->Phase3St	233	Covered	T8,T14,T19
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T33,T82,T29
Phase3St->TerminalSt	249	Covered	T8,T14,T19
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T20,T51
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T19,T4
TimeoutSt->Phase0St	172	Covered	T20,T25,T77

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T14,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T19,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T25,T77
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T19,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T19,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T97,T98,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T8,T14,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T8,T14,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T100,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T8,T14,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T8,T14,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T102,T103,T104
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T8,T14,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T8,T14,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T82,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T8,T14,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T8,T14,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T51,T71
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T14,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	695263121	247	0	0
CheckAccumTrig0_A	695263121	509	0	0
CheckAccumTrig1_A	695263121	30	0	0
CheckClr_A	695263121	262	0	0
CheckEn_A	695102115	326983737	0	0
CheckPhase0_A	695263121	618	0	0
CheckPhase1_A	695263121	605	0	0
CheckPhase2_A	695263121	599	0	0
CheckPhase3_A	695263121	586	0	0
CheckTimeout0_A	695263121	1959	0	0
CheckTimeoutSt1_A	695263121	192486	0	0
CheckTimeoutSt2_A	695263121	1838	0	0
CheckTimeoutStTrig_A	695263121	88	0	0
ErrorStAllEscAsserted_A	695263121	1290	0	0
ErrorStIsTerminal_A	695263121	1050	0	0
EscStateOut_A	695100578	695028611	0	0
u_state_regs_A	695263121	695089685	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	247	0	0
T9	42989	77	0	0
T10	0	26	0	0
T11	0	20	0	0
T34	0	49	0	0
T35	0	75	0	0
T36	205502	0	0	0
T37	31753	0	0	0
T38	833464	0	0	0
T39	59310	0	0	0
T40	7536	0	0	0
T41	5362	0	0	0
T42	33012	0	0	0
T43	875341	0	0	0
T44	633537	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	509	0	0
T4	314876	2	0	0
T8	244125	1	0	0
T13	40749	0	0	0
T14	199782	1	0	0
T15	74346	0	0	0
T16	0	1	0	0
T19	162152	1	0	0
T20	0	2	0	0
T22	51142	0	0	0
T23	0	1	0	0
T45	214923	0	0	0
T46	98458	1	0	0
T47	14299	0	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	30	0	0
T5	130303	0	0	0
T6	119121	0	0	0
T16	275928	0	0	0
T20	126273	5	0	0
T21	115482	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T32	19677	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T44	0	1	0	0
T48	2902	0	0	0
T49	26002	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T60	0	1	0	0
T62	19551	0	0	0
T63	59363	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	262	0	0
T5	130303	0	0	0
T6	119121	0	0	0
T16	275928	0	0	0
T20	126273	6	0	0
T21	115482	0	0	0
T32	19677	0	0	0
T33	0	2	0	0
T48	2902	0	0	0
T49	26002	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	2	0	0
T62	19551	0	0	0
T63	59363	0	0	0
T64	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695102115	326983737	0	0
T1	320549	320450	0	0
T2	35024	31245	0	0
T3	78661	78588	0	0
T7	570136	570129	0	0
T8	244125	2123	0	0
T12	26932	26874	0	0
T13	40749	618	0	0
T14	199782	5627	0	0
T15	74346	74282	0	0
T22	51142	51062	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	618	0	0
T4	314876	2	0	0
T8	244125	1	0	0
T13	40749	0	0	0
T14	199782	1	0	0
T15	74346	0	0	0
T16	0	1	0	0
T19	162152	1	0	0
T20	0	7	0	0
T22	51142	0	0	0
T23	0	1	0	0
T45	214923	0	0	0
T46	98458	1	0	0
T47	14299	0	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	605	0	0
T4	314876	2	0	0
T8	244125	1	0	0
T13	40749	0	0	0
T14	199782	1	0	0
T15	74346	0	0	0
T16	0	1	0	0
T19	162152	1	0	0
T20	0	7	0	0
T22	51142	0	0	0
T23	0	1	0	0
T45	214923	0	0	0
T46	98458	1	0	0
T47	14299	0	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	599	0	0
T4	314876	2	0	0
T8	244125	1	0	0
T13	40749	0	0	0
T14	199782	1	0	0
T15	74346	0	0	0
T16	0	1	0	0
T19	162152	1	0	0
T20	0	7	0	0
T22	51142	0	0	0
T23	0	1	0	0
T45	214923	0	0	0
T46	98458	1	0	0
T47	14299	0	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	586	0	0
T4	314876	2	0	0
T8	244125	1	0	0
T13	40749	0	0	0
T14	199782	1	0	0
T15	74346	0	0	0
T16	0	1	0	0
T19	162152	1	0	0
T20	0	7	0	0
T22	51142	0	0	0
T23	0	1	0	0
T45	214923	0	0	0
T46	98458	1	0	0
T47	14299	0	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1959	0	0
T4	314876	3	0	0
T13	40749	8	0	0
T14	199782	0	0	0
T19	162152	1	0	0
T20	126273	7	0	0
T22	51142	0	0	0
T25	0	4	0	0
T45	214923	0	0	0
T46	98458	0	0	0
T47	14299	1	0	0
T48	2902	0	0	0
T52	0	6	0	0
T70	0	3	0	0
T74	0	3	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	192486	0	0
T4	314876	424	0	0
T13	40749	643	0	0
T14	199782	0	0	0
T19	162152	48	0	0
T20	126273	90	0	0
T22	51142	0	0	0
T25	0	214	0	0
T45	214923	0	0	0
T46	98458	0	0	0
T47	14299	68	0	0
T48	2902	0	0	0
T52	0	461	0	0
T70	0	146	0	0
T74	0	194	0	0
T75	0	115	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1838	0	0
T4	314876	3	0	0
T13	40749	8	0	0
T14	199782	0	0	0
T19	162152	1	0	0
T20	126273	2	0	0
T22	51142	0	0	0
T25	0	3	0	0
T45	214923	0	0	0
T46	98458	0	0	0
T47	14299	1	0	0
T48	2902	0	0	0
T52	0	6	0	0
T70	0	3	0	0
T74	0	3	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	88	0	0
T18	101276	0	0	0
T25	149547	1	0	0
T29	0	2	0	0
T33	64710	0	0	0
T58	0	1	0	0
T73	27093	0	0	0
T75	12333	0	0	0
T76	4680	0	0	0
T77	0	1	0	0
T80	0	1	0	0
T81	0	6	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	53956	0	0	0
T89	20270	0	0	0
T90	130457	0	0	0
T91	3365	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1290	0	0
T9	42989	316	0	0
T10	0	142	0	0
T11	0	150	0	0
T34	0	333	0	0
T35	0	349	0	0
T36	205502	0	0	0
T37	31753	0	0	0
T38	833464	0	0	0
T39	59310	0	0	0
T40	7536	0	0	0
T41	5362	0	0	0
T42	33012	0	0	0
T43	875341	0	0	0
T44	633537	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1050	0	0
T9	42989	256	0	0
T10	0	112	0	0
T11	0	120	0	0
T34	0	273	0	0
T35	0	289	0	0
T36	205502	0	0	0
T37	31753	0	0	0
T38	833464	0	0	0
T39	59310	0	0	0
T40	7536	0	0	0
T41	5362	0	0	0
T42	33012	0	0	0
T43	875341	0	0	0
T44	633537	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695100578	695028611	0	0
T1	320549	320451	0	0
T2	35024	34965	0	0
T3	78661	78589	0	0
T7	570136	570129	0	0
T8	244125	244120	0	0
T12	26932	26875	0	0
T13	40749	40690	0	0
T14	199782	199775	0	0
T15	74346	74283	0	0
T22	51142	51063	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	695089685	0	0
T1	320549	320451	0	0
T2	35024	34965	0	0
T3	78661	78589	0	0
T7	570136	570129	0	0
T8	244125	244120	0	0
T12	26932	26875	0	0
T13	40749	40690	0	0
T14	199782	199775	0	0
T15	74346	74283	0	0
T22	51142	51063	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T8,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T8,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T8,T13
1	0	1	Covered	T1,T15,T45
1	1	0	Covered	T2,T13,T19
1	1	1	Covered	T19,T46,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T19,T46,T4
0	1	Covered	T19,T24,T79
1	0	Covered	T23,T24,T75

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T19,T46,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T24,T75

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T46,T4
1	0	Not Covered
1	1	Covered	T19,T24,T79

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T14,T22
1	Covered	T1,T8,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T8,T15
1	Covered	T14,T50,T51

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T8,T14
1	Covered	T15,T4,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T8,T15
1	Covered	T22,T46,T24

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T15,T14,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T14,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T8,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T15,T22,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T8,T15
Phase1St	198	Covered	T1,T8,T15
Phase2St	215	Covered	T1,T8,T15
Phase3St	233	Covered	T1,T8,T15
TerminalSt	249	Covered	T1,T8,T15
TimeoutSt	159	Covered	T19,T46,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T8,T15
IdleSt->TimeoutSt	159	Covered	T19,T46,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T25,T26,T27
Phase0St->Phase1St	198	Covered	T1,T8,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T28,T105,T98
Phase1St->Phase2St	215	Covered	T1,T8,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T106,T107,T108
Phase2St->Phase3St	233	Covered	T1,T8,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T79,T102,T109
Phase3St->TerminalSt	249	Covered	T1,T8,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T46,T4,T24
TimeoutSt->Phase0St	172	Covered	T19,T23,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T46,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T23,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T19,T46,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T46,T4,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T26,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T8,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T15,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T105,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T8,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T15,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T106,T107,T108
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T8,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T8,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T79,T102,T109
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T8,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T8,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T5,T51
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T8,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	695263121	268	0	0
CheckAccumTrig0_A	695263121	497	0	0
CheckAccumTrig1_A	695263121	24	0	0
CheckClr_A	695263121	216	0	0
CheckEn_A	695102115	303389235	0	0
CheckPhase0_A	695263121	584	0	0
CheckPhase1_A	695263121	577	0	0
CheckPhase2_A	695263121	567	0	0
CheckPhase3_A	695263121	558	0	0
CheckTimeout0_A	695263121	1460	0	0
CheckTimeoutSt1_A	695263121	157252	0	0
CheckTimeoutSt2_A	695263121	1367	0	0
CheckTimeoutStTrig_A	695263121	68	0	0
ErrorStAllEscAsserted_A	695263121	1285	0	0
ErrorStIsTerminal_A	695263121	1045	0	0
EscStateOut_A	695100578	695028611	0	0
u_state_regs_A	695263121	695089685	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	268	0	0
T9	42989	90	0	0
T10	0	33	0	0
T11	0	25	0	0
T34	0	66	0	0
T35	0	54	0	0
T36	205502	0	0	0
T37	31753	0	0	0
T38	833464	0	0	0
T39	59310	0	0	0
T40	7536	0	0	0
T41	5362	0	0	0
T42	33012	0	0	0
T43	875341	0	0	0
T44	633537	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	497	0	0
T1	320549	1	0	0
T2	35024	0	0	0
T3	78661	0	0	0
T4	0	1	0	0
T5	0	2	0	0
T7	570136	0	0	0
T8	244125	1	0	0
T12	26932	0	0	0
T13	40749	0	0	0
T14	199782	1	0	0
T15	74346	3	0	0
T16	0	1	0	0
T22	51142	1	0	0
T46	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	24	0	0
T23	11008	1	0	0
T24	9026	1	0	0
T29	0	1	0	0
T38	0	1	0	0
T44	0	1	0	0
T71	177186	0	0	0
T72	6616	0	0	0
T74	13654	0	0	0
T75	0	1	0	0
T81	0	1	0	0
T85	0	1	0	0
T96	5510	0	0	0
T102	0	1	0	0
T110	0	1	0	0
T111	369349	0	0	0
T112	313740	0	0	0
T113	169986	0	0	0
T114	105614	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	216	0	0
T4	314876	0	0	0
T5	0	1	0	0
T13	40749	0	0	0
T14	199782	0	0	0
T15	74346	2	0	0
T19	162152	0	0	0
T20	126273	0	0	0
T22	51142	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T45	214923	0	0	0
T46	98458	0	0	0
T47	14299	0	0	0
T51	0	4	0	0
T64	0	1	0	0
T113	0	1	0	0
T115	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695102115	303389235	0	0
T1	320549	2114	0	0
T2	35024	32065	0	0
T3	78661	72197	0	0
T7	570136	570129	0	0
T8	244125	10887	0	0
T12	26932	26874	0	0
T13	40749	37315	0	0
T14	199782	5643	0	0
T15	74346	2161	0	0
T22	51142	3126	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	584	0	0
T1	320549	1	0	0
T2	35024	0	0	0
T3	78661	0	0	0
T4	0	1	0	0
T5	0	2	0	0
T7	570136	0	0	0
T8	244125	1	0	0
T12	26932	0	0	0
T13	40749	0	0	0
T14	199782	1	0	0
T15	74346	3	0	0
T19	0	1	0	0
T22	51142	1	0	0
T46	0	1	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	577	0	0
T1	320549	1	0	0
T2	35024	0	0	0
T3	78661	0	0	0
T4	0	1	0	0
T5	0	2	0	0
T7	570136	0	0	0
T8	244125	1	0	0
T12	26932	0	0	0
T13	40749	0	0	0
T14	199782	1	0	0
T15	74346	3	0	0
T19	0	1	0	0
T22	51142	1	0	0
T46	0	1	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	567	0	0
T1	320549	1	0	0
T2	35024	0	0	0
T3	78661	0	0	0
T4	0	1	0	0
T5	0	2	0	0
T7	570136	0	0	0
T8	244125	1	0	0
T12	26932	0	0	0
T13	40749	0	0	0
T14	199782	1	0	0
T15	74346	3	0	0
T19	0	1	0	0
T22	51142	1	0	0
T46	0	1	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	558	0	0
T1	320549	1	0	0
T2	35024	0	0	0
T3	78661	0	0	0
T4	0	1	0	0
T5	0	2	0	0
T7	570136	0	0	0
T8	244125	1	0	0
T12	26932	0	0	0
T13	40749	0	0	0
T14	199782	1	0	0
T15	74346	3	0	0
T19	0	1	0	0
T22	51142	1	0	0
T46	0	1	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1460	0	0
T4	314876	1	0	0
T5	130303	0	0	0
T16	275928	0	0	0
T19	162152	1	0	0
T20	126273	0	0	0
T21	115482	0	0	0
T23	0	1	0	0
T24	0	3	0	0
T25	0	12	0	0
T45	214923	0	0	0
T46	98458	1	0	0
T47	14299	0	0	0
T48	2902	0	0	0
T52	0	4	0	0
T69	0	1	0	0
T74	0	3	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	157252	0	0
T4	314876	139	0	0
T5	130303	0	0	0
T16	275928	0	0	0
T19	162152	20	0	0
T20	126273	0	0	0
T21	115482	0	0	0
T24	0	429	0	0
T25	0	900	0	0
T45	214923	0	0	0
T46	98458	192	0	0
T47	14299	0	0	0
T48	2902	0	0	0
T52	0	200	0	0
T69	0	32	0	0
T74	0	186	0	0
T76	0	186	0	0
T77	0	401	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1367	0	0
T4	314876	1	0	0
T5	130303	0	0	0
T16	275928	0	0	0
T20	126273	0	0	0
T21	115482	0	0	0
T24	0	1	0	0
T25	0	12	0	0
T32	19677	0	0	0
T46	98458	1	0	0
T47	14299	0	0	0
T48	2902	0	0	0
T52	0	4	0	0
T53	0	1	0	0
T62	19551	0	0	0
T69	0	1	0	0
T74	0	3	0	0
T76	0	3	0	0
T77	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	68	0	0
T4	314876	0	0	0
T5	130303	0	0	0
T16	275928	0	0	0
T19	162152	1	0	0
T20	126273	0	0	0
T21	115482	0	0	0
T24	0	1	0	0
T29	0	2	0	0
T44	0	2	0	0
T45	214923	0	0	0
T46	98458	0	0	0
T47	14299	0	0	0
T48	2902	0	0	0
T56	0	1	0	0
T58	0	2	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T116	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1285	0	0
T9	42989	328	0	0
T10	0	186	0	0
T11	0	143	0	0
T34	0	324	0	0
T35	0	304	0	0
T36	205502	0	0	0
T37	31753	0	0	0
T38	833464	0	0	0
T39	59310	0	0	0
T40	7536	0	0	0
T41	5362	0	0	0
T42	33012	0	0	0
T43	875341	0	0	0
T44	633537	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1045	0	0
T9	42989	268	0	0
T10	0	156	0	0
T11	0	113	0	0
T34	0	264	0	0
T35	0	244	0	0
T36	205502	0	0	0
T37	31753	0	0	0
T38	833464	0	0	0
T39	59310	0	0	0
T40	7536	0	0	0
T41	5362	0	0	0
T42	33012	0	0	0
T43	875341	0	0	0
T44	633537	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695100578	695028611	0	0
T1	320549	320451	0	0
T2	35024	34965	0	0
T3	78661	78589	0	0
T7	570136	570129	0	0
T8	244125	244120	0	0
T12	26932	26875	0	0
T13	40749	40690	0	0
T14	199782	199775	0	0
T15	74346	74283	0	0
T22	51142	51063	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	695089685	0	0
T1	320549	320451	0	0
T2	35024	34965	0	0
T3	78661	78589	0	0
T7	570136	570129	0	0
T8	244125	244120	0	0
T12	26932	26875	0	0
T13	40749	40690	0	0
T14	199782	199775	0	0
T15	74346	74283	0	0
T22	51142	51063	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T8,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T8,T15,T22

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T8,T13
1	0	1	Covered	T7,T14,T45
1	1	0	Covered	T2,T19,T4
1	1	1	Covered	T2,T13,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T4
0	1	Covered	T4,T52,T78
1	0	Covered	T28,T29,T117

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T13,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T29,T117

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T4
1	0	Not Covered
1	1	Covered	T4,T52,T78

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T8,T22,T19
1	Covered	T15,T4,T49

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T8,T15,T22
1	Covered	T4,T112,T72

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T8,T15,T45
1	Covered	T22,T19,T46

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T22,T19
1	Covered	T8,T45,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T19,T45,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T15,T22,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T8,T46,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T8,T15,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T8,T15,T22
Phase1St	198	Covered	T8,T15,T22
Phase2St	215	Covered	T8,T15,T22
Phase3St	233	Covered	T8,T15,T22
TerminalSt	249	Covered	T8,T15,T22
TimeoutSt	159	Covered	T2,T13,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T8,T15,T22
IdleSt->TimeoutSt	159	Covered	T2,T13,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T118,T98
Phase0St->Phase1St	198	Covered	T8,T15,T22
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T28,T117,T101
Phase1St->Phase2St	215	Covered	T8,T15,T22
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T112,T72,T53
Phase2St->Phase3St	233	Covered	T8,T15,T22
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T20,T27,T119
Phase3St->TerminalSt	249	Covered	T8,T15,T22
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T4,T47
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T13,T74
TimeoutSt->Phase0St	172	Covered	T4,T52,T78

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T15,T22
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T13,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T52,T78
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T13,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T13,T74
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T118,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T8,T15,T22
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T8,T15,T22
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T117,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T8,T15,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T8,T15,T22
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T112,T72,T53
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T8,T15,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T8,T15,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T27,T119
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T8,T15,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T8,T15,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T47,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T15,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	695263121	198	0	0
CheckAccumTrig0_A	695263121	478	0	0
CheckAccumTrig1_A	695263121	29	0	0
CheckClr_A	695263121	220	0	0
CheckEn_A	695102115	351089115	0	0
CheckPhase0_A	695263121	562	0	0
CheckPhase1_A	695263121	553	0	0
CheckPhase2_A	695263121	539	0	0
CheckPhase3_A	695263121	529	0	0
CheckTimeout0_A	695263121	1645	0	0
CheckTimeoutSt1_A	695263121	159318	0	0
CheckTimeoutSt2_A	695263121	1549	0	0
CheckTimeoutStTrig_A	695263121	62	0	0
ErrorStAllEscAsserted_A	695263121	1189	0	0
ErrorStIsTerminal_A	695263121	949	0	0
EscStateOut_A	695100578	695028611	0	0
u_state_regs_A	695263121	695089685	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	198	0	0
T9	42989	58	0	0
T10	0	20	0	0
T11	0	27	0	0
T34	0	58	0	0
T35	0	35	0	0
T36	205502	0	0	0
T37	31753	0	0	0
T38	833464	0	0	0
T39	59310	0	0	0
T40	7536	0	0	0
T41	5362	0	0	0
T42	33012	0	0	0
T43	875341	0	0	0
T44	633537	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	478	0	0
T4	314876	2	0	0
T8	244125	1	0	0
T13	40749	0	0	0
T14	199782	0	0	0
T15	74346	1	0	0
T19	162152	1	0	0
T20	0	1	0	0
T22	51142	1	0	0
T45	214923	1	0	0
T46	98458	1	0	0
T47	14299	2	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	29	0	0
T9	42989	0	0	0
T28	965573	1	0	0
T29	0	2	0	0
T109	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	2	0	0
T123	0	2	0	0
T124	0	1	0	0
T125	147429	0	0	0
T126	332020	0	0	0
T127	59854	0	0	0
T128	8040	0	0	0
T129	10523	0	0	0
T130	525447	0	0	0
T131	297124	0	0	0
T132	343947	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	220	0	0
T4	314876	0	0	0
T13	40749	0	0	0
T14	199782	0	0	0
T15	74346	1	0	0
T19	162152	0	0	0
T20	126273	1	0	0
T22	51142	0	0	0
T24	0	1	0	0
T33	0	1	0	0
T45	214923	0	0	0
T46	98458	0	0	0
T47	14299	1	0	0
T52	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T112	0	1	0	0
T113	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695102115	351089115	0	0
T1	320549	45559	0	0
T2	35024	32277	0	0
T3	78661	72193	0	0
T7	570136	10288	0	0
T8	244125	16244	0	0
T12	26932	26874	0	0
T13	40749	626	0	0
T14	199782	199083	0	0
T15	74346	67532	0	0
T22	51142	3143	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	562	0	0
T4	314876	3	0	0
T8	244125	1	0	0
T13	40749	0	0	0
T14	199782	0	0	0
T15	74346	1	0	0
T19	162152	1	0	0
T20	0	1	0	0
T22	51142	1	0	0
T45	214923	1	0	0
T46	98458	1	0	0
T47	14299	2	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	553	0	0
T4	314876	3	0	0
T8	244125	1	0	0
T13	40749	0	0	0
T14	199782	0	0	0
T15	74346	1	0	0
T19	162152	1	0	0
T20	0	1	0	0
T22	51142	1	0	0
T45	214923	1	0	0
T46	98458	1	0	0
T47	14299	2	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	539	0	0
T4	314876	3	0	0
T8	244125	1	0	0
T13	40749	0	0	0
T14	199782	0	0	0
T15	74346	1	0	0
T19	162152	1	0	0
T20	0	1	0	0
T22	51142	1	0	0
T45	214923	1	0	0
T46	98458	1	0	0
T47	14299	2	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	529	0	0
T4	314876	3	0	0
T8	244125	1	0	0
T13	40749	0	0	0
T14	199782	0	0	0
T15	74346	1	0	0
T19	162152	1	0	0
T22	51142	1	0	0
T23	0	1	0	0
T45	214923	1	0	0
T46	98458	1	0	0
T47	14299	2	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1645	0	0
T2	35024	1	0	0
T3	78661	0	0	0
T4	0	1	0	0
T7	570136	0	0	0
T8	244125	0	0	0
T12	26932	0	0	0
T13	40749	6	0	0
T14	199782	0	0	0
T15	74346	0	0	0
T19	162152	0	0	0
T22	51142	0	0	0
T25	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	3	0	0
T74	0	2	0	0
T77	0	3	0	0
T78	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	159318	0	0
T2	35024	253	0	0
T3	78661	0	0	0
T4	0	124	0	0
T7	570136	0	0	0
T8	244125	0	0	0
T12	26932	0	0	0
T13	40749	775	0	0
T14	199782	0	0	0
T15	74346	0	0	0
T19	162152	0	0	0
T22	51142	0	0	0
T25	0	22	0	0
T52	0	43	0	0
T53	0	84	0	0
T54	0	389	0	0
T74	0	131	0	0
T77	0	402	0	0
T78	0	540	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1549	0	0
T2	35024	1	0	0
T3	78661	0	0	0
T7	570136	0	0	0
T8	244125	0	0	0
T12	26932	0	0	0
T13	40749	6	0	0
T14	199782	0	0	0
T15	74346	0	0	0
T19	162152	0	0	0
T22	51142	0	0	0
T25	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	3	0	0
T74	0	2	0	0
T77	0	3	0	0
T78	0	5	0	0
T133	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	62	0	0
T4	314876	1	0	0
T5	130303	0	0	0
T16	275928	0	0	0
T20	126273	0	0	0
T21	115482	0	0	0
T29	0	2	0	0
T32	19677	0	0	0
T47	14299	0	0	0
T48	2902	0	0	0
T52	0	1	0	0
T62	19551	0	0	0
T63	59363	0	0	0
T78	0	1	0	0
T100	0	2	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	1189	0	0
T9	42989	291	0	0
T10	0	145	0	0
T11	0	160	0	0
T34	0	295	0	0
T35	0	298	0	0
T36	205502	0	0	0
T37	31753	0	0	0
T38	833464	0	0	0
T39	59310	0	0	0
T40	7536	0	0	0
T41	5362	0	0	0
T42	33012	0	0	0
T43	875341	0	0	0
T44	633537	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	949	0	0
T9	42989	231	0	0
T10	0	115	0	0
T11	0	130	0	0
T34	0	235	0	0
T35	0	238	0	0
T36	205502	0	0	0
T37	31753	0	0	0
T38	833464	0	0	0
T39	59310	0	0	0
T40	7536	0	0	0
T41	5362	0	0	0
T42	33012	0	0	0
T43	875341	0	0	0
T44	633537	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695100578	695028611	0	0
T1	320549	320451	0	0
T2	35024	34965	0	0
T3	78661	78589	0	0
T7	570136	570129	0	0
T8	244125	244120	0	0
T12	26932	26875	0	0
T13	40749	40690	0	0
T14	199782	199775	0	0
T15	74346	74283	0	0
T22	51142	51063	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695263121	695089685	0	0
T1	320549	320451	0	0
T2	35024	34965	0	0
T3	78661	78589	0	0
T7	570136	570129	0	0
T8	244125	244120	0	0
T12	26932	26875	0	0
T13	40749	40690	0	0
T14	199782	199775	0	0
T15	74346	74283	0	0
T22	51142	51063	0	0