Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64831186	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31577519

1

T1

410982

T2

3293

T3

120031

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14521721	1			T1	151793		T2	1942		T3	46907
values[0x0]	39781216	1			T1	478626		T2	3916		T3	167176
values[0x1]	42105768	1			T1	567830		T2	3878		T3	167270

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55186095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41222610

1

T1

561580

T2

4074

T3

151996

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	749954	1			T1	4612		T3	1449		T4	587
valid_sources[0x01]	319662	1			T1	4719		T3	1452		T4	595
valid_sources[0x02]	310751	1			T1	4729		T3	1467		T4	619
valid_sources[0x03]	327959	1			T1	4635		T3	1438		T4	669
valid_sources[0x04]	311817	1			T1	4654		T3	1486		T4	646
valid_sources[0x05]	309093	1			T1	4572		T3	1543		T4	611
valid_sources[0x06]	321438	1			T1	4687		T3	1511		T4	568
valid_sources[0x07]	316222	1			T1	4743		T3	1490		T4	581
valid_sources[0x08]	593217	1			T1	4584		T3	1518		T4	612
valid_sources[0x09]	317257	1			T1	4830		T3	1410		T4	680
valid_sources[0x0a]	764809	1			T1	4743		T3	1478		T4	577
valid_sources[0x0b]	691010	1			T1	4718		T3	1507		T4	588
valid_sources[0x0c]	570190	1			T1	4503		T3	1478		T4	587
valid_sources[0x0d]	312922	1			T1	4575		T3	1440		T4	594
valid_sources[0x0e]	335411	1			T1	4641		T3	1496		T4	561
valid_sources[0x0f]	311025	1			T1	4662		T3	1523		T4	617
valid_sources[0x10]	320525	1			T1	4604		T3	1412		T4	618
valid_sources[0x11]	321196	1			T1	4520		T3	1486		T4	598
valid_sources[0x12]	309048	1			T1	4666		T3	1489		T4	615
valid_sources[0x13]	312529	1			T1	4625		T3	1544		T4	616
valid_sources[0x14]	710497	1			T1	4672		T3	1509		T4	611
valid_sources[0x15]	324657	1			T1	4813		T3	1559		T4	580
valid_sources[0x16]	323480	1			T1	4622		T3	1520		T4	577
valid_sources[0x17]	321483	1			T1	4398		T3	1488		T4	568
valid_sources[0x18]	754257	1			T1	4544		T3	1478		T4	648
valid_sources[0x19]	338726	1			T1	4459		T3	1494		T4	614
valid_sources[0x1a]	310827	1			T1	4663		T3	1443		T4	615
valid_sources[0x1b]	318084	1			T1	4698		T3	1462		T4	572
valid_sources[0x1c]	304093	1			T1	4753		T3	1434		T4	638
valid_sources[0x1d]	318745	1			T1	4563		T3	1452		T4	602
valid_sources[0x1e]	318991	1			T1	4830		T3	1493		T4	616
valid_sources[0x1f]	309278	1			T1	4694		T3	1480		T4	619
valid_sources[0x20]	322997	1			T1	4786		T3	1429		T4	612
valid_sources[0x21]	315428	1			T1	4918		T3	1551		T4	626
valid_sources[0x22]	311789	1			T1	4618		T3	1530		T4	619
valid_sources[0x23]	312584	1			T1	4534		T3	1528		T4	566
valid_sources[0x24]	327151	1			T1	4832		T3	1471		T4	589
valid_sources[0x25]	307703	1			T1	4680		T3	1522		T4	588
valid_sources[0x26]	307237	1			T1	4691		T3	1506		T4	669
valid_sources[0x27]	314978	1			T1	4676		T3	1511		T4	613
valid_sources[0x28]	338460	1			T1	4801		T3	1465		T4	624
valid_sources[0x29]	317401	1			T1	4724		T3	1523		T4	652
valid_sources[0x2a]	345649	1			T1	4711		T3	1494		T4	576
valid_sources[0x2b]	742805	1			T1	4675		T3	1468		T4	613
valid_sources[0x2c]	323458	1			T1	4633		T3	1461		T4	581
valid_sources[0x2d]	312322	1			T1	4883		T3	1440		T4	611
valid_sources[0x2e]	312099	1			T1	4684		T3	1443		T4	600
valid_sources[0x2f]	303726	1			T1	4587		T3	1451		T4	589
valid_sources[0x30]	318542	1			T1	4612		T3	1459		T4	608
valid_sources[0x31]	674038	1			T1	4631		T3	1471		T4	561
valid_sources[0x32]	317490	1			T1	4518		T3	1479		T4	585
valid_sources[0x33]	320491	1			T1	4561		T3	1477		T4	620
valid_sources[0x34]	313856	1			T1	4671		T3	1501		T4	605
valid_sources[0x35]	304291	1			T1	4550		T3	1445		T4	587
valid_sources[0x36]	426514	1			T1	4888		T3	1514		T4	574
valid_sources[0x37]	323527	1			T1	4568		T2	9736		T3	1513
valid_sources[0x38]	314097	1			T1	4660		T3	1461		T4	596
valid_sources[0x39]	316935	1			T1	4604		T3	1487		T4	591
valid_sources[0x3a]	343683	1			T1	4717		T3	1511		T4	604
valid_sources[0x3b]	315356	1			T1	4771		T3	1543		T4	619
valid_sources[0x3c]	314130	1			T1	4716		T3	1501		T4	624
valid_sources[0x3d]	318335	1			T1	4493		T3	1577		T4	576
valid_sources[0x3e]	335261	1			T1	4617		T3	1504		T4	587
valid_sources[0x3f]	308855	1			T1	4714		T3	1510		T4	568
valid_sources[0x40]	314597	1			T1	4809		T3	1464		T4	622
valid_sources[0x41]	319164	1			T1	4718		T3	1573		T4	578
valid_sources[0x42]	312185	1			T1	4968		T3	1473		T4	574
valid_sources[0x43]	764538	1			T1	4679		T3	1452		T4	590
valid_sources[0x44]	310894	1			T1	4878		T3	1610		T4	596
valid_sources[0x45]	318476	1			T1	4703		T3	1516		T4	591
valid_sources[0x46]	314905	1			T1	4615		T3	1452		T4	624
valid_sources[0x47]	1142366	1			T1	4625		T3	1474		T4	598
valid_sources[0x48]	335082	1			T1	4536		T3	1558		T4	601
valid_sources[0x49]	311482	1			T1	4599		T3	1511		T4	592
valid_sources[0x4a]	308784	1			T1	4806		T3	1471		T4	623
valid_sources[0x4b]	315421	1			T1	4469		T3	1497		T4	632
valid_sources[0x4c]	312817	1			T1	4507		T3	1559		T4	617
valid_sources[0x4d]	317962	1			T1	4593		T3	1469		T4	567
valid_sources[0x4e]	310135	1			T1	4752		T3	1475		T4	622
valid_sources[0x4f]	308485	1			T1	4893		T3	1482		T4	619
valid_sources[0x50]	313923	1			T1	4840		T3	1474		T4	598
valid_sources[0x51]	310642	1			T1	4638		T3	1524		T4	579
valid_sources[0x52]	381118	1			T1	4804		T3	1445		T4	615
valid_sources[0x53]	325073	1			T1	4690		T3	1451		T4	608
valid_sources[0x54]	554820	1			T1	4703		T3	1516		T4	603
valid_sources[0x55]	323415	1			T1	4601		T3	1466		T4	574
valid_sources[0x56]	317672	1			T1	4696		T3	1479		T4	553
valid_sources[0x57]	649675	1			T1	4651		T3	1483		T4	599
valid_sources[0x58]	350308	1			T1	4714		T3	1459		T4	617
valid_sources[0x59]	371716	1			T1	4583		T3	1525		T4	594
valid_sources[0x5a]	318245	1			T1	4649		T3	1444		T4	583
valid_sources[0x5b]	351811	1			T1	4505		T3	1496		T4	573
valid_sources[0x5c]	746796	1			T1	4767		T3	1482		T4	591
valid_sources[0x5d]	305148	1			T1	4476		T3	1516		T4	570
valid_sources[0x5e]	320124	1			T1	4820		T3	1496		T4	635
valid_sources[0x5f]	559153	1			T1	4591		T3	1515		T4	613
valid_sources[0x60]	316039	1			T1	4873		T3	1441		T4	569
valid_sources[0x61]	309630	1			T1	4840		T3	1445		T4	621
valid_sources[0x62]	310900	1			T1	4812		T3	1432		T4	590
valid_sources[0x63]	301784	1			T1	4683		T3	1445		T4	590
valid_sources[0x64]	312255	1			T1	4665		T3	1519		T4	590
valid_sources[0x65]	305136	1			T1	4834		T3	1473		T4	589
valid_sources[0x66]	545601	1			T1	4707		T3	1496		T4	593
valid_sources[0x67]	326398	1			T1	4733		T3	1519		T4	594
valid_sources[0x68]	758742	1			T1	4599		T3	1448		T4	642
valid_sources[0x69]	317142	1			T1	4754		T3	1493		T4	598
valid_sources[0x6a]	329159	1			T1	4614		T3	1463		T4	573
valid_sources[0x6b]	1137180	1			T1	4685		T3	1501		T4	589
valid_sources[0x6c]	321211	1			T1	4734		T3	1549		T4	579
valid_sources[0x6d]	320714	1			T1	4866		T3	1484		T4	629
valid_sources[0x6e]	321580	1			T1	4770		T3	1463		T4	572
valid_sources[0x6f]	313708	1			T1	4878		T3	1527		T4	629
valid_sources[0x70]	326954	1			T1	4621		T3	1530		T4	566
valid_sources[0x71]	311999	1			T1	4591		T3	1472		T4	553
valid_sources[0x72]	316564	1			T1	4710		T3	1433		T4	626
valid_sources[0x73]	724545	1			T1	4648		T3	1444		T4	662
valid_sources[0x74]	592044	1			T1	4623		T3	1457		T4	607
valid_sources[0x75]	309386	1			T1	4731		T3	1517		T4	569
valid_sources[0x76]	319797	1			T1	4725		T3	1479		T4	630
valid_sources[0x77]	800042	1			T1	4713		T3	1509		T4	576
valid_sources[0x78]	319674	1			T1	4444		T3	1504		T4	565
valid_sources[0x79]	319246	1			T1	4651		T3	1489		T4	593
valid_sources[0x7a]	312169	1			T1	4687		T3	1433		T4	557
valid_sources[0x7b]	309684	1			T1	4760		T3	1489		T4	603
valid_sources[0x7c]	318231	1			T1	4557		T3	1491		T4	640
valid_sources[0x7d]	306902	1			T1	4511		T3	1478		T4	625
valid_sources[0x7e]	309723	1			T1	4484		T3	1448		T4	621
valid_sources[0x7f]	620665	1			T1	4829		T3	1540		T4	584
valid_sources[0x80]	308992	1			T1	4642		T3	1535		T4	616

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7265922

1

T1

86144

T2

940

T3

23364

values[0x0]

all_enables

biggest_size

15306178

1

T1

198646

T2

1498

T3

62073

values[0x1]

all_enables

biggest_size

9005419

1

T1

126192

T2

855

T3

34594