Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.98	100.00		96.95			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.98	100.00		96.95			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.98	100.00		96.95			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.98	100.00		96.95			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T44,T210,T211
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15424	0	0
DisabledNoTrigBkwd_A	2147483647	740914	0	0
DisabledNoTrigFwd_A	2147483647	1668169468	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15424	0	0
T31	140476	0	0	0
T44	1315	564	0	0
T53	17296	0	0	0
T80	154662	0	0	0
T93	243068	0	0	0
T110	584748	0	0	0
T210	0	807	0	0
T211	3182	712	0	0
T212	0	414	0	0
T213	0	201	0	0
T214	0	422	0	0
T215	0	950	0	0
T216	3336	783	0	0
T217	0	1133	0	0
T218	0	724	0	0
T219	0	1232	0	0
T220	0	829	0	0
T221	0	1322	0	0
T222	0	653	0	0
T223	0	1011	0	0
T224	0	687	0	0
T225	0	1065	0	0
T226	0	826	0	0
T227	0	643	0	0
T228	0	446	0	0
T229	111682	0	0	0
T230	28616	0	0	0
T231	75426	0	0	0
T232	3630	0	0	0
T233	29827	0	0	0
T234	332131	0	0	0
T235	57065	0	0	0
T236	12245	0	0	0
T237	401763	0	0	0
T238	19708	0	0	0
T239	400419	0	0	0
T240	24941	0	0	0
T241	16381	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	740914	0	0
T1	1842632	8622	0	0
T2	170296	79	0	0
T3	1413180	395	0	0
T4	2184944	1947	0	0
T5	3219268	473	0	0
T6	498560	13740	0	0
T7	2764292	15	0	0
T11	13496	3	0	0
T12	259624	4	0	0
T13	0	1770	0	0
T15	0	8	0	0
T18	0	3	0	0
T20	60660	18	0	0
T22	0	29	0	0
T44	0	21	0	0
T45	0	5	0	0
T46	0	765	0	0
T47	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1668169468	0	0
T1	1842632	1275490	0	0
T2	170296	81734	0	0
T3	1413180	722077	0	0
T4	2184944	1139511	0	0
T5	3219268	1860914	0	0
T6	498560	258055	0	0
T7	2764292	2084675	0	0
T11	13496	10408	0	0
T12	259624	175100	0	0
T20	60660	22285	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T11,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T216,T218,T225
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	724106490	2572	0	0
DisabledNoTrigBkwd_A	724106490	227376	0	0
DisabledNoTrigFwd_A	724106490	374250369	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	2572	0	0
T93	243068	0	0	0
T110	584748	0	0	0
T216	3336	783	0	0
T218	0	724	0	0
T225	0	1065	0	0
T235	57065	0	0	0
T236	12245	0	0	0
T237	401763	0	0	0
T238	19708	0	0	0
T239	400419	0	0	0
T240	24941	0	0	0
T241	16381	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	227376	0	0
T1	460658	3887	0	0
T2	42574	49	0	0
T3	353295	0	0	0
T4	546236	1124	0	0
T5	804817	52	0	0
T6	124640	2450	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	4	0	0
T20	15165	0	0	0
T22	0	7	0	0
T45	0	5	0	0
T46	0	735	0	0
T47	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	374250369	0	0
T1	460658	248464	0	0
T2	42574	582	0	0
T3	353295	11843	0	0
T4	546236	62674	0	0
T5	804817	690199	0	0
T6	124640	583	0	0
T7	691073	690979	0	0
T11	3374	3274	0	0
T12	64906	43401	0	0
T20	15165	15075	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T211,T214,T220
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	724106490	4764	0	0
DisabledNoTrigBkwd_A	724106490	194664	0	0
DisabledNoTrigFwd_A	724106490	442747808	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	4764	0	0
T31	140476	0	0	0
T53	17296	0	0	0
T80	154662	0	0	0
T211	3182	712	0	0
T214	0	422	0	0
T220	0	829	0	0
T221	0	1322	0	0
T222	0	653	0	0
T226	0	826	0	0
T229	111682	0	0	0
T230	28616	0	0	0
T231	75426	0	0	0
T232	3630	0	0	0
T233	29827	0	0	0
T234	332131	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	194664	0	0
T1	460658	397	0	0
T2	42574	4	0	0
T3	353295	1	0	0
T4	546236	174	0	0
T5	804817	214	0	0
T6	124640	56	0	0
T7	691073	0	0	0
T11	3374	1	0	0
T12	64906	0	0	0
T15	0	8	0	0
T20	15165	8	0	0
T22	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	442747808	0	0
T1	460658	396884	0	0
T2	42574	38071	0	0
T3	353295	352679	0	0
T4	546236	506953	0	0
T5	804817	243202	0	0
T6	124640	124181	0	0
T7	691073	667905	0	0
T11	3374	2108	0	0
T12	64906	64815	0	0
T20	15165	6026	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T44,T210,T215
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	724106490	5010	0	0
DisabledNoTrigBkwd_A	724106490	194529	0	0
DisabledNoTrigFwd_A	724106490	392979590	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	5010	0	0
T13	192112	0	0	0
T14	15793	0	0	0
T15	358792	0	0	0
T18	844166	0	0	0
T44	1315	564	0	0
T45	25630	0	0	0
T46	96031	0	0	0
T47	74258	0	0	0
T48	33642	0	0	0
T63	119797	0	0	0
T210	0	807	0	0
T215	0	950	0	0
T219	0	1232	0	0
T223	0	1011	0	0
T228	0	446	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	194529	0	0
T1	460658	758	0	0
T2	42574	26	0	0
T3	353295	0	0	0
T4	546236	258	0	0
T5	804817	0	0	0
T6	124640	11232	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T13	0	1769	0	0
T18	0	3	0	0
T20	15165	10	0	0
T22	0	2	0	0
T44	0	21	0	0
T46	0	24	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	392979590	0	0
T1	460658	380395	0	0
T2	42574	590	0	0
T3	353295	351743	0	0
T4	546236	300207	0	0
T5	804817	597162	0	0
T6	124640	8810	0	0
T7	691073	690979	0	0
T11	3374	3274	0	0
T12	64906	61225	0	0
T20	15165	590	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T3,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T213,T217
1	1	Covered	T1,T3,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	724106490	3078	0	0
DisabledNoTrigBkwd_A	724106490	124345	0	0
DisabledNoTrigFwd_A	724106490	458191701	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	3078	0	0
T54	10443	0	0	0
T55	57830	0	0	0
T118	22920	0	0	0
T212	4227	414	0	0
T213	0	201	0	0
T217	0	1133	0	0
T224	0	687	0	0
T227	0	643	0	0
T242	116030	0	0	0
T243	11130	0	0	0
T244	915934	0	0	0
T245	130114	0	0	0
T246	73828	0	0	0
T247	344925	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	124345	0	0
T1	460658	3580	0	0
T2	42574	0	0	0
T3	353295	394	0	0
T4	546236	391	0	0
T5	804817	207	0	0
T6	124640	2	0	0
T7	691073	15	0	0
T11	3374	2	0	0
T12	64906	0	0	0
T13	0	1	0	0
T20	15165	0	0	0
T22	0	11	0	0
T46	0	6	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	458191701	0	0
T1	460658	249747	0	0
T2	42574	42491	0	0
T3	353295	5812	0	0
T4	546236	269677	0	0
T5	804817	330351	0	0
T6	124640	124481	0	0
T7	691073	34812	0	0
T11	3374	1752	0	0
T12	64906	5659	0	0
T20	15165	594	0	0