Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.98	100.00		96.95			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.98	100.00		96.95			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.98	100.00		96.95			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.78	100.00	95.56	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.98	100.00		96.95			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T23
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T4
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T2,T11
1	1	1	Covered	T1,T4,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T6

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T6

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T12

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T4,T6

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T4,T6
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T24,T25,T26
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T5,T27,T28
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T5,T29,T30
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T28,T31,T32
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T6,T5
TimeoutSt->Phase0St	172	Covered	T1,T4,T6

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T27,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T29,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T31,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	895	0	0
CheckAccumTrig0_A	2147483647	2268	0	0
CheckAccumTrig1_A	2147483647	113	0	0
CheckClr_A	2147483647	1079	0	0
CheckEn_A	2147483647	1302049794	0	0
CheckPhase0_A	2147483647	2602	0	0
CheckPhase1_A	2147483647	2549	0	0
CheckPhase2_A	2147483647	2505	0	0
CheckPhase3_A	2147483647	2457	0	0
CheckTimeout0_A	2147483647	5703	0	0
CheckTimeoutSt1_A	2147483647	571927	0	0
CheckTimeoutSt2_A	2147483647	5325	0	0
CheckTimeoutStTrig_A	2147483647	264	0	0
ErrorStAllEscAsserted_A	2147483647	5070	0	0
ErrorStIsTerminal_A	2147483647	4110	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	895	0	0
T8	165620	197	0	0
T9	0	211	0	0
T10	0	120	0	0
T33	0	215	0	0
T34	0	152	0	0
T35	38268	0	0	0
T36	1490256	0	0	0
T37	1062244	0	0	0
T38	111332	0	0	0
T39	91288	0	0	0
T40	49232	0	0	0
T41	396108	0	0	0
T42	2362568	0	0	0
T43	24484	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2268	0	0
T1	1842632	24	0	0
T2	170296	5	0	0
T3	1413180	2	0	0
T4	2184944	13	0	0
T5	3219268	7	0	0
T6	498560	3	0	0
T7	2764292	1	0	0
T11	13496	2	0	0
T12	259624	2	0	0
T13	0	3	0	0
T15	0	1	0	0
T18	0	1	0	0
T20	60660	2	0	0
T22	0	5	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	113	0	0
T1	460658	2	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	1	0	0
T5	1609634	2	0	0
T6	249280	1	0	0
T7	1382146	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T13	192112	0	0	0
T15	358792	0	0	0
T20	30330	0	0	0
T21	12863	0	0	0
T22	14260	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	1	0	0
T31	0	3	0	0
T37	0	2	0	0
T44	1315	0	0	0
T45	25630	1	0	0
T47	0	1	0	0
T49	608322	1	0	0
T50	0	7	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	325567	0	0	0
T60	255979	0	0	0
T61	26667	0	0	0
T62	586358	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1079	0	0
T1	1842632	13	0	0
T2	170296	3	0	0
T3	1413180	0	0	0
T4	2184944	4	0	0
T5	3219268	6	0	0
T6	498560	0	0	0
T7	2764292	0	0	0
T11	13496	0	0	0
T12	259624	1	0	0
T13	0	1	0	0
T18	0	2	0	0
T20	60660	0	0	0
T22	0	2	0	0
T27	0	6	0	0
T28	0	8	0	0
T45	0	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T63	0	5	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	0	3	0	0
T70	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1302049794	0	0
T1	1842632	1059158	0	0
T2	170296	81732	0	0
T3	1413180	379739	0	0
T4	2184944	1085524	0	0
T5	3219268	1854617	0	0
T6	498560	14030	0	0
T7	2764292	2084672	0	0
T11	13496	9248	0	0
T12	259624	133708	0	0
T20	60660	16844	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2602	0	0
T1	1842632	30	0	0
T2	170296	5	0	0
T3	1413180	2	0	0
T4	2184944	15	0	0
T5	3219268	12	0	0
T6	498560	4	0	0
T7	2764292	1	0	0
T11	13496	2	0	0
T12	259624	2	0	0
T13	0	2	0	0
T15	0	1	0	0
T18	0	1	0	0
T20	60660	2	0	0
T22	0	5	0	0
T44	0	1	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2549	0	0
T1	1842632	30	0	0
T2	170296	5	0	0
T3	1413180	2	0	0
T4	2184944	15	0	0
T5	3219268	11	0	0
T6	498560	4	0	0
T7	2764292	1	0	0
T11	13496	2	0	0
T12	259624	2	0	0
T13	0	2	0	0
T15	0	1	0	0
T18	0	1	0	0
T20	60660	2	0	0
T22	0	5	0	0
T44	0	1	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2505	0	0
T1	1842632	30	0	0
T2	170296	5	0	0
T3	1413180	2	0	0
T4	2184944	15	0	0
T5	3219268	10	0	0
T6	498560	4	0	0
T7	2764292	1	0	0
T11	13496	2	0	0
T12	259624	2	0	0
T13	0	2	0	0
T15	0	1	0	0
T18	0	1	0	0
T20	60660	2	0	0
T22	0	5	0	0
T44	0	1	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2457	0	0
T1	1842632	30	0	0
T2	170296	5	0	0
T3	1413180	2	0	0
T4	2184944	15	0	0
T5	3219268	10	0	0
T6	498560	4	0	0
T7	2764292	1	0	0
T11	13496	2	0	0
T12	259624	2	0	0
T13	0	2	0	0
T15	0	1	0	0
T18	0	1	0	0
T20	60660	2	0	0
T22	0	5	0	0
T44	0	1	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5703	0	0
T1	1381974	8	0	0
T2	127722	0	0	0
T3	1059885	0	0	0
T4	1638708	2	0	0
T5	3219268	15	0	0
T6	498560	2	0	0
T7	2764292	0	0	0
T11	10122	0	0	0
T12	194718	0	0	0
T13	192112	0	0	0
T15	358792	0	0	0
T18	0	1	0	0
T20	60660	0	0	0
T21	12863	0	0	0
T22	14260	2	0	0
T28	0	1	0	0
T44	1315	0	0	0
T45	25630	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	9	0	0
T59	0	2	0	0
T62	0	3	0	0
T63	0	7	0	0
T68	0	4	0	0
T71	0	4	0	0
T72	0	9	0	0
T73	0	14	0	0
T74	0	2	0	0
T75	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	571927	0	0
T1	1381974	830	0	0
T2	127722	0	0	0
T3	1059885	0	0	0
T4	1638708	49	0	0
T5	3219268	1726	0	0
T6	498560	89	0	0
T7	2764292	0	0	0
T11	10122	0	0	0
T12	194718	0	0	0
T13	192112	0	0	0
T15	358792	0	0	0
T18	0	42	0	0
T20	60660	0	0	0
T21	12863	0	0	0
T22	14260	182	0	0
T28	0	1	0	0
T44	1315	0	0	0
T45	25630	0	0	0
T46	0	903	0	0
T47	0	235	0	0
T48	0	105	0	0
T49	0	3712	0	0
T59	0	197	0	0
T62	0	542	0	0
T63	0	1621	0	0
T68	0	256	0	0
T71	0	397	0	0
T72	0	514	0	0
T73	0	1119	0	0
T74	0	188	0	0
T75	0	161	0	0
T76	0	683	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5325	0	0
T1	921316	2	0	0
T2	85148	0	0	0
T3	706590	0	0	0
T4	1092472	0	0	0
T5	3219268	10	0	0
T6	373920	1	0	0
T7	2073219	0	0	0
T11	6748	0	0	0
T12	129812	0	0	0
T13	384224	0	0	0
T14	15793	0	0	0
T15	717584	0	0	0
T18	844166	1	0	0
T20	45495	0	0	0
T21	25726	0	0	0
T22	28520	2	0	0
T24	0	3	0	0
T44	2630	0	0	0
T45	51260	0	0	0
T46	96031	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	3	0	0
T59	0	2	0	0
T62	0	3	0	0
T63	0	4	0	0
T68	0	4	0	0
T69	0	19	0	0
T70	0	18	0	0
T71	0	2	0	0
T72	0	9	0	0
T73	0	20	0	0
T74	0	5	0	0
T75	0	1	0	0
T77	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	264	0	0
T1	460658	1	0	0
T4	1092472	1	0	0
T5	1609634	2	0	0
T6	249280	0	0	0
T7	1382146	0	0	0
T12	129812	0	0	0
T15	358792	0	0	0
T16	975502	0	0	0
T17	138270	0	0	0
T19	219035	0	0	0
T20	30330	0	0	0
T21	12863	0	0	0
T22	14260	0	0	0
T24	0	3	0	0
T25	0	1	0	0
T26	0	1	0	0
T44	1315	0	0	0
T46	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T62	0	1	0	0
T63	119797	3	0	0
T70	0	3	0	0
T71	29676	2	0	0
T73	0	1	0	0
T75	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	80071	0	0	0
T83	3092	0	0	0
T84	76805	0	0	0
T85	23165	0	0	0
T86	937890	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5070	0	0
T8	165620	1322	0	0
T9	0	1183	0	0
T10	0	593	0	0
T33	0	1281	0	0
T34	0	691	0	0
T35	38268	0	0	0
T36	1490256	0	0	0
T37	1062244	0	0	0
T38	111332	0	0	0
T39	91288	0	0	0
T40	49232	0	0	0
T41	396108	0	0	0
T42	2362568	0	0	0
T43	24484	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4110	0	0
T8	165620	1082	0	0
T9	0	943	0	0
T10	0	473	0	0
T33	0	1041	0	0
T34	0	571	0	0
T35	38268	0	0	0
T36	1490256	0	0	0
T37	1062244	0	0	0
T38	111332	0	0	0
T39	91288	0	0	0
T40	49232	0	0	0
T41	396108	0	0	0
T42	2362568	0	0	0
T43	24484	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1842632	1842588	0	0
T2	170296	169964	0	0
T3	1413180	1413148	0	0
T4	2184944	2182636	0	0
T5	3219268	3217452	0	0
T6	498560	498536	0	0
T7	2764292	2763916	0	0
T11	13496	13096	0	0
T12	259624	259260	0	0
T20	60660	60300	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1842632	1842588	0	0
T2	170296	169964	0	0
T3	1413180	1413148	0	0
T4	2184944	2182636	0	0
T5	3219268	3217452	0	0
T6	498560	498536	0	0
T7	2764292	2763916	0	0
T11	13496	13096	0	0
T12	259624	259260	0	0
T20	60660	60300	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T12
1	0	1	Covered	T1,T4,T46
1	1	0	Covered	T1,T11,T5
1	1	1	Covered	T1,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T4,T63,T71
1	0	Covered	T1,T4,T5

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T4,T63,T71

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T5,T63

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T1,T2,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T12,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T1,T4,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T80,T87,T88
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T5,T87,T89
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T57,T88
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T32,T87,T90
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T12
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T22,T63
TimeoutSt->Phase0St	172	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T22,T63
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T80,T87,T88
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T87,T89
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T57,T88
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T87,T90
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	724106490	266	0	0
CheckAccumTrig0_A	724106490	832	0	0
CheckAccumTrig1_A	724106490	58	0	0
CheckClr_A	724106490	425	0	0
CheckEn_A	723908984	313477562	0	0
CheckPhase0_A	724106490	932	0	0
CheckPhase1_A	724106490	917	0	0
CheckPhase2_A	724106490	901	0	0
CheckPhase3_A	724106490	880	0	0
CheckTimeout0_A	724106490	1090	0	0
CheckTimeoutSt1_A	724106490	124351	0	0
CheckTimeoutSt2_A	724106490	974	0	0
CheckTimeoutStTrig_A	724106490	58	0	0
ErrorStAllEscAsserted_A	724106490	1216	0	0
ErrorStIsTerminal_A	724106490	976	0	0
EscStateOut_A	723907329	723837363	0	0
u_state_regs_A	724106490	723935699	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	266	0	0
T8	41405	53	0	0
T9	0	61	0	0
T10	0	32	0	0
T33	0	68	0	0
T34	0	52	0	0
T35	9567	0	0	0
T36	372564	0	0	0
T37	265561	0	0	0
T38	27833	0	0	0
T39	22822	0	0	0
T40	12308	0	0	0
T41	99027	0	0	0
T42	590642	0	0	0
T43	6121	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	832	0	0
T1	460658	7	0	0
T2	42574	1	0	0
T3	353295	0	0	0
T4	546236	4	0	0
T5	804817	3	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	2	0	0
T20	15165	0	0	0
T22	0	2	0	0
T45	0	3	0	0
T46	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	58	0	0
T1	460658	2	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	1	0	0
T5	804817	2	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T20	15165	0	0	0
T26	0	1	0	0
T31	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	6	0	0
T51	0	1	0	0
T54	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	425	0	0
T1	460658	4	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	2	0	0
T5	804817	4	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	1	0	0
T20	15165	0	0	0
T22	0	2	0	0
T45	0	4	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723908984	313477562	0	0
T1	460658	224504	0	0
T2	42574	582	0	0
T3	353295	11843	0	0
T4	546236	50399	0	0
T5	804817	690195	0	0
T6	124640	583	0	0
T7	691073	690978	0	0
T11	3374	3273	0	0
T12	64906	2011	0	0
T20	15165	15074	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	932	0	0
T1	460658	9	0	0
T2	42574	1	0	0
T3	353295	0	0	0
T4	546236	6	0	0
T5	804817	5	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	2	0	0
T20	15165	0	0	0
T22	0	2	0	0
T45	0	4	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	917	0	0
T1	460658	9	0	0
T2	42574	1	0	0
T3	353295	0	0	0
T4	546236	6	0	0
T5	804817	4	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	2	0	0
T20	15165	0	0	0
T22	0	2	0	0
T45	0	4	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	901	0	0
T1	460658	9	0	0
T2	42574	1	0	0
T3	353295	0	0	0
T4	546236	6	0	0
T5	804817	3	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	2	0	0
T20	15165	0	0	0
T22	0	2	0	0
T45	0	4	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	880	0	0
T1	460658	9	0	0
T2	42574	1	0	0
T3	353295	0	0	0
T4	546236	6	0	0
T5	804817	3	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	2	0	0
T20	15165	0	0	0
T22	0	2	0	0
T45	0	4	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1090	0	0
T1	460658	2	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	2	0	0
T5	804817	4	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T20	15165	0	0	0
T22	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T63	0	3	0	0
T71	0	1	0	0
T72	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	124351	0	0
T1	460658	21	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	49	0	0
T5	804817	286	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T20	15165	0	0	0
T22	0	47	0	0
T47	0	36	0	0
T49	0	1704	0	0
T62	0	77	0	0
T63	0	1346	0	0
T71	0	122	0	0
T72	0	296	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	974	0	0
T5	804817	2	0	0
T13	192112	0	0	0
T14	15793	0	0	0
T15	358792	0	0	0
T18	844166	0	0	0
T21	12863	0	0	0
T22	14260	1	0	0
T24	0	3	0	0
T44	1315	0	0	0
T45	25630	0	0	0
T46	96031	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T69	0	12	0	0
T70	0	3	0	0
T72	0	5	0	0
T73	0	7	0	0
T74	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	58	0	0
T4	546236	1	0	0
T5	804817	0	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T12	64906	0	0	0
T15	358792	0	0	0
T20	15165	0	0	0
T21	12863	0	0	0
T22	14260	0	0	0
T24	0	1	0	0
T44	1315	0	0	0
T49	0	2	0	0
T55	0	1	0	0
T63	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1216	0	0
T8	41405	324	0	0
T9	0	264	0	0
T10	0	142	0	0
T33	0	315	0	0
T34	0	171	0	0
T35	9567	0	0	0
T36	372564	0	0	0
T37	265561	0	0	0
T38	27833	0	0	0
T39	22822	0	0	0
T40	12308	0	0	0
T41	99027	0	0	0
T42	590642	0	0	0
T43	6121	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	976	0	0
T8	41405	264	0	0
T9	0	204	0	0
T10	0	112	0	0
T33	0	255	0	0
T34	0	141	0	0
T35	9567	0	0	0
T36	372564	0	0	0
T37	265561	0	0	0
T38	27833	0	0	0
T39	22822	0	0	0
T40	12308	0	0	0
T41	99027	0	0	0
T42	590642	0	0	0
T43	6121	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723907329	723837363	0	0
T1	460658	460647	0	0
T2	42574	42491	0	0
T3	353295	353287	0	0
T4	546236	545659	0	0
T5	804817	804363	0	0
T6	124640	124634	0	0
T7	691073	690979	0	0
T11	3374	3274	0	0
T12	64906	64815	0	0
T20	15165	15075	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	723935699	0	0
T1	460658	460647	0	0
T2	42574	42491	0	0
T3	353295	353287	0	0
T4	546236	545659	0	0
T5	804817	804363	0	0
T6	124640	124634	0	0
T7	691073	690979	0	0
T11	3374	3274	0	0
T12	64906	64815	0	0
T20	15165	15075	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T4
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T6,T5,T47

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T47
0	1	Covered	T63,T71,T49
1	0	Covered	T6,T28,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T5,T47
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T28,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T5,T47
1	0	Not Covered
1	1	Covered	T63,T71,T49

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T11

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T46

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T63,T71

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T11

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T6,T5,T47

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T6,T5,T47
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T25,T53,T56
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T28,T31,T91
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T30,T92,T93
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T28,T31,T57
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T5,T47
TimeoutSt->Phase0St	172	Covered	T6,T63,T71

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T5,T47
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T63,T71
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T5,T47
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T5,T47
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T53,T56
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T31,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T30,T92,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T31,T57
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	724106490	225	0	0
CheckAccumTrig0_A	724106490	479	0	0
CheckAccumTrig1_A	724106490	23	0	0
CheckClr_A	724106490	210	0	0
CheckEn_A	723908984	337039182	0	0
CheckPhase0_A	724106490	557	0	0
CheckPhase1_A	724106490	547	0	0
CheckPhase2_A	724106490	541	0	0
CheckPhase3_A	724106490	530	0	0
CheckTimeout0_A	724106490	1268	0	0
CheckTimeoutSt1_A	724106490	150742	0	0
CheckTimeoutSt2_A	724106490	1181	0	0
CheckTimeoutStTrig_A	724106490	64	0	0
ErrorStAllEscAsserted_A	724106490	1297	0	0
ErrorStIsTerminal_A	724106490	1057	0	0
EscStateOut_A	723907329	723837363	0	0
u_state_regs_A	724106490	723935699	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	225	0	0
T8	41405	53	0	0
T9	0	57	0	0
T10	0	32	0	0
T33	0	59	0	0
T34	0	24	0	0
T35	9567	0	0	0
T36	372564	0	0	0
T37	265561	0	0	0
T38	27833	0	0	0
T39	22822	0	0	0
T40	12308	0	0	0
T41	99027	0	0	0
T42	590642	0	0	0
T43	6121	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	479	0	0
T1	460658	5	0	0
T2	42574	1	0	0
T3	353295	1	0	0
T4	546236	2	0	0
T5	804817	2	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	1	0	0
T12	64906	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T20	15165	1	0	0
T22	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	23	0	0
T5	804817	0	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T13	192112	0	0	0
T15	358792	0	0	0
T20	15165	0	0	0
T21	12863	0	0	0
T22	14260	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T37	0	2	0	0
T44	1315	0	0	0
T45	25630	0	0	0
T51	0	1	0	0
T52	0	2	0	0
T56	0	1	0	0
T58	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	210	0	0
T1	460658	3	0	0
T2	42574	1	0	0
T3	353295	0	0	0
T4	546236	0	0	0
T5	804817	0	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T18	0	1	0	0
T20	15165	0	0	0
T28	0	7	0	0
T47	0	1	0	0
T63	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T69	0	3	0	0
T70	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723908984	337039182	0	0
T1	460658	396883	0	0
T2	42574	38070	0	0
T3	353295	10341	0	0
T4	546236	506948	0	0
T5	804817	240886	0	0
T6	124640	587	0	0
T7	691073	667904	0	0
T11	3374	2108	0	0
T12	64906	64814	0	0
T20	15165	586	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	557	0	0
T1	460658	5	0	0
T2	42574	1	0	0
T3	353295	1	0	0
T4	546236	2	0	0
T5	804817	2	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	1	0	0
T12	64906	0	0	0
T15	0	1	0	0
T20	15165	1	0	0
T22	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	547	0	0
T1	460658	5	0	0
T2	42574	1	0	0
T3	353295	1	0	0
T4	546236	2	0	0
T5	804817	2	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	1	0	0
T12	64906	0	0	0
T15	0	1	0	0
T20	15165	1	0	0
T22	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	541	0	0
T1	460658	5	0	0
T2	42574	1	0	0
T3	353295	1	0	0
T4	546236	2	0	0
T5	804817	2	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	1	0	0
T12	64906	0	0	0
T15	0	1	0	0
T20	15165	1	0	0
T22	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	530	0	0
T1	460658	5	0	0
T2	42574	1	0	0
T3	353295	1	0	0
T4	546236	2	0	0
T5	804817	2	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	1	0	0
T12	64906	0	0	0
T15	0	1	0	0
T20	15165	1	0	0
T22	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1268	0	0
T5	804817	3	0	0
T6	124640	2	0	0
T7	691073	0	0	0
T13	192112	0	0	0
T15	358792	0	0	0
T20	15165	0	0	0
T21	12863	0	0	0
T22	14260	0	0	0
T28	0	1	0	0
T44	1315	0	0	0
T45	25630	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T71	0	3	0	0
T72	0	4	0	0
T73	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	150742	0	0
T5	804817	428	0	0
T6	124640	89	0	0
T7	691073	0	0	0
T13	192112	0	0	0
T15	358792	0	0	0
T20	15165	0	0	0
T21	12863	0	0	0
T22	14260	0	0	0
T28	0	1	0	0
T44	1315	0	0	0
T45	25630	0	0	0
T47	0	199	0	0
T49	0	858	0	0
T62	0	152	0	0
T63	0	199	0	0
T71	0	275	0	0
T72	0	218	0	0
T73	0	81	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1181	0	0
T5	804817	3	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T13	192112	0	0	0
T15	358792	0	0	0
T20	15165	0	0	0
T21	12863	0	0	0
T22	14260	0	0	0
T44	1315	0	0	0
T45	25630	0	0	0
T47	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T71	0	2	0	0
T72	0	4	0	0
T73	0	1	0	0
T74	0	1	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	64	0	0
T16	975502	0	0	0
T17	138270	0	0	0
T19	219035	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T63	119797	1	0	0
T71	29676	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T80	0	1	0	0
T82	80071	0	0	0
T83	3092	0	0	0
T84	76805	0	0	0
T85	23165	0	0	0
T86	937890	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1297	0	0
T8	41405	333	0	0
T9	0	305	0	0
T10	0	149	0	0
T33	0	322	0	0
T34	0	188	0	0
T35	9567	0	0	0
T36	372564	0	0	0
T37	265561	0	0	0
T38	27833	0	0	0
T39	22822	0	0	0
T40	12308	0	0	0
T41	99027	0	0	0
T42	590642	0	0	0
T43	6121	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1057	0	0
T8	41405	273	0	0
T9	0	245	0	0
T10	0	119	0	0
T33	0	262	0	0
T34	0	158	0	0
T35	9567	0	0	0
T36	372564	0	0	0
T37	265561	0	0	0
T38	27833	0	0	0
T39	22822	0	0	0
T40	12308	0	0	0
T41	99027	0	0	0
T42	590642	0	0	0
T43	6121	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723907329	723837363	0	0
T1	460658	460647	0	0
T2	42574	42491	0	0
T3	353295	353287	0	0
T4	546236	545659	0	0
T5	804817	804363	0	0
T6	124640	124634	0	0
T7	691073	690979	0	0
T11	3374	3274	0	0
T12	64906	64815	0	0
T20	15165	15075	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	723935699	0	0
T1	460658	460647	0	0
T2	42574	42491	0	0
T3	353295	353287	0	0
T4	546236	545659	0	0
T5	804817	804363	0	0
T6	124640	124634	0	0
T7	691073	690979	0	0
T11	3374	3274	0	0
T12	64906	64815	0	0
T20	15165	15075	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T12
1	0	1	Covered	T1,T4,T44
1	1	0	Covered	T1,T4,T6
1	1	1	Covered	T1,T5,T46

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T46
0	1	Covered	T1,T5,T46
1	0	Covered	T49,T50,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T5,T46
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T49,T50,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T46
1	0	Not Covered
1	1	Covered	T1,T5,T46

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T20
1	Covered	T2,T4,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T22,T47

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T44

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T1,T5,T46

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T1,T5,T46
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T24,T26,T94
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T27,T95,T96
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T57,T97,T98
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T57,T36,T99
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T5,T48
TimeoutSt->Phase0St	172	Covered	T1,T5,T46

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T46
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T46
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T46
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T48
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T26,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T95,T96
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T57,T97,T98
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T57,T36,T99
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	724106490	188	0	0
CheckAccumTrig0_A	724106490	498	0	0
CheckAccumTrig1_A	724106490	22	0	0
CheckClr_A	724106490	234	0	0
CheckEn_A	723908984	320587098	0	0
CheckPhase0_A	724106490	580	0	0
CheckPhase1_A	724106490	562	0	0
CheckPhase2_A	724106490	555	0	0
CheckPhase3_A	724106490	544	0	0
CheckTimeout0_A	724106490	1623	0	0
CheckTimeoutSt1_A	724106490	142018	0	0
CheckTimeoutSt2_A	724106490	1530	0	0
CheckTimeoutStTrig_A	724106490	70	0	0
ErrorStAllEscAsserted_A	724106490	1207	0	0
ErrorStIsTerminal_A	724106490	967	0	0
EscStateOut_A	723907329	723837363	0	0
u_state_regs_A	724106490	723935699	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	188	0	0
T8	41405	51	0	0
T9	0	41	0	0
T10	0	27	0	0
T33	0	32	0	0
T34	0	37	0	0
T35	9567	0	0	0
T36	372564	0	0	0
T37	265561	0	0	0
T38	27833	0	0	0
T39	22822	0	0	0
T40	12308	0	0	0
T41	99027	0	0	0
T42	590642	0	0	0
T43	6121	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	498	0	0
T1	460658	5	0	0
T2	42574	3	0	0
T3	353295	0	0	0
T4	546236	4	0	0
T5	804817	0	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T13	0	1	0	0
T18	0	1	0	0
T20	15165	1	0	0
T22	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	22	0	0
T49	608322	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	2	0	0
T59	325567	0	0	0
T60	255979	0	0	0
T61	26667	0	0	0
T62	586358	0	0	0
T73	49616	0	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	119798	0	0	0
T105	309055	0	0	0
T106	21958	0	0	0
T107	371521	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	234	0	0
T1	460658	2	0	0
T2	42574	2	0	0
T3	353295	0	0	0
T4	546236	1	0	0
T5	804817	1	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T18	0	1	0	0
T20	15165	0	0	0
T27	0	3	0	0
T48	0	1	0	0
T63	0	2	0	0
T67	0	1	0	0
T68	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723908984	320587098	0	0
T1	460658	289548	0	0
T2	42574	590	0	0
T3	353295	351743	0	0
T4	546236	259977	0	0
T5	804817	597158	0	0
T6	124640	8810	0	0
T7	691073	690978	0	0
T11	3374	3273	0	0
T12	64906	61224	0	0
T20	15165	590	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	580	0	0
T1	460658	6	0	0
T2	42574	3	0	0
T3	353295	0	0	0
T4	546236	4	0	0
T5	804817	2	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T13	0	1	0	0
T18	0	1	0	0
T20	15165	1	0	0
T22	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	562	0	0
T1	460658	6	0	0
T2	42574	3	0	0
T3	353295	0	0	0
T4	546236	4	0	0
T5	804817	2	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T13	0	1	0	0
T18	0	1	0	0
T20	15165	1	0	0
T22	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	555	0	0
T1	460658	6	0	0
T2	42574	3	0	0
T3	353295	0	0	0
T4	546236	4	0	0
T5	804817	2	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T13	0	1	0	0
T18	0	1	0	0
T20	15165	1	0	0
T22	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	544	0	0
T1	460658	6	0	0
T2	42574	3	0	0
T3	353295	0	0	0
T4	546236	4	0	0
T5	804817	2	0	0
T6	124640	1	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T13	0	1	0	0
T18	0	1	0	0
T20	15165	1	0	0
T22	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1623	0	0
T1	460658	2	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	0	0	0
T5	804817	7	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T20	15165	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	3	0	0
T62	0	2	0	0
T63	0	1	0	0
T68	0	4	0	0
T73	0	12	0	0
T74	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	142018	0	0
T1	460658	703	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	0	0	0
T5	804817	1006	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T20	15165	0	0	0
T46	0	903	0	0
T48	0	105	0	0
T49	0	337	0	0
T62	0	313	0	0
T63	0	47	0	0
T68	0	256	0	0
T73	0	1038	0	0
T74	0	78	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1530	0	0
T1	460658	1	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	0	0	0
T5	804817	5	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T20	15165	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T62	0	1	0	0
T63	0	1	0	0
T68	0	4	0	0
T73	0	12	0	0
T74	0	1	0	0
T77	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	70	0	0
T1	460658	1	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	0	0	0
T5	804817	2	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T20	15165	0	0	0
T24	0	2	0	0
T46	0	1	0	0
T62	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1207	0	0
T8	41405	318	0	0
T9	0	295	0	0
T10	0	126	0	0
T33	0	317	0	0
T34	0	151	0	0
T35	9567	0	0	0
T36	372564	0	0	0
T37	265561	0	0	0
T38	27833	0	0	0
T39	22822	0	0	0
T40	12308	0	0	0
T41	99027	0	0	0
T42	590642	0	0	0
T43	6121	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	967	0	0
T8	41405	258	0	0
T9	0	235	0	0
T10	0	96	0	0
T33	0	257	0	0
T34	0	121	0	0
T35	9567	0	0	0
T36	372564	0	0	0
T37	265561	0	0	0
T38	27833	0	0	0
T39	22822	0	0	0
T40	12308	0	0	0
T41	99027	0	0	0
T42	590642	0	0	0
T43	6121	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723907329	723837363	0	0
T1	460658	460647	0	0
T2	42574	42491	0	0
T3	353295	353287	0	0
T4	546236	545659	0	0
T5	804817	804363	0	0
T6	124640	124634	0	0
T7	691073	690979	0	0
T11	3374	3274	0	0
T12	64906	64815	0	0
T20	15165	15075	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	723935699	0	0
T1	460658	460647	0	0
T2	42574	42491	0	0
T3	353295	353287	0	0
T4	546236	545659	0	0
T5	804817	804363	0	0
T6	124640	124634	0	0
T7	691073	690979	0	0
T11	3374	3274	0	0
T12	64906	64815	0	0
T20	15165	15075	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T23
1	1	1	Covered	T1,T3,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T12
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T6,T5
1	1	1	Covered	T1,T5,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T22
0	1	Covered	T1,T49,T75
1	0	Covered	T1,T5,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T5,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T22
1	0	Not Covered
1	1	Covered	T1,T49,T75

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T7,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T4
1	Covered	T1,T3,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T11,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T6,T82

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T5,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T11,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T11
Phase1St	198	Covered	T1,T3,T11
Phase2St	215	Covered	T1,T3,T11
Phase3St	233	Covered	T1,T3,T11
TerminalSt	249	Covered	T1,T3,T11
TimeoutSt	159	Covered	T1,T5,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T3,T11
IdleSt->TimeoutSt	159	Covered	T1,T5,T22
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T49,T87
Phase0St->Phase1St	198	Covered	T1,T3,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T86,T53,T108
Phase1St->Phase2St	215	Covered	T1,T3,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T25,T109
Phase2St->Phase3St	233	Covered	T1,T3,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T37,T110,T111
Phase3St->TerminalSt	249	Covered	T1,T3,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T22,T18
TimeoutSt->Phase0St	172	Covered	T1,T5,T49

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T49
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T49,T87
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T86,T53,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T25,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T37,T110,T111
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	724106490	216	0	0
CheckAccumTrig0_A	724106490	459	0	0
CheckAccumTrig1_A	724106490	10	0	0
CheckClr_A	724106490	210	0	0
CheckEn_A	723908984	330945952	0	0
CheckPhase0_A	724106490	533	0	0
CheckPhase1_A	724106490	523	0	0
CheckPhase2_A	724106490	508	0	0
CheckPhase3_A	724106490	503	0	0
CheckTimeout0_A	724106490	1722	0	0
CheckTimeoutSt1_A	724106490	154816	0	0
CheckTimeoutSt2_A	724106490	1640	0	0
CheckTimeoutStTrig_A	724106490	72	0	0
ErrorStAllEscAsserted_A	724106490	1350	0	0
ErrorStIsTerminal_A	724106490	1110	0	0
EscStateOut_A	723907329	723837363	0	0
u_state_regs_A	724106490	723935699	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	216	0	0
T8	41405	40	0	0
T9	0	52	0	0
T10	0	29	0	0
T33	0	56	0	0
T34	0	39	0	0
T35	9567	0	0	0
T36	372564	0	0	0
T37	265561	0	0	0
T38	27833	0	0	0
T39	22822	0	0	0
T40	12308	0	0	0
T41	99027	0	0	0
T42	590642	0	0	0
T43	6121	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	459	0	0
T1	460658	7	0	0
T2	42574	0	0	0
T3	353295	1	0	0
T4	546236	3	0	0
T5	804817	2	0	0
T6	124640	1	0	0
T7	691073	1	0	0
T11	3374	1	0	0
T12	64906	0	0	0
T13	0	1	0	0
T20	15165	0	0	0
T22	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	10	0	0
T1	460658	2	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	0	0	0
T5	804817	1	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T20	15165	0	0	0
T49	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	210	0	0
T1	460658	4	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	1	0	0
T5	804817	1	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T13	0	1	0	0
T19	0	3	0	0
T20	15165	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T49	0	1	0	0
T63	0	1	0	0
T86	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723908984	330945952	0	0
T1	460658	148223	0	0
T2	42574	42490	0	0
T3	353295	5812	0	0
T4	546236	268200	0	0
T5	804817	326378	0	0
T6	124640	4050	0	0
T7	691073	34812	0	0
T11	3374	594	0	0
T12	64906	5659	0	0
T20	15165	594	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	533	0	0
T1	460658	10	0	0
T2	42574	0	0	0
T3	353295	1	0	0
T4	546236	3	0	0
T5	804817	3	0	0
T6	124640	1	0	0
T7	691073	1	0	0
T11	3374	1	0	0
T12	64906	0	0	0
T13	0	1	0	0
T20	15165	0	0	0
T22	0	1	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	523	0	0
T1	460658	10	0	0
T2	42574	0	0	0
T3	353295	1	0	0
T4	546236	3	0	0
T5	804817	3	0	0
T6	124640	1	0	0
T7	691073	1	0	0
T11	3374	1	0	0
T12	64906	0	0	0
T13	0	1	0	0
T20	15165	0	0	0
T22	0	1	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	508	0	0
T1	460658	10	0	0
T2	42574	0	0	0
T3	353295	1	0	0
T4	546236	3	0	0
T5	804817	3	0	0
T6	124640	1	0	0
T7	691073	1	0	0
T11	3374	1	0	0
T12	64906	0	0	0
T13	0	1	0	0
T20	15165	0	0	0
T22	0	1	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	503	0	0
T1	460658	10	0	0
T2	42574	0	0	0
T3	353295	1	0	0
T4	546236	3	0	0
T5	804817	3	0	0
T6	124640	1	0	0
T7	691073	1	0	0
T11	3374	1	0	0
T12	64906	0	0	0
T13	0	1	0	0
T20	15165	0	0	0
T22	0	1	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1722	0	0
T1	460658	4	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	0	0	0
T5	804817	1	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T18	0	1	0	0
T20	15165	0	0	0
T22	0	1	0	0
T49	0	3	0	0
T59	0	2	0	0
T63	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	154816	0	0
T1	460658	106	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	0	0	0
T5	804817	6	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T18	0	42	0	0
T20	15165	0	0	0
T22	0	135	0	0
T49	0	813	0	0
T59	0	197	0	0
T63	0	29	0	0
T74	0	110	0	0
T75	0	161	0	0
T76	0	683	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1640	0	0
T1	460658	1	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	0	0	0
T5	804817	0	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T18	0	1	0	0
T20	15165	0	0	0
T22	0	1	0	0
T49	0	1	0	0
T59	0	2	0	0
T63	0	1	0	0
T69	0	7	0	0
T70	0	15	0	0
T74	0	1	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	72	0	0
T1	460658	1	0	0
T2	42574	0	0	0
T3	353295	0	0	0
T4	546236	0	0	0
T5	804817	0	0	0
T6	124640	0	0	0
T7	691073	0	0	0
T11	3374	0	0	0
T12	64906	0	0	0
T20	15165	0	0	0
T24	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T118	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1350	0	0
T8	41405	347	0	0
T9	0	319	0	0
T10	0	176	0	0
T33	0	327	0	0
T34	0	181	0	0
T35	9567	0	0	0
T36	372564	0	0	0
T37	265561	0	0	0
T38	27833	0	0	0
T39	22822	0	0	0
T40	12308	0	0	0
T41	99027	0	0	0
T42	590642	0	0	0
T43	6121	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	1110	0	0
T8	41405	287	0	0
T9	0	259	0	0
T10	0	146	0	0
T33	0	267	0	0
T34	0	151	0	0
T35	9567	0	0	0
T36	372564	0	0	0
T37	265561	0	0	0
T38	27833	0	0	0
T39	22822	0	0	0
T40	12308	0	0	0
T41	99027	0	0	0
T42	590642	0	0	0
T43	6121	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723907329	723837363	0	0
T1	460658	460647	0	0
T2	42574	42491	0	0
T3	353295	353287	0	0
T4	546236	545659	0	0
T5	804817	804363	0	0
T6	124640	124634	0	0
T7	691073	690979	0	0
T11	3374	3274	0	0
T12	64906	64815	0	0
T20	15165	15075	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724106490	723935699	0	0
T1	460658	460647	0	0
T2	42574	42491	0	0
T3	353295	353287	0	0
T4	546236	545659	0	0
T5	804817	804363	0	0
T6	124640	124634	0	0
T7	691073	690979	0	0
T11	3374	3274	0	0
T12	64906	64815	0	0
T20	15165	15075	0	0