Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66318038	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32215232

1

T1

3922

T2

6772

T3

4036

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14843101	1			T1	1451		T2	2445		T3	1574
values[0x0]	40725446	1			T1	5637		T2	9689		T3	5587
values[0x1]	42964723	1			T1	5617		T2	9371		T3	5579

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56529328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42003942

1

T1

4982

T2

8592

T3

5081

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	322300	1			T1	33		T3	67		T7	1632
valid_sources[0x01]	327498	1			T1	48		T3	55		T7	1547
valid_sources[0x02]	349675	1			T1	64		T3	44		T7	1508
valid_sources[0x03]	324689	1			T1	40		T3	48		T7	1549
valid_sources[0x04]	317742	1			T1	59		T3	41		T7	1610
valid_sources[0x05]	361446	1			T1	47		T3	65		T7	1580
valid_sources[0x06]	324029	1			T1	70		T3	64		T7	1543
valid_sources[0x07]	317876	1			T1	51		T3	61		T7	1543
valid_sources[0x08]	317387	1			T1	50		T3	41		T7	1529
valid_sources[0x09]	321444	1			T1	37		T3	43		T7	1598
valid_sources[0x0a]	316877	1			T1	57		T3	66		T7	1577
valid_sources[0x0b]	317255	1			T1	59		T3	50		T7	1559
valid_sources[0x0c]	367158	1			T1	34		T3	58		T7	1525
valid_sources[0x0d]	539784	1			T1	45		T3	48		T7	1595
valid_sources[0x0e]	778159	1			T1	52		T3	50		T7	1619
valid_sources[0x0f]	640018	1			T1	47		T3	50		T7	1585
valid_sources[0x10]	330392	1			T1	30		T3	51		T7	1621
valid_sources[0x11]	325343	1			T1	74		T3	59		T7	1561
valid_sources[0x12]	328472	1			T1	37		T3	47		T7	1571
valid_sources[0x13]	319127	1			T1	61		T3	68		T7	1523
valid_sources[0x14]	320324	1			T1	61		T3	50		T7	1603
valid_sources[0x15]	322329	1			T1	51		T3	42		T7	1582
valid_sources[0x16]	317437	1			T1	63		T3	49		T7	1589
valid_sources[0x17]	323310	1			T1	48		T3	59		T7	1523
valid_sources[0x18]	323760	1			T1	37		T3	54		T7	1704
valid_sources[0x19]	319559	1			T1	71		T3	53		T7	1605
valid_sources[0x1a]	320663	1			T1	63		T3	55		T7	1496
valid_sources[0x1b]	327863	1			T1	33		T3	59		T7	1480
valid_sources[0x1c]	325174	1			T1	55		T3	49		T7	1556
valid_sources[0x1d]	321985	1			T1	34		T3	32		T7	1625
valid_sources[0x1e]	322640	1			T1	38		T3	63		T7	1495
valid_sources[0x1f]	746175	1			T1	43		T3	45		T7	1575
valid_sources[0x20]	806432	1			T1	68		T3	49		T7	1654
valid_sources[0x21]	321563	1			T1	47		T3	52		T7	1484
valid_sources[0x22]	318986	1			T1	54		T3	40		T7	1571
valid_sources[0x23]	532329	1			T1	67		T3	40		T7	1600
valid_sources[0x24]	317015	1			T1	38		T3	40		T7	1639
valid_sources[0x25]	325470	1			T1	59		T3	75		T7	1623
valid_sources[0x26]	324031	1			T1	54		T3	31		T7	1510
valid_sources[0x27]	327818	1			T1	59		T3	48		T7	1608
valid_sources[0x28]	318532	1			T1	43		T3	39		T7	1505
valid_sources[0x29]	749930	1			T1	37		T3	54		T7	1490
valid_sources[0x2a]	765299	1			T1	36		T3	57		T7	1559
valid_sources[0x2b]	624468	1			T1	52		T3	52		T7	1473
valid_sources[0x2c]	328685	1			T1	60		T3	56		T7	1523
valid_sources[0x2d]	676162	1			T1	33		T3	41		T7	1566
valid_sources[0x2e]	326041	1			T1	46		T3	62		T7	1608
valid_sources[0x2f]	316638	1			T1	59		T3	50		T7	1593
valid_sources[0x30]	322046	1			T1	48		T3	38		T7	1598
valid_sources[0x31]	324267	1			T1	47		T3	43		T7	1584
valid_sources[0x32]	523883	1			T1	49		T3	46		T7	1541
valid_sources[0x33]	328445	1			T1	44		T3	69		T7	1575
valid_sources[0x34]	321650	1			T1	45		T3	68		T7	1557
valid_sources[0x35]	319409	1			T1	80		T3	39		T7	1629
valid_sources[0x36]	319399	1			T1	76		T3	52		T7	1598
valid_sources[0x37]	981026	1			T1	53		T3	53		T7	1552
valid_sources[0x38]	315829	1			T1	57		T3	43		T7	1630
valid_sources[0x39]	323466	1			T1	61		T3	51		T11	5628
valid_sources[0x3a]	321166	1			T1	64		T3	50		T7	1588
valid_sources[0x3b]	325059	1			T1	58		T3	48		T7	1534
valid_sources[0x3c]	358161	1			T1	44		T3	56		T7	1591
valid_sources[0x3d]	323125	1			T1	42		T3	43		T7	1573
valid_sources[0x3e]	320102	1			T1	43		T3	57		T7	1537
valid_sources[0x3f]	317459	1			T1	48		T3	39		T7	1603
valid_sources[0x40]	612664	1			T1	46		T3	64		T7	1639
valid_sources[0x41]	332809	1			T1	58		T3	51		T7	1581
valid_sources[0x42]	624152	1			T1	52		T3	48		T7	1596
valid_sources[0x43]	321001	1			T1	52		T3	50		T7	1510
valid_sources[0x44]	631801	1			T1	49		T3	57		T7	1601
valid_sources[0x45]	324465	1			T1	40		T3	56		T7	1645
valid_sources[0x46]	314675	1			T1	62		T3	42		T7	1575
valid_sources[0x47]	327236	1			T1	44		T3	56		T7	1629
valid_sources[0x48]	325313	1			T1	52		T3	33		T7	1586
valid_sources[0x49]	317899	1			T1	41		T3	46		T7	1645
valid_sources[0x4a]	320712	1			T1	63		T3	42		T7	1623
valid_sources[0x4b]	319996	1			T1	52		T3	49		T7	1516
valid_sources[0x4c]	319450	1			T1	32		T3	47		T7	1609
valid_sources[0x4d]	333870	1			T1	59		T3	47		T7	1523
valid_sources[0x4e]	320016	1			T1	53		T3	41		T7	1633
valid_sources[0x4f]	323190	1			T1	45		T3	30		T7	1545
valid_sources[0x50]	318586	1			T1	41		T3	41		T7	1596
valid_sources[0x51]	317511	1			T1	56		T3	55		T7	1631
valid_sources[0x52]	317797	1			T1	42		T3	54		T7	1572
valid_sources[0x53]	787762	1			T1	65		T3	58		T7	1570
valid_sources[0x54]	326967	1			T1	47		T3	55		T7	1619
valid_sources[0x55]	320518	1			T1	37		T3	54		T7	1584
valid_sources[0x56]	320228	1			T1	45		T3	58		T7	1456
valid_sources[0x57]	323538	1			T1	59		T3	35		T7	1613
valid_sources[0x58]	320479	1			T1	49		T3	63		T7	1580
valid_sources[0x59]	355055	1			T1	45		T3	48		T7	1580
valid_sources[0x5a]	792050	1			T1	44		T3	57		T7	1594
valid_sources[0x5b]	323440	1			T1	39		T3	42		T7	1596
valid_sources[0x5c]	316904	1			T1	46		T3	69		T7	1595
valid_sources[0x5d]	319566	1			T1	60		T3	27		T7	1571
valid_sources[0x5e]	321727	1			T1	42		T3	43		T7	1630
valid_sources[0x5f]	702793	1			T1	43		T3	46		T7	1562
valid_sources[0x60]	322364	1			T1	53		T3	35		T7	1552
valid_sources[0x61]	319328	1			T1	58		T3	37		T7	1608
valid_sources[0x62]	329000	1			T1	43		T3	51		T7	1546
valid_sources[0x63]	321323	1			T1	56		T3	55		T7	1607
valid_sources[0x64]	316187	1			T1	52		T3	45		T7	1566
valid_sources[0x65]	316648	1			T1	53		T3	64		T7	1597
valid_sources[0x66]	327271	1			T1	52		T3	53		T7	1579
valid_sources[0x67]	364410	1			T1	57		T3	52		T7	1534
valid_sources[0x68]	319655	1			T1	40		T3	53		T7	1632
valid_sources[0x69]	324469	1			T1	30		T3	48		T7	1576
valid_sources[0x6a]	326809	1			T1	44		T3	59		T7	1522
valid_sources[0x6b]	321528	1			T1	65		T3	37		T7	1617
valid_sources[0x6c]	318906	1			T1	47		T3	55		T7	1567
valid_sources[0x6d]	314846	1			T1	49		T3	55		T7	1508
valid_sources[0x6e]	328337	1			T1	26		T3	32		T7	1561
valid_sources[0x6f]	318311	1			T1	56		T3	53		T7	1647
valid_sources[0x70]	336787	1			T1	34		T3	36		T7	1535
valid_sources[0x71]	326238	1			T1	46		T3	52		T7	1601
valid_sources[0x72]	521723	1			T1	45		T3	45		T7	1581
valid_sources[0x73]	317303	1			T1	42		T3	40		T7	1584
valid_sources[0x74]	316212	1			T1	45		T3	42		T7	1652
valid_sources[0x75]	320910	1			T1	35		T3	32		T7	1519
valid_sources[0x76]	327350	1			T1	47		T3	50		T7	1686
valid_sources[0x77]	319567	1			T1	42		T3	58		T7	1541
valid_sources[0x78]	323650	1			T1	61		T3	67		T7	1595
valid_sources[0x79]	319705	1			T1	63		T3	55		T7	1605
valid_sources[0x7a]	323082	1			T1	55		T3	33		T7	1604
valid_sources[0x7b]	321319	1			T1	36		T3	53		T7	1656
valid_sources[0x7c]	326341	1			T1	51		T3	54		T7	1589
valid_sources[0x7d]	782683	1			T1	59		T3	77		T7	1591
valid_sources[0x7e]	328251	1			T1	61		T3	45		T7	1476
valid_sources[0x7f]	359276	1			T1	55		T3	48		T7	1549
valid_sources[0x80]	321975	1			T1	36		T3	56		T7	1649

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7396636

1

T1

733

T2

1203

T3

789

values[0x0]

all_enables

biggest_size

15641232

1

T1

2111

T2

3625

T3

2127

values[0x1]

all_enables

biggest_size

9177364

1

T1

1078

T2

1944

T3

1120