Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T39,T60
1	1	Covered	T1,T2,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T12

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13495	0	0
DisabledNoTrigBkwd_A	2147483647	854390	0	0
DisabledNoTrigFwd_A	2147483647	1559056984	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13495	0	0
T5	439288	0	0	0
T19	114131	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T36	5601	1928	0	0
T37	11145	0	0	0
T38	28082	0	0	0
T39	1148	404	0	0
T42	24031	0	0	0
T60	1502	701	0	0
T66	38401	0	0	0
T67	37745	0	0	0
T70	136695	0	0	0
T98	6066	657	0	0
T99	358199	0	0	0
T100	6535	0	0	0
T199	0	501	0	0
T200	0	168	0	0
T201	0	557	0	0
T202	0	375	0	0
T203	0	280	0	0
T204	0	776	0	0
T205	0	1355	0	0
T206	0	526	0	0
T207	0	813	0	0
T208	0	746	0	0
T209	0	242	0	0
T210	0	1029	0	0
T211	0	734	0	0
T212	0	881	0	0
T213	0	582	0	0
T214	0	240	0	0
T215	643134	0	0	0
T216	39207	0	0	0
T217	492917	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	854390	0	0
T2	199075	37	0	0
T3	107339	0	0	0
T4	42740	0	0	0
T5	0	9	0	0
T6	0	10529	0	0
T7	795964	1533	0	0
T8	730220	4962	0	0
T11	64744	0	0	0
T12	64852	93	0	0
T13	83656	4	0	0
T14	51390	8	0	0
T15	1379292	237	0	0
T16	695817	36	0	0
T17	672357	431	0	0
T18	0	2	0	0
T19	0	2	0	0
T20	275802	0	0	0
T21	176934	2690	0	0
T22	0	4450	0	0
T23	253136	54	0	0
T24	0	1	0	0
T26	0	1127	0	0
T28	0	2	0	0
T36	0	40	0	0
T39	0	9	0	0
T40	66272	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1559056984	0	0
T1	434856	410295	0	0
T2	796300	599865	0	0
T3	429356	1101706	0	0
T7	1591928	1213617	0	0
T8	730220	370856	0	0
T11	258976	85113	0	0
T12	129704	97647	0	0
T13	83656	79382	0	0
T14	68520	27163	0	0
T15	1379292	1039994	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98,T201,T205
1	1	Covered	T1,T2,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	707762413	3315	0	0
DisabledNoTrigBkwd_A	707762413	218260	0	0
DisabledNoTrigFwd_A	707762413	332007861	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	3315	0	0
T42	24031	0	0	0
T66	38401	0	0	0
T67	37745	0	0	0
T70	136695	0	0	0
T98	3033	657	0	0
T99	358199	0	0	0
T100	6535	0	0	0
T201	0	557	0	0
T205	0	1355	0	0
T208	0	746	0	0
T215	643134	0	0	0
T216	39207	0	0	0
T217	492917	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	218260	0	0
T2	199075	37	0	0
T3	107339	0	0	0
T7	397982	1528	0	0
T8	182555	1690	0	0
T11	64744	0	0	0
T12	32426	93	0	0
T13	20914	0	0	0
T14	17130	8	0	0
T15	344823	0	0	0
T17	0	431	0	0
T21	0	2690	0	0
T22	0	2346	0	0
T23	63284	54	0	0
T24	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	332007861	0	0
T1	108714	99858	0	0
T2	199075	6466	0	0
T3	107339	818268	0	0
T7	397982	21710	0	0
T8	182555	6023	0	0
T11	64744	64679	0	0
T12	32426	582	0	0
T13	20914	20814	0	0
T14	17130	2108	0	0
T15	344823	344750	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T2,T11,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T39,T203
1	1	Covered	T2,T11,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T13,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	707762413	4007	0	0
DisabledNoTrigBkwd_A	707762413	233122	0	0
DisabledNoTrigFwd_A	707762413	377867673	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	4007	0	0
T5	439288	0	0	0
T19	114131	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T36	5601	1928	0	0
T37	11145	0	0	0
T38	28082	0	0	0
T39	1148	404	0	0
T203	0	280	0	0
T207	0	813	0	0
T213	0	582	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	233122	0	0
T5	0	9	0	0
T6	0	10483	0	0
T7	397982	5	0	0
T8	182555	3272	0	0
T12	32426	0	0	0
T13	20914	4	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	36	0	0
T17	224119	0	0	0
T19	0	2	0	0
T20	91934	0	0	0
T22	0	2104	0	0
T23	63284	0	0	0
T36	0	40	0	0
T39	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	377867673	0	0
T1	108714	105445	0	0
T2	199075	195407	0	0
T3	107339	68774	0	0
T7	397982	396967	0	0
T8	182555	586	0	0
T11	64744	8753	0	0
T12	32426	32355	0	0
T13	20914	16940	0	0
T14	17130	11830	0	0
T15	344823	344750	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T11,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T199,T200
1	1	Covered	T1,T11,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T18,T28

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	707762413	3901	0	0
DisabledNoTrigBkwd_A	707762413	180047	0	0
DisabledNoTrigFwd_A	707762413	438638954	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	3901	0	0
T29	222245	0	0	0
T30	495208	0	0	0
T60	1502	701	0	0
T61	67381	0	0	0
T62	624577	0	0	0
T63	5936	0	0	0
T64	111371	0	0	0
T65	376830	0	0	0
T69	8022	0	0	0
T98	3033	0	0	0
T199	0	501	0	0
T200	0	168	0	0
T206	0	526	0	0
T209	0	242	0	0
T210	0	1029	0	0
T211	0	734	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	180047	0	0
T4	21370	0	0	0
T6	0	46	0	0
T8	182555	0	0	0
T13	20914	0	0	0
T15	344823	237	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T18	0	2	0	0
T20	91934	0	0	0
T21	176934	0	0	0
T23	63284	0	0	0
T26	0	1127	0	0
T28	0	2	0	0
T40	33136	0	0	0
T41	0	14	0	0
T58	0	1	0	0
T59	0	336	0	0
T60	0	9	0	0
T61	0	15	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	438638954	0	0
T1	108714	99539	0	0
T2	199075	198996	0	0
T3	107339	107332	0	0
T7	397982	396967	0	0
T8	182555	182545	0	0
T11	64744	3164	0	0
T12	32426	32355	0	0
T13	20914	20814	0	0
T14	17130	11073	0	0
T15	344823	5744	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T14
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T11,T14

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T202,T204,T212
1	1	Covered	T1,T11,T14

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T14,T16,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	707762413	2272	0	0
DisabledNoTrigBkwd_A	707762413	222961	0	0
DisabledNoTrigFwd_A	707762413	410542496	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	2272	0	0
T202	2712	375	0	0
T204	0	776	0	0
T212	0	881	0	0
T214	0	240	0	0
T218	492440	0	0	0
T219	37492	0	0	0
T220	127711	0	0	0
T221	195921	0	0	0
T222	49357	0	0	0
T223	266462	0	0	0
T224	153825	0	0	0
T225	19000	0	0	0
T226	549729	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	222961	0	0
T4	21370	0	0	0
T6	0	12	0	0
T8	182555	0	0	0
T13	20914	0	0	0
T14	17130	8	0	0
T15	344823	0	0	0
T16	231939	68	0	0
T17	224119	269	0	0
T18	0	2	0	0
T20	91934	0	0	0
T21	0	4	0	0
T22	0	3136	0	0
T23	63284	0	0	0
T26	0	189	0	0
T40	33136	0	0	0
T58	0	369	0	0
T59	0	246	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	410542496	0	0
T1	108714	105453	0	0
T2	199075	198996	0	0
T3	107339	107332	0	0
T7	397982	397973	0	0
T8	182555	181702	0	0
T11	64744	8517	0	0
T12	32426	32355	0	0
T13	20914	20814	0	0
T14	17130	2152	0	0
T15	344823	344750	0	0