Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T2,T11,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T11,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T14,T13
1	0	1	Covered	T1,T2,T7
1	1	0	Covered	T11,T14,T13
1	1	1	Covered	T11,T14,T23

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T14,T23
0	1	Covered	T11,T24,T25
1	0	Covered	T23,T24,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T14,T23
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T23,T24,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T14,T23
1	0	Covered	T27
1	1	Covered	T11,T24,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T12,T15
1	Covered	T2,T14,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T7,T15,T28

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T8,T21,T24

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T14
1	Covered	T7,T12,T8

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T2,T7,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T2,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T2,T7,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T7,T12,T14

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T7,T12
Phase1St	198	Covered	T2,T7,T12
Phase2St	215	Covered	T2,T7,T12
Phase3St	233	Covered	T2,T7,T12
TerminalSt	249	Covered	T2,T7,T12
TimeoutSt	159	Covered	T11,T14,T23

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T4,T9,T10
IdleSt->Phase0St	152	Covered	T2,T7,T12
IdleSt->TimeoutSt	159	Covered	T11,T14,T23
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T6,T29,T30
Phase0St->Phase1St	198	Covered	T2,T7,T12
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T31,T32,T33
Phase1St->Phase2St	215	Covered	T2,T7,T12
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T8,T5,T33
Phase2St->Phase3St	233	Covered	T2,T7,T12
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T8,T5,T29
Phase3St->TerminalSt	249	Covered	T2,T7,T12
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T11,T14,T8
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T11,T14,T20
TimeoutSt->Phase0St	172	Covered	T11,T23,T24

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T14,T23
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T23,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T14,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T11,T14,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T29,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T7,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T7,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T32,T33
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T7,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T7,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T5,T33
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T7,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T7,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T8,T5,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T7,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T7,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T8,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T7,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	808	0	0
CheckAccumTrig0_A	2147483647	2367	0	0
CheckAccumTrig1_A	2147483647	111	0	0
CheckClr_A	2147483647	1124	0	0
CheckEn_A	2147483647	1232309448	0	0
CheckPhase0_A	2147483647	2671	0	0
CheckPhase1_A	2147483647	2616	0	0
CheckPhase2_A	2147483647	2569	0	0
CheckPhase3_A	2147483647	2517	0	0
CheckTimeout0_A	2147483647	4178	0	0
CheckTimeoutSt1_A	2147483647	527274	0	0
CheckTimeoutSt2_A	2147483647	3808	0	0
CheckTimeoutStTrig_A	2147483647	255	0	0
ErrorStAllEscAsserted_A	2147483647	4572	0	0
ErrorStIsTerminal_A	2147483647	3732	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	808	0	0
T4	85480	115	0	0
T9	0	215	0	0
T10	0	117	0	0
T18	417160	0	0	0
T21	707736	0	0	0
T22	1495900	0	0	0
T24	22788	0	0	0
T25	95936	0	0	0
T28	237144	0	0	0
T34	0	130	0	0
T35	0	231	0	0
T36	22404	0	0	0
T37	44580	0	0	0
T38	112328	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2367	0	0
T2	199075	1	0	0
T3	107339	0	0	0
T4	42740	0	0	0
T5	0	3	0	0
T6	0	4	0	0
T7	795964	2	0	0
T8	730220	7	0	0
T11	64744	0	0	0
T12	64852	1	0	0
T13	83656	1	0	0
T14	51390	2	0	0
T15	1379292	1	0	0
T16	695817	1	0	0
T17	672357	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	275802	0	0	0
T21	176934	1	0	0
T22	0	2	0	0
T23	253136	3	0	0
T26	0	4	0	0
T28	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	66272	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111	0	0
T4	21370	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T18	104290	0	0	0
T20	91934	0	0	0
T21	176934	0	0	0
T23	63284	1	0	0
T24	0	1	0	0
T26	345218	1	0	0
T29	222245	0	0	0
T30	0	1	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T40	33136	0	0	0
T41	398140	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	371736	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	380899	0	0	0
T59	133153	0	0	0
T60	1502	0	0	0
T61	67381	0	0	0
T62	624577	0	0	0
T63	5936	0	0	0
T64	111371	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1124	0	0
T4	42740	0	0	0
T5	439288	5	0	0
T6	111293	3	0	0
T8	365110	5	0	0
T11	0	1	0	0
T13	20914	0	0	0
T14	17130	1	0	0
T15	344823	0	0	0
T16	463878	0	0	0
T17	448238	0	0	0
T18	104290	0	0	0
T19	114131	0	0	0
T20	183868	0	0	0
T21	176934	1	0	0
T23	126568	3	0	0
T24	0	2	0	0
T26	345218	19	0	0
T28	59286	2	0	0
T29	0	5	0	0
T30	0	4	0	0
T36	5601	0	0	0
T38	0	1	0	0
T39	1148	0	0	0
T40	66272	0	0	0
T41	0	11	0	0
T58	380899	1	0	0
T59	133153	4	0	0
T61	0	3	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1232309448	0	0
T1	434856	410291	0	0
T2	796300	599862	0	0
T3	429356	1101705	0	0
T7	1591928	819326	0	0
T8	730220	370856	0	0
T11	258976	85112	0	0
T12	129704	97644	0	0
T13	83656	67539	0	0
T14	68520	27162	0	0
T15	1379292	1039991	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2671	0	0
T2	199075	1	0	0
T3	107339	0	0	0
T4	21370	0	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	1193946	2	0	0
T8	730220	7	0	0
T11	129488	0	0	0
T12	97278	1	0	0
T13	83656	1	0	0
T14	51390	2	0	0
T15	1379292	1	0	0
T16	695817	1	0	0
T17	672357	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	183868	0	0	0
T21	176934	1	0	0
T22	0	2	0	0
T23	253136	4	0	0
T24	0	2	0	0
T26	0	8	0	0
T28	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	33136	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2616	0	0
T2	199075	1	0	0
T3	107339	0	0	0
T4	21370	0	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	1193946	2	0	0
T8	730220	7	0	0
T11	129488	0	0	0
T12	97278	1	0	0
T13	83656	1	0	0
T14	51390	2	0	0
T15	1379292	1	0	0
T16	695817	1	0	0
T17	672357	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	183868	0	0	0
T21	176934	1	0	0
T22	0	2	0	0
T23	253136	4	0	0
T24	0	2	0	0
T26	0	8	0	0
T28	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	33136	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2569	0	0
T2	199075	1	0	0
T3	107339	0	0	0
T4	21370	0	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	1193946	2	0	0
T8	730220	6	0	0
T11	129488	0	0	0
T12	97278	1	0	0
T13	83656	1	0	0
T14	51390	2	0	0
T15	1379292	1	0	0
T16	695817	1	0	0
T17	672357	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	183868	0	0	0
T21	176934	1	0	0
T22	0	2	0	0
T23	253136	4	0	0
T24	0	2	0	0
T26	0	8	0	0
T28	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	33136	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2517	0	0
T2	199075	1	0	0
T3	107339	0	0	0
T4	21370	0	0	0
T5	0	2	0	0
T6	0	1	0	0
T7	1193946	2	0	0
T8	730220	5	0	0
T11	129488	0	0	0
T12	97278	1	0	0
T13	83656	1	0	0
T14	51390	2	0	0
T15	1379292	1	0	0
T16	695817	1	0	0
T17	672357	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	183868	0	0	0
T21	176934	1	0	0
T22	0	2	0	0
T23	253136	4	0	0
T24	0	2	0	0
T26	0	8	0	0
T28	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	33136	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4178	0	0
T4	21370	0	0	0
T5	0	59	0	0
T6	0	1	0	0
T7	1193946	0	0	0
T8	547665	0	0	0
T11	194232	14	0	0
T12	97278	0	0	0
T13	62742	0	0	0
T14	51390	1	0	0
T15	1034469	0	0	0
T16	927756	0	0	0
T17	896476	0	0	0
T18	104290	0	0	0
T20	91934	12	0	0
T21	176934	0	0	0
T23	253136	1	0	0
T24	0	4	0	0
T25	0	1	0	0
T26	0	33	0	0
T29	0	65	0	0
T30	0	1	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T40	33136	0	0	0
T41	0	7	0	0
T44	0	1	0	0
T59	0	59	0	0
T61	0	2	0	0
T65	0	740	0	0
T66	0	3	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	527274	0	0
T4	21370	0	0	0
T5	0	6435	0	0
T6	0	85	0	0
T7	1193946	0	0	0
T8	547665	0	0	0
T11	194232	2608	0	0
T12	97278	0	0	0
T13	62742	0	0	0
T14	51390	116	0	0
T15	1034469	0	0	0
T16	927756	0	0	0
T17	896476	0	0	0
T18	104290	0	0	0
T20	91934	3718	0	0
T21	176934	0	0	0
T23	253136	1	0	0
T24	0	863	0	0
T25	0	51	0	0
T26	0	6154	0	0
T29	0	4143	0	0
T30	0	8	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T40	33136	0	0	0
T41	0	1093	0	0
T44	0	40	0	0
T59	0	6856	0	0
T61	0	259	0	0
T65	0	71565	0	0
T66	0	1546	0	0
T69	0	81	0	0
T70	0	26	0	0
T71	0	17	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3808	0	0
T4	21370	0	0	0
T5	439288	58	0	0
T6	0	1	0	0
T7	795964	0	0	0
T8	365110	0	0	0
T11	129488	12	0	0
T12	64852	0	0	0
T13	41828	0	0	0
T14	34260	1	0	0
T15	689646	0	0	0
T16	463878	0	0	0
T17	448238	0	0	0
T18	104290	0	0	0
T20	91934	12	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T23	126568	0	0	0
T24	5697	2	0	0
T25	23984	0	0	0
T26	0	22	0	0
T29	0	62	0	0
T31	0	1	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T40	33136	0	0	0
T41	0	2	0	0
T44	0	26	0	0
T59	0	56	0	0
T61	0	2	0	0
T65	0	740	0	0
T66	0	2	0	0
T69	0	5	0	0
T70	0	1	0	0
T72	0	7	0	0
T73	0	13	0	0
T74	0	1	0	0
T75	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	255	0	0
T5	878576	0	0	0
T6	222586	0	0	0
T7	397982	0	0	0
T11	64744	2	0	0
T19	228262	0	0	0
T22	373975	0	0	0
T24	5697	1	0	0
T25	47968	1	0	0
T26	1035654	10	0	0
T28	118572	0	0	0
T29	222245	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T38	56164	0	0	0
T39	2296	0	0	0
T41	398140	3	0	0
T44	0	1	0	0
T46	0	2	0	0
T49	0	5	0	0
T58	761798	0	0	0
T59	266306	3	0	0
T60	1502	0	0	0
T61	67381	0	0	0
T62	624577	0	0	0
T63	5936	0	0	0
T64	111371	0	0	0
T65	0	2	0	0
T66	0	7	0	0
T67	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	7	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4572	0	0
T4	85480	698	0	0
T9	0	1268	0	0
T10	0	624	0	0
T18	417160	0	0	0
T21	707736	0	0	0
T22	1495900	0	0	0
T24	22788	0	0	0
T25	95936	0	0	0
T28	237144	0	0	0
T34	0	669	0	0
T35	0	1313	0	0
T36	22404	0	0	0
T37	44580	0	0	0
T38	112328	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3732	0	0
T4	85480	578	0	0
T9	0	1028	0	0
T10	0	504	0	0
T18	417160	0	0	0
T21	707736	0	0	0
T22	1495900	0	0	0
T24	22788	0	0	0
T25	95936	0	0	0
T28	237144	0	0	0
T34	0	549	0	0
T35	0	1073	0	0
T36	22404	0	0	0
T37	44580	0	0	0
T38	112328	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	434856	434600	0	0
T2	796300	795984	0	0
T3	429356	429328	0	0
T7	1591928	1591892	0	0
T8	730220	730180	0	0
T11	258976	258716	0	0
T12	129704	129420	0	0
T13	83656	83256	0	0
T14	68520	68312	0	0
T15	1379292	1379000	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	434856	434600	0	0
T2	796300	795984	0	0
T3	429356	429328	0	0
T7	1591928	1591892	0	0
T8	730220	730180	0	0
T11	258976	258716	0	0
T12	129704	129420	0	0
T13	83656	83256	0	0
T14	68520	68312	0	0
T15	1379292	1379000	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T2,T7,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T23,T20,T21
1	0	1	Covered	T2,T7,T16
1	1	0	Covered	T11,T13,T40
1	1	1	Covered	T23,T20,T24

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T23,T20,T24
0	1	Covered	T25,T26,T29
1	0	Covered	T23,T24,T42

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T23,T20,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T24,T42

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T20,T24
1	0	Not Covered
1	1	Covered	T25,T26,T29

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T12,T8
1	Covered	T2,T14,T23

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T28,T5,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T8,T21,T24

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T14,T8
1	Covered	T7,T12,T23

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T2,T7,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T2,T14,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T2,T8,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T7,T12,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T7,T12
Phase1St	198	Covered	T2,T7,T12
Phase2St	215	Covered	T2,T7,T12
Phase3St	233	Covered	T2,T7,T12
TerminalSt	249	Covered	T2,T7,T12
TimeoutSt	159	Covered	T23,T20,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T9,T10
IdleSt->Phase0St	152	Covered	T2,T7,T12
IdleSt->TimeoutSt	159	Covered	T23,T20,T24
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T30,T79
Phase0St->Phase1St	198	Covered	T2,T7,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T33,T80,T48
Phase1St->Phase2St	215	Covered	T2,T7,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T48,T51
Phase2St->Phase3St	233	Covered	T2,T7,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T65,T49,T81
Phase3St->TerminalSt	249	Covered	T2,T7,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T14,T23,T24
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T20,T24,T5
TimeoutSt->Phase0St	172	Covered	T23,T24,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T20,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T23,T20,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T24,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T30,T79
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T7,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T7,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T33,T80,T48
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T7,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T7,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T48,T51
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T7,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T7,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T65,T49,T81
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T7,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T7,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T23,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T7,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	707762413	210	0	0
CheckAccumTrig0_A	707762413	872	0	0
CheckAccumTrig1_A	707762413	38	0	0
CheckClr_A	707762413	437	0	0
CheckEn_A	707636586	251040390	0	0
CheckPhase0_A	707762413	957	0	0
CheckPhase1_A	707762413	941	0	0
CheckPhase2_A	707762413	918	0	0
CheckPhase3_A	707762413	898	0	0
CheckTimeout0_A	707762413	752	0	0
CheckTimeoutSt1_A	707762413	95152	0	0
CheckTimeoutSt2_A	707762413	643	0	0
CheckTimeoutStTrig_A	707762413	69	0	0
ErrorStAllEscAsserted_A	707762413	1216	0	0
ErrorStIsTerminal_A	707762413	1006	0	0
EscStateOut_A	707635597	707567937	0	0
u_state_regs_A	707762413	707605749	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	210	0	0
T4	21370	30	0	0
T9	0	70	0	0
T10	0	25	0	0
T18	104290	0	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T34	0	24	0	0
T35	0	61	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T38	28082	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	872	0	0
T2	199075	1	0	0
T3	107339	0	0	0
T7	397982	1	0	0
T8	182555	1	0	0
T11	64744	0	0	0
T12	32426	1	0	0
T13	20914	0	0	0
T14	17130	2	0	0
T15	344823	0	0	0
T17	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	63284	3	0	0
T38	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	38	0	0
T4	21370	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T18	104290	0	0	0
T20	91934	0	0	0
T21	176934	0	0	0
T23	63284	1	0	0
T24	0	1	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T40	33136	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	437	0	0
T4	21370	0	0	0
T5	0	3	0	0
T6	0	1	0	0
T8	182555	0	0	0
T13	20914	0	0	0
T14	17130	1	0	0
T15	344823	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T20	91934	0	0	0
T23	63284	3	0	0
T24	0	1	0	0
T26	0	9	0	0
T28	0	1	0	0
T29	0	1	0	0
T38	0	1	0	0
T40	33136	0	0	0
T41	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707636586	251040390	0	0
T1	108714	99857	0	0
T2	199075	6466	0	0
T3	107339	818267	0	0
T7	397982	21710	0	0
T8	182555	6023	0	0
T11	64744	64678	0	0
T12	32426	582	0	0
T13	20914	20813	0	0
T14	17130	2108	0	0
T15	344823	344749	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	957	0	0
T2	199075	1	0	0
T3	107339	0	0	0
T7	397982	1	0	0
T8	182555	1	0	0
T11	64744	0	0	0
T12	32426	1	0	0
T13	20914	0	0	0
T14	17130	2	0	0
T15	344823	0	0	0
T17	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	63284	4	0	0
T24	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	941	0	0
T2	199075	1	0	0
T3	107339	0	0	0
T7	397982	1	0	0
T8	182555	1	0	0
T11	64744	0	0	0
T12	32426	1	0	0
T13	20914	0	0	0
T14	17130	2	0	0
T15	344823	0	0	0
T17	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	63284	4	0	0
T24	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	918	0	0
T2	199075	1	0	0
T3	107339	0	0	0
T7	397982	1	0	0
T8	182555	1	0	0
T11	64744	0	0	0
T12	32426	1	0	0
T13	20914	0	0	0
T14	17130	2	0	0
T15	344823	0	0	0
T17	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	63284	4	0	0
T24	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	898	0	0
T2	199075	1	0	0
T3	107339	0	0	0
T7	397982	1	0	0
T8	182555	1	0	0
T11	64744	0	0	0
T12	32426	1	0	0
T13	20914	0	0	0
T14	17130	2	0	0
T15	344823	0	0	0
T17	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	63284	4	0	0
T24	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	752	0	0
T4	21370	0	0	0
T5	0	1	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T18	104290	0	0	0
T20	91934	12	0	0
T21	176934	0	0	0
T23	63284	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T26	0	12	0	0
T29	0	14	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T40	33136	0	0	0
T41	0	2	0	0
T59	0	2	0	0
T61	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	95152	0	0
T4	21370	0	0	0
T5	0	170	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T18	104290	0	0	0
T20	91934	3718	0	0
T21	176934	0	0	0
T23	63284	1	0	0
T24	0	88	0	0
T25	0	51	0	0
T26	0	2461	0	0
T29	0	942	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T40	33136	0	0	0
T41	0	342	0	0
T59	0	374	0	0
T61	0	43	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	643	0	0
T4	21370	0	0	0
T5	0	1	0	0
T18	104290	0	0	0
T20	91934	12	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	1	0	0
T25	23984	0	0	0
T26	0	9	0	0
T29	0	13	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T40	33136	0	0	0
T41	0	2	0	0
T59	0	2	0	0
T61	0	1	0	0
T65	0	2	0	0
T69	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	69	0	0
T5	439288	0	0	0
T6	111293	0	0	0
T19	114131	0	0	0
T25	23984	1	0	0
T26	345218	3	0	0
T28	59286	0	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T38	28082	0	0	0
T39	1148	0	0	0
T49	0	2	0	0
T58	380899	0	0	0
T59	133153	0	0	0
T66	0	4	0	0
T73	0	1	0	0
T74	0	2	0	0
T78	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	1216	0	0
T4	21370	182	0	0
T9	0	360	0	0
T10	0	160	0	0
T18	104290	0	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T34	0	156	0	0
T35	0	358	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T38	28082	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	1006	0	0
T4	21370	152	0	0
T9	0	300	0	0
T10	0	130	0	0
T18	104290	0	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T34	0	126	0	0
T35	0	298	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T38	28082	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707635597	707567937	0	0
T1	108714	108650	0	0
T2	199075	198996	0	0
T3	107339	107332	0	0
T7	397982	397973	0	0
T8	182555	182545	0	0
T11	64744	64679	0	0
T12	32426	32355	0	0
T13	20914	20814	0	0
T14	17130	17078	0	0
T15	344823	344750	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	707605749	0	0
T1	108714	108650	0	0
T2	199075	198996	0	0
T3	107339	107332	0	0
T7	397982	397973	0	0
T8	182555	182545	0	0
T11	64744	64679	0	0
T12	32426	32355	0	0
T13	20914	20814	0	0
T14	17130	17078	0	0
T15	344823	344750	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T11,T7,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T11,T7,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T7,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T13,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T14,T13
1	0	1	Covered	T2,T16,T36
1	1	0	Covered	T14,T13,T20
1	1	1	Covered	T11,T24,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T24,T5
0	1	Covered	T24,T26,T59
1	0	Covered	T26,T41,T30

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T11,T24,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T41,T30

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T24,T5
1	0	Not Covered
1	1	Covered	T24,T26,T59

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T8,T22
1	Covered	T13,T16,T36

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T13,T8,T16
1	Covered	T7,T19,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T13,T8
1	Covered	T22,T5,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T13,T16
1	Covered	T8,T5,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T7,T8,T36

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T13,T36,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T7,T8,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T13,T8,T36

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T7,T13,T8
Phase1St	198	Covered	T7,T13,T8
Phase2St	215	Covered	T7,T13,T8
Phase3St	233	Covered	T7,T13,T8
TerminalSt	249	Covered	T7,T13,T8
TimeoutSt	159	Covered	T11,T24,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T9,T10
IdleSt->Phase0St	152	Covered	T7,T13,T8
IdleSt->TimeoutSt	159	Covered	T11,T24,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T30,T44
Phase0St->Phase1St	198	Covered	T7,T13,T8
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T32,T53,T82
Phase1St->Phase2St	215	Covered	T7,T13,T8
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T8,T33,T53
Phase2St->Phase3St	233	Covered	T7,T13,T8
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T8,T5,T29
Phase3St->TerminalSt	249	Covered	T7,T13,T8
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T8,T24,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T11,T24,T5
TimeoutSt->Phase0St	172	Covered	T24,T26,T59

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T13,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T24,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T26,T59
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T24,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T11,T24,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T30,T33
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T7,T13,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T7,T13,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T53,T82
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T7,T13,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T7,T13,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T33,T53
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T7,T13,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T7,T13,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T8,T5,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T7,T13,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T7,T13,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T24,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T7,T13,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	707762413	217	0	0
CheckAccumTrig0_A	707762413	496	0	0
CheckAccumTrig1_A	707762413	27	0	0
CheckClr_A	707762413	239	0	0
CheckEn_A	707636586	303479615	0	0
CheckPhase0_A	707762413	571	0	0
CheckPhase1_A	707762413	559	0	0
CheckPhase2_A	707762413	548	0	0
CheckPhase3_A	707762413	542	0	0
CheckTimeout0_A	707762413	1318	0	0
CheckTimeoutSt1_A	707762413	163150	0	0
CheckTimeoutSt2_A	707762413	1227	0	0
CheckTimeoutStTrig_A	707762413	63	0	0
ErrorStAllEscAsserted_A	707762413	1155	0	0
ErrorStIsTerminal_A	707762413	945	0	0
EscStateOut_A	707635597	707567937	0	0
u_state_regs_A	707762413	707605749	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	217	0	0
T4	21370	19	0	0
T9	0	75	0	0
T10	0	32	0	0
T18	104290	0	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T34	0	46	0	0
T35	0	45	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T38	28082	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	496	0	0
T5	0	3	0	0
T6	0	2	0	0
T7	397982	1	0	0
T8	182555	6	0	0
T12	32426	0	0	0
T13	20914	1	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	1	0	0
T17	224119	0	0	0
T19	0	1	0	0
T20	91934	0	0	0
T22	0	1	0	0
T23	63284	0	0	0
T36	0	1	0	0
T39	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	27	0	0
T26	345218	1	0	0
T29	222245	0	0	0
T30	0	1	0	0
T41	398140	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	380899	0	0	0
T59	133153	0	0	0
T60	1502	0	0	0
T61	67381	0	0	0
T62	624577	0	0	0
T63	5936	0	0	0
T64	111371	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	239	0	0
T4	21370	0	0	0
T5	0	2	0	0
T6	0	1	0	0
T8	182555	5	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T18	104290	0	0	0
T20	91934	0	0	0
T21	176934	0	0	0
T23	63284	0	0	0
T24	0	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T36	5601	0	0	0
T40	33136	0	0	0
T41	0	4	0	0
T61	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707636586	303479615	0	0
T1	108714	105444	0	0
T2	199075	195406	0	0
T3	107339	68774	0	0
T7	397982	2676	0	0
T8	182555	586	0	0
T11	64744	8753	0	0
T12	32426	32354	0	0
T13	20914	5100	0	0
T14	17130	11830	0	0
T15	344823	344749	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	571	0	0
T5	0	3	0	0
T7	397982	1	0	0
T8	182555	6	0	0
T12	32426	0	0	0
T13	20914	1	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	1	0	0
T17	224119	0	0	0
T19	0	1	0	0
T20	91934	0	0	0
T22	0	1	0	0
T23	63284	0	0	0
T24	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	559	0	0
T5	0	3	0	0
T7	397982	1	0	0
T8	182555	6	0	0
T12	32426	0	0	0
T13	20914	1	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	1	0	0
T17	224119	0	0	0
T19	0	1	0	0
T20	91934	0	0	0
T22	0	1	0	0
T23	63284	0	0	0
T24	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	548	0	0
T5	0	3	0	0
T7	397982	1	0	0
T8	182555	5	0	0
T12	32426	0	0	0
T13	20914	1	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	1	0	0
T17	224119	0	0	0
T19	0	1	0	0
T20	91934	0	0	0
T22	0	1	0	0
T23	63284	0	0	0
T24	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	542	0	0
T5	0	2	0	0
T7	397982	1	0	0
T8	182555	4	0	0
T12	32426	0	0	0
T13	20914	1	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	1	0	0
T17	224119	0	0	0
T19	0	1	0	0
T20	91934	0	0	0
T22	0	1	0	0
T23	63284	0	0	0
T24	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	1318	0	0
T5	0	31	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	6	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T23	63284	0	0	0
T24	0	2	0	0
T26	0	4	0	0
T29	0	18	0	0
T30	0	1	0	0
T41	0	3	0	0
T59	0	4	0	0
T65	0	348	0	0
T66	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	163150	0	0
T5	0	3447	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	1198	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T23	63284	0	0	0
T24	0	775	0	0
T26	0	617	0	0
T29	0	1168	0	0
T30	0	8	0	0
T41	0	78	0	0
T59	0	450	0	0
T65	0	33483	0	0
T66	0	1546	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	1227	0	0
T5	0	31	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	6	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T23	63284	0	0	0
T24	0	1	0	0
T26	0	2	0	0
T29	0	18	0	0
T44	0	26	0	0
T59	0	3	0	0
T65	0	347	0	0
T66	0	1	0	0
T72	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	63	0	0
T5	439288	0	0	0
T6	111293	0	0	0
T19	114131	0	0	0
T22	373975	0	0	0
T24	5697	1	0	0
T25	23984	0	0	0
T26	345218	1	0	0
T28	59286	0	0	0
T38	28082	0	0	0
T39	1148	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T59	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T74	0	4	0	0
T76	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	1155	0	0
T4	21370	171	0	0
T9	0	311	0	0
T10	0	175	0	0
T18	104290	0	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T34	0	172	0	0
T35	0	326	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T38	28082	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	945	0	0
T4	21370	141	0	0
T9	0	251	0	0
T10	0	145	0	0
T18	104290	0	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T34	0	142	0	0
T35	0	266	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T38	28082	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707635597	707567937	0	0
T1	108714	108650	0	0
T2	199075	198996	0	0
T3	107339	107332	0	0
T7	397982	397973	0	0
T8	182555	182545	0	0
T11	64744	64679	0	0
T12	32426	32355	0	0
T13	20914	20814	0	0
T14	17130	17078	0	0
T15	344823	344750	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	707605749	0	0
T1	108714	108650	0	0
T2	199075	198996	0	0
T3	107339	107332	0	0
T7	397982	397973	0	0
T8	182555	182545	0	0
T11	64744	64679	0	0
T12	32426	32355	0	0
T13	20914	20814	0	0
T14	17130	17078	0	0
T15	344823	344750	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T11,T14,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T11,T14,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T14,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T11,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T14,T16,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T5,T6
1	0	1	Covered	T1,T14,T8
1	1	0	Covered	T13,T20,T21
1	1	1	Covered	T11,T5,T26

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T5,T26
0	1	Covered	T11,T5,T26
1	0	Covered	T29,T44,T83

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T11,T5,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T29,T44,T83

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T5,T26
1	0	Not Covered
1	1	Covered	T11,T5,T26

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T14,T16
1	Covered	T11,T21,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T14,T17
1	Covered	T11,T16,T26

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T16,T17
1	Covered	T14,T26,T59

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T14,T16
1	Covered	T17,T5,T59

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T11,T16,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T11,T21,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T11,T16,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T11,T14,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T11,T14,T16
Phase1St	198	Covered	T11,T14,T16
Phase2St	215	Covered	T11,T14,T16
Phase3St	233	Covered	T11,T14,T16
TerminalSt	249	Covered	T11,T14,T16
TimeoutSt	159	Covered	T11,T5,T26

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T9,T10
IdleSt->Phase0St	152	Covered	T14,T16,T17
IdleSt->TimeoutSt	159	Covered	T11,T5,T26
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T32,T84,T85
Phase0St->Phase1St	198	Covered	T11,T14,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T21,T30,T86
Phase1St->Phase2St	215	Covered	T11,T14,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T87,T88
Phase2St->Phase3St	233	Covered	T11,T14,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T59,T29,T55
Phase3St->TerminalSt	249	Covered	T11,T14,T16
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T11,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T26,T59
TimeoutSt->Phase0St	172	Covered	T11,T5,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T16,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T5,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T5,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T5,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T26,T59
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T84,T85,T89
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T11,T14,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T11,T14,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T21,T30,T90
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T11,T14,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T11,T14,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T87,T88
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T11,T14,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T11,T14,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T59,T29,T55
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T11,T14,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T11,T14,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T11,T26,T59
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T11,T14,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	707762413	212	0	0
CheckAccumTrig0_A	707762413	508	0	0
CheckAccumTrig1_A	707762413	18	0	0
CheckClr_A	707762413	221	0	0
CheckEn_A	707636586	324251969	0	0
CheckPhase0_A	707762413	579	0	0
CheckPhase1_A	707762413	561	0	0
CheckPhase2_A	707762413	553	0	0
CheckPhase3_A	707762413	543	0	0
CheckTimeout0_A	707762413	809	0	0
CheckTimeoutSt1_A	707762413	122268	0	0
CheckTimeoutSt2_A	707762413	725	0	0
CheckTimeoutStTrig_A	707762413	65	0	0
ErrorStAllEscAsserted_A	707762413	1099	0	0
ErrorStIsTerminal_A	707762413	889	0	0
EscStateOut_A	707635597	707567937	0	0
u_state_regs_A	707762413	707605749	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	212	0	0
T4	21370	31	0	0
T9	0	42	0	0
T10	0	38	0	0
T18	104290	0	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T34	0	41	0	0
T35	0	60	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T38	28082	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	508	0	0
T4	21370	0	0	0
T6	0	1	0	0
T8	182555	0	0	0
T13	20914	0	0	0
T14	17130	1	0	0
T15	344823	0	0	0
T16	231939	1	0	0
T17	224119	1	0	0
T18	0	1	0	0
T20	91934	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	63284	0	0	0
T26	0	7	0	0
T40	33136	0	0	0
T58	0	1	0	0
T59	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	18	0	0
T29	222245	1	0	0
T30	495208	0	0	0
T44	0	1	0	0
T63	5936	0	0	0
T64	111371	0	0	0
T65	376830	0	0	0
T66	38401	0	0	0
T69	8022	0	0	0
T83	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	3033	0	0	0
T99	358199	0	0	0
T100	6535	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	221	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	1	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T21	0	1	0	0
T23	63284	0	0	0
T26	0	5	0	0
T29	0	1	0	0
T30	0	3	0	0
T41	0	1	0	0
T59	0	2	0	0
T61	0	2	0	0
T70	0	1	0	0
T101	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707636586	324251969	0	0
T1	108714	105452	0	0
T2	199075	198995	0	0
T3	107339	107332	0	0
T7	397982	397973	0	0
T8	182555	181702	0	0
T11	64744	8517	0	0
T12	32426	32354	0	0
T13	20914	20813	0	0
T14	17130	2152	0	0
T15	344823	344749	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	579	0	0
T5	0	1	0	0
T6	0	1	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	2	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	1	0	0
T15	344823	0	0	0
T16	231939	1	0	0
T17	224119	1	0	0
T18	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	63284	0	0	0
T26	0	9	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	561	0	0
T5	0	1	0	0
T6	0	1	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	2	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	1	0	0
T15	344823	0	0	0
T16	231939	1	0	0
T17	224119	1	0	0
T18	0	1	0	0
T22	0	1	0	0
T23	63284	0	0	0
T26	0	9	0	0
T58	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	553	0	0
T5	0	1	0	0
T6	0	1	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	2	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	1	0	0
T15	344823	0	0	0
T16	231939	1	0	0
T17	224119	1	0	0
T18	0	1	0	0
T22	0	1	0	0
T23	63284	0	0	0
T26	0	9	0	0
T58	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	543	0	0
T5	0	1	0	0
T6	0	1	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	2	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	1	0	0
T15	344823	0	0	0
T16	231939	1	0	0
T17	224119	1	0	0
T18	0	1	0	0
T22	0	1	0	0
T23	63284	0	0	0
T26	0	9	0	0
T58	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	809	0	0
T5	0	24	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	2	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T23	63284	0	0	0
T26	0	3	0	0
T29	0	16	0	0
T41	0	1	0	0
T44	0	1	0	0
T59	0	52	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	122268	0	0
T5	0	2306	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	135	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T23	63284	0	0	0
T26	0	521	0	0
T29	0	918	0	0
T41	0	646	0	0
T44	0	40	0	0
T59	0	5883	0	0
T69	0	81	0	0
T70	0	26	0	0
T71	0	17	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	725	0	0
T5	439288	23	0	0
T6	111293	0	0	0
T26	345218	1	0	0
T29	222245	14	0	0
T31	0	1	0	0
T41	398140	0	0	0
T58	380899	0	0	0
T59	133153	51	0	0
T60	1502	0	0	0
T61	67381	0	0	0
T62	624577	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T73	0	13	0	0
T74	0	1	0	0
T75	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	65	0	0
T5	0	1	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	2	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	0	0	0
T15	344823	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T23	63284	0	0	0
T26	0	2	0	0
T29	0	1	0	0
T32	0	1	0	0
T41	0	1	0	0
T59	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	1099	0	0
T4	21370	179	0	0
T9	0	299	0	0
T10	0	135	0	0
T18	104290	0	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T34	0	169	0	0
T35	0	317	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T38	28082	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	889	0	0
T4	21370	149	0	0
T9	0	239	0	0
T10	0	105	0	0
T18	104290	0	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T34	0	139	0	0
T35	0	257	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T38	28082	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707635597	707567937	0	0
T1	108714	108650	0	0
T2	199075	198996	0	0
T3	107339	107332	0	0
T7	397982	397973	0	0
T8	182555	182545	0	0
T11	64744	64679	0	0
T12	32426	32355	0	0
T13	20914	20814	0	0
T14	17130	17078	0	0
T15	344823	344750	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	707605749	0	0
T1	108714	108650	0	0
T2	199075	198996	0	0
T3	107339	107332	0	0
T7	397982	397973	0	0
T8	182555	182545	0	0
T11	64744	64679	0	0
T12	32426	32355	0	0
T13	20914	20814	0	0
T14	17130	17078	0	0
T15	344823	344750	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T11,T14,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T11,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T14,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T11,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T18,T28

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T14,T20
1	0	1	Covered	T16,T18,T37
1	1	0	Covered	T13,T20,T21
1	1	1	Covered	T11,T14,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T14,T5
0	1	Covered	T26,T59,T41
1	0	Covered	T44,T74,T90

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T11,T14,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T44,T74,T90

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T14,T5
1	0	Covered	T27
1	1	Covered	T26,T59,T41

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T6,T26
1	Covered	T18,T28,T26

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T18,T28,T6
1	Covered	T15,T26,T58

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T18,T28
1	Covered	T26,T41,T65

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T18,T28
1	Covered	T6,T59,T41

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T15,T18,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T15,T28,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T15,T26,T59

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T15,T28,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T15,T18,T28
Phase1St	198	Covered	T15,T18,T28
Phase2St	215	Covered	T15,T18,T28
Phase3St	233	Covered	T15,T18,T28
TerminalSt	249	Covered	T15,T18,T28
TimeoutSt	159	Covered	T11,T14,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T9,T10
IdleSt->Phase0St	152	Covered	T15,T18,T28
IdleSt->TimeoutSt	159	Covered	T11,T14,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T29,T67
Phase0St->Phase1St	198	Covered	T15,T18,T28
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T73,T92
Phase1St->Phase2St	215	Covered	T15,T18,T28
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T33,T102,T103
Phase2St->Phase3St	233	Covered	T15,T18,T28
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T104,T31,T73
Phase3St->TerminalSt	249	Covered	T15,T18,T28
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T28,T26,T58
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T11,T14,T5
TimeoutSt->Phase0St	172	Covered	T26,T59,T41

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T18,T28
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T14,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T59,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T14,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T11,T14,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T29,T67
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T15,T18,T28
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T15,T18,T28
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T73,T92
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T15,T18,T28
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T15,T18,T28
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T102,T103
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T15,T18,T28
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T15,T18,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T104,T31,T73
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T15,T18,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T15,T18,T28
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T28,T26,T58
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T15,T18,T28
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	707762413	169	0	0
CheckAccumTrig0_A	707762413	491	0	0
CheckAccumTrig1_A	707762413	28	0	0
CheckClr_A	707762413	227	0	0
CheckEn_A	707636586	353537474	0	0
CheckPhase0_A	707762413	564	0	0
CheckPhase1_A	707762413	555	0	0
CheckPhase2_A	707762413	550	0	0
CheckPhase3_A	707762413	534	0	0
CheckTimeout0_A	707762413	1299	0	0
CheckTimeoutSt1_A	707762413	146704	0	0
CheckTimeoutSt2_A	707762413	1213	0	0
CheckTimeoutStTrig_A	707762413	58	0	0
ErrorStAllEscAsserted_A	707762413	1102	0	0
ErrorStIsTerminal_A	707762413	892	0	0
EscStateOut_A	707635597	707567937	0	0
u_state_regs_A	707762413	707605749	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	169	0	0
T4	21370	35	0	0
T9	0	28	0	0
T10	0	22	0	0
T18	104290	0	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T34	0	19	0	0
T35	0	65	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T38	28082	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	491	0	0
T4	21370	0	0	0
T6	0	2	0	0
T8	182555	0	0	0
T13	20914	0	0	0
T15	344823	1	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T18	0	1	0	0
T20	91934	0	0	0
T21	176934	0	0	0
T23	63284	0	0	0
T26	0	4	0	0
T28	0	1	0	0
T40	33136	0	0	0
T41	0	3	0	0
T58	0	1	0	0
T59	0	4	0	0
T60	0	1	0	0
T61	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	28	0	0
T31	184524	0	0	0
T44	371736	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T73	567650	0	0	0
T74	0	1	0	0
T90	0	1	0	0
T92	0	1	0	0
T104	434090	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	2	0	0
T109	6640	0	0	0
T110	7043	0	0	0
T111	31217	0	0	0
T112	331111	0	0	0
T113	148610	0	0	0
T114	177072	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	227	0	0
T5	439288	0	0	0
T6	111293	1	0	0
T19	114131	0	0	0
T26	345218	5	0	0
T28	59286	1	0	0
T29	0	1	0	0
T39	1148	0	0	0
T41	398140	3	0	0
T58	380899	1	0	0
T59	133153	2	0	0
T60	1502	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707636586	353537474	0	0
T1	108714	99538	0	0
T2	199075	198995	0	0
T3	107339	107332	0	0
T7	397982	396967	0	0
T8	182555	182545	0	0
T11	64744	3164	0	0
T12	32426	32354	0	0
T13	20914	20813	0	0
T14	17130	11072	0	0
T15	344823	5744	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	564	0	0
T4	21370	0	0	0
T6	0	1	0	0
T8	182555	0	0	0
T13	20914	0	0	0
T15	344823	1	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T18	0	1	0	0
T20	91934	0	0	0
T21	176934	0	0	0
T23	63284	0	0	0
T26	0	8	0	0
T28	0	1	0	0
T40	33136	0	0	0
T41	0	4	0	0
T58	0	1	0	0
T59	0	5	0	0
T60	0	1	0	0
T61	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	555	0	0
T4	21370	0	0	0
T6	0	1	0	0
T8	182555	0	0	0
T13	20914	0	0	0
T15	344823	1	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T18	0	1	0	0
T20	91934	0	0	0
T21	176934	0	0	0
T23	63284	0	0	0
T26	0	8	0	0
T28	0	1	0	0
T40	33136	0	0	0
T41	0	4	0	0
T58	0	1	0	0
T59	0	5	0	0
T60	0	1	0	0
T61	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	550	0	0
T4	21370	0	0	0
T6	0	1	0	0
T8	182555	0	0	0
T13	20914	0	0	0
T15	344823	1	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T18	0	1	0	0
T20	91934	0	0	0
T21	176934	0	0	0
T23	63284	0	0	0
T26	0	8	0	0
T28	0	1	0	0
T40	33136	0	0	0
T41	0	4	0	0
T58	0	1	0	0
T59	0	5	0	0
T60	0	1	0	0
T61	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	534	0	0
T4	21370	0	0	0
T6	0	1	0	0
T8	182555	0	0	0
T13	20914	0	0	0
T15	344823	1	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T18	0	1	0	0
T20	91934	0	0	0
T21	176934	0	0	0
T23	63284	0	0	0
T26	0	8	0	0
T28	0	1	0	0
T40	33136	0	0	0
T41	0	4	0	0
T58	0	1	0	0
T59	0	5	0	0
T60	0	1	0	0
T61	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	1299	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	6	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	1	0	0
T15	344823	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T23	63284	0	0	0
T26	0	14	0	0
T29	0	17	0	0
T41	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T65	0	392	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	146704	0	0
T5	0	512	0	0
T6	0	85	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	1275	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	116	0	0
T15	344823	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T23	63284	0	0	0
T26	0	2555	0	0
T29	0	1115	0	0
T41	0	27	0	0
T59	0	149	0	0
T61	0	216	0	0
T65	0	38082	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	1213	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	397982	0	0	0
T8	182555	0	0	0
T11	64744	6	0	0
T12	32426	0	0	0
T13	20914	0	0	0
T14	17130	1	0	0
T15	344823	0	0	0
T16	231939	0	0	0
T17	224119	0	0	0
T23	63284	0	0	0
T26	0	10	0	0
T29	0	17	0	0
T61	0	1	0	0
T65	0	391	0	0
T66	0	1	0	0
T69	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	58	0	0
T26	345218	4	0	0
T29	222245	0	0	0
T41	398140	1	0	0
T46	0	1	0	0
T49	0	3	0	0
T58	380899	0	0	0
T59	133153	1	0	0
T60	1502	0	0	0
T61	67381	0	0	0
T62	624577	0	0	0
T63	5936	0	0	0
T64	111371	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T72	0	1	0	0
T77	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	1102	0	0
T4	21370	166	0	0
T9	0	298	0	0
T10	0	154	0	0
T18	104290	0	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T34	0	172	0	0
T35	0	312	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T38	28082	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	892	0	0
T4	21370	136	0	0
T9	0	238	0	0
T10	0	124	0	0
T18	104290	0	0	0
T21	176934	0	0	0
T22	373975	0	0	0
T24	5697	0	0	0
T25	23984	0	0	0
T28	59286	0	0	0
T34	0	142	0	0
T35	0	252	0	0
T36	5601	0	0	0
T37	11145	0	0	0
T38	28082	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707635597	707567937	0	0
T1	108714	108650	0	0
T2	199075	198996	0	0
T3	107339	107332	0	0
T7	397982	397973	0	0
T8	182555	182545	0	0
T11	64744	64679	0	0
T12	32426	32355	0	0
T13	20914	20814	0	0
T14	17130	17078	0	0
T15	344823	344750	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707762413	707605749	0	0
T1	108714	108650	0	0
T2	199075	198996	0	0
T3	107339	107332	0	0
T7	397982	397973	0	0
T8	182555	182545	0	0
T11	64744	64679	0	0
T12	32426	32355	0	0
T13	20914	20814	0	0
T14	17130	17078	0	0
T15	344823	344750	0	0