Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=6 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 70173 70173 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 2147483647 2147483647 0 89424
gen_no_flops.OutputDelay_A 2147483647 2147483647 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 70173 70173 0 0
T1 113 113 0 0
T2 113 113 0 0
T3 113 113 0 0
T7 113 113 0 0
T11 113 113 0 0
T12 113 113 0 0
T13 113 113 0 0
T14 113 113 0 0
T15 113 113 0 0
T20 113 113 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 47621816 47621251 0 0
T2 1630590 1619742 0 0
T3 30350896 30349992 0 0
T7 54690870 54690305 0 0
T11 42105269 42104252 0 0
T12 48523895 48515194 0 0
T13 17541555 17540990 0 0
T14 90074560 90065972 0 0
T15 11424074 11423057 0 0
T20 2474926 2467242 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 89424
T1 20228736 20228448 0 144
T2 692640 687888 0 144
T3 12892416 12892032 0 144
T7 23231520 23231232 0 144
T11 17885424 17884992 0 144
T12 20611920 20608080 0 144
T13 7451280 7450992 0 144
T14 38261760 38257968 0 144
T15 4852704 4852224 0 144
T20 1051296 1047888 0 144

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 27393080 27392755 0 0
T2 937950 931710 0 0
T3 17458480 17457960 0 0
T7 31459350 31459025 0 0
T11 24219845 24219260 0 0
T12 27911975 27906970 0 0
T13 10090275 10089950 0 0
T14 51812800 51807860 0 0
T15 6571370 6570785 0 0
T20 1423630 1419210 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 670495040 670303880 0 1863


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670303880 0 1863
T1 421432 421426 0 3
T2 14430 14331 0 3
T3 268592 268584 0 3
T7 483990 483984 0 3
T11 372613 372604 0 3
T12 429415 429335 0 3
T13 155235 155229 0 3
T14 797120 797041 0 3
T15 101098 101088 0 3
T20 21902 21831 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 621 621 0 0
OutputsKnown_A 670495040 670311745 0 0
gen_no_flops.OutputDelay_A 670495040 670311745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 621 621 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 670495040 670311745 0 0
T1 421432 421427 0 0
T2 14430 14334 0 0
T3 268592 268584 0 0
T7 483990 483985 0 0
T11 372613 372604 0 0
T12 429415 429338 0 0
T13 155235 155230 0 0
T14 797120 797044 0 0
T15 101098 101089 0 0
T20 21902 21834 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%