Unified Coverage Report :: Module :: prim_esc_sender

Module : prim_esc_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_esc_sev[0].u_esc_sender	100.00			100.00
tb.dut.gen_esc_sev[1].u_esc_sender	100.00			100.00
tb.dut.gen_esc_sev[2].u_esc_sender	100.00			100.00
tb.dut.gen_esc_sev[3].u_esc_sender	100.00			100.00

---

Module Instance : tb.dut.gen_esc_sev[0].u_esc_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_esc_sev[1].u_esc_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_esc_sev[2].u_esc_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_esc_sev[3].u_esc_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_esc_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
ping_ok_o	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
integ_fail_o	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	OUTPUT
esc_req_i	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
esc_rx_i.resp_n	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
esc_rx_i.resp_p	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
esc_tx_o.esc_n	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	OUTPUT
esc_tx_o.esc_p	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_esc_sev[0].u_esc_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
ping_ok_o	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
integ_fail_o	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	OUTPUT
esc_req_i	Yes	Yes	T3,T12,T7	Yes	T3,T12,T7	INPUT
esc_rx_i.resp_n	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
esc_rx_i.resp_p	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
esc_tx_o.esc_n	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	OUTPUT
esc_tx_o.esc_p	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_esc_sev[1].u_esc_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
ping_ok_o	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
integ_fail_o	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	OUTPUT
esc_req_i	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
esc_rx_i.resp_n	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
esc_rx_i.resp_p	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
esc_tx_o.esc_n	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	OUTPUT
esc_tx_o.esc_p	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_esc_sev[2].u_esc_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
ping_ok_o	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
integ_fail_o	Yes	Yes	T3,T15,T11	Yes	T3,T15,T11	OUTPUT
esc_req_i	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
esc_rx_i.resp_n	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
esc_rx_i.resp_p	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
esc_tx_o.esc_n	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	OUTPUT
esc_tx_o.esc_p	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_esc_sev[3].u_esc_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
ping_ok_o	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
integ_fail_o	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	OUTPUT
esc_req_i	Yes	Yes	T3,T7,T15	Yes	T3,T7,T15	INPUT
esc_rx_i.resp_n	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
esc_rx_i.resp_p	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
esc_tx_o.esc_n	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
esc_tx_o.esc_p	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT