Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T126,T215,T216
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T12

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	16164	0	0
DisabledNoTrigBkwd_A	2147483647	793726	0	0
DisabledNoTrigFwd_A	2147483647	1450011487	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16164	0	0
T21	13376	0	0	0
T25	16104	0	0	0
T28	4701	0	0	0
T74	71064	0	0	0
T82	63647	0	0	0
T83	150822	0	0	0
T84	21139	0	0	0
T102	854360	0	0	0
T112	795015	0	0	0
T118	438617	0	0	0
T119	25284	0	0	0
T120	232770	0	0	0
T126	3524	1096	0	0
T127	10185	0	0	0
T196	0	1581	0	0
T215	1691	643	0	0
T216	0	1094	0	0
T217	0	624	0	0
T218	0	524	0	0
T219	0	509	0	0
T220	0	845	0	0
T221	0	441	0	0
T222	0	638	0	0
T223	1379	540	0	0
T224	0	507	0	0
T225	0	1895	0	0
T226	0	879	0	0
T227	0	523	0	0
T228	0	788	0	0
T229	0	662	0	0
T230	0	924	0	0
T231	0	401	0	0
T232	0	1050	0	0
T233	22872	0	0	0
T234	62450	0	0	0
T235	63765	0	0	0
T236	136914	0	0	0
T237	88985	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	793726	0	0
T1	421432	2	0	0
T2	14430	0	0	0
T3	1074368	6463	0	0
T4	2232402	928	0	0
T5	0	6722	0	0
T6	0	10	0	0
T7	1935960	4690	0	0
T11	1490452	11007	0	0
T12	1717660	294	0	0
T13	620940	2120	0	0
T14	3188480	16	0	0
T15	404392	31	0	0
T17	0	3490	0	0
T18	0	10351	0	0
T19	0	5416	0	0
T20	87608	4	0	0
T26	0	173	0	0
T30	106782	6	0	0
T46	0	3	0	0
T47	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1450011487	0	0
T1	1685728	1682826	0	0
T2	57720	29852	0	0
T3	1074368	557828	0	0
T7	1935960	1004759	0	0
T11	1490452	389646	0	0
T12	1717660	883355	0	0
T13	620940	326984	0	0
T14	3188480	1635102	0	0
T15	404392	203110	0	0
T20	87608	67488	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T215,T216,T217
1	1	Covered	T3,T7,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	670495040	3787	0	0
DisabledNoTrigBkwd_A	670495040	257850	0	0
DisabledNoTrigFwd_A	670495040	299878918	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	3787	0	0
T82	63647	0	0	0
T83	150822	0	0	0
T84	21139	0	0	0
T102	854360	0	0	0
T215	1691	643	0	0
T216	0	1094	0	0
T217	0	624	0	0
T222	0	638	0	0
T228	0	788	0	0
T233	22872	0	0	0
T234	62450	0	0	0
T235	63765	0	0	0
T236	136914	0	0	0
T237	88985	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	257850	0	0
T3	268592	12	0	0
T4	744134	799	0	0
T5	0	1474	0	0
T7	483990	1812	0	0
T11	372613	2258	0	0
T12	429415	0	0	0
T13	155235	987	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T20	21902	4	0	0
T26	0	34	0	0
T30	35594	6	0	0
T46	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	299878918	0	0
T1	421432	421427	0	0
T2	14430	14334	0	0
T3	268592	266491	0	0
T7	483990	8125	0	0
T11	372613	2639	0	0
T12	429415	429338	0	0
T13	155235	10058	0	0
T14	797120	756831	0	0
T15	101098	101089	0	0
T20	21902	1986	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T126,T220,T229
1	1	Covered	T2,T3,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T12,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	670495040	2603	0	0
DisabledNoTrigBkwd_A	670495040	190764	0	0
DisabledNoTrigFwd_A	670495040	367211712	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	2603	0	0
T21	13376	0	0	0
T25	16104	0	0	0
T28	4701	0	0	0
T74	71064	0	0	0
T112	795015	0	0	0
T118	438617	0	0	0
T119	25284	0	0	0
T120	232770	0	0	0
T126	3524	1096	0	0
T127	10185	0	0	0
T220	0	845	0	0
T229	0	662	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	190764	0	0
T3	268592	4662	0	0
T4	744134	4	0	0
T5	0	105	0	0
T7	483990	0	0	0
T11	372613	4155	0	0
T12	429415	119	0	0
T13	155235	6	0	0
T14	797120	16	0	0
T15	101098	1	0	0
T18	0	5873	0	0
T20	21902	0	0	0
T26	0	139	0	0
T30	35594	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	367211712	0	0
T1	421432	421427	0	0
T2	14430	13263	0	0
T3	268592	10100	0	0
T7	483990	483985	0	0
T11	372613	11710	0	0
T12	429415	15708	0	0
T13	155235	153989	0	0
T14	797120	38907	0	0
T15	101098	100637	0	0
T20	21902	21834	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T223,T224,T227
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T12,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	670495040	3945	0	0
DisabledNoTrigBkwd_A	670495040	172510	0	0
DisabledNoTrigFwd_A	670495040	404746209	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	3945	0	0
T61	428831	0	0	0
T223	1379	540	0	0
T224	0	507	0	0
T227	0	523	0	0
T230	0	924	0	0
T231	0	401	0	0
T232	0	1050	0	0
T238	69537	0	0	0
T239	877811	0	0	0
T240	510423	0	0	0
T241	264106	0	0	0
T242	57112	0	0	0
T243	17695	0	0	0
T244	280302	0	0	0
T245	949184	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	172510	0	0
T3	268592	3	0	0
T4	744134	7	0	0
T5	0	3843	0	0
T6	0	10	0	0
T7	483990	0	0	0
T11	372613	0	0	0
T12	429415	175	0	0
T13	155235	1121	0	0
T14	797120	0	0	0
T15	101098	7	0	0
T18	0	2443	0	0
T19	0	5416	0	0
T20	21902	0	0	0
T30	35594	0	0	0
T47	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	404746209	0	0
T1	421432	419664	0	0
T2	14430	1661	0	0
T3	268592	267389	0	0
T7	483990	483985	0	0
T11	372613	372604	0	0
T12	429415	8971	0	0
T13	155235	9846	0	0
T14	797120	797044	0	0
T15	101098	690	0	0
T20	21902	21834	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T12
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T196,T218,T219
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	670495040	5829	0	0
DisabledNoTrigBkwd_A	670495040	172602	0	0
DisabledNoTrigFwd_A	670495040	378174648	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	5829	0	0
T100	15750	0	0	0
T196	5008	1581	0	0
T197	105275	0	0	0
T198	117569	0	0	0
T217	1385	0	0	0
T218	0	524	0	0
T219	0	509	0	0
T221	0	441	0	0
T225	0	1895	0	0
T226	0	879	0	0
T246	6475	0	0	0
T247	60892	0	0	0
T248	56242	0	0	0
T249	492696	0	0	0
T250	49907	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	172602	0	0
T1	421432	2	0	0
T2	14430	0	0	0
T3	268592	1786	0	0
T4	0	118	0	0
T5	0	1300	0	0
T7	483990	2878	0	0
T11	372613	4594	0	0
T12	429415	0	0	0
T13	155235	6	0	0
T14	797120	0	0	0
T15	101098	23	0	0
T17	0	3490	0	0
T18	0	2035	0	0
T20	21902	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	378174648	0	0
T1	421432	420308	0	0
T2	14430	594	0	0
T3	268592	13848	0	0
T7	483990	28664	0	0
T11	372613	2693	0	0
T12	429415	429338	0	0
T13	155235	153091	0	0
T14	797120	42320	0	0
T15	101098	694	0	0
T20	21902	21834	0	0