Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T21,T22
1	1	1	Covered	T1,T3,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T11
1	0	1	Covered	T1,T12,T7
1	1	0	Covered	T2,T3,T11
1	1	1	Covered	T2,T3,T11

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T4,T23,T24
1	0	Covered	T18,T23,T25

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T11
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T18,T23,T25

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Not Covered
1	1	Covered	T4,T23,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T3,T13,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T3,T12,T7

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T7
1	Covered	T11,T20,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T15,T4,T26

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T12,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T12,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T12,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T7,T15

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T12
Phase1St	198	Covered	T1,T3,T12
Phase2St	215	Covered	T1,T3,T12
Phase3St	233	Covered	T1,T3,T12
TerminalSt	249	Covered	T1,T3,T12
TimeoutSt	159	Covered	T2,T3,T11

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T3,T12
IdleSt->TimeoutSt	159	Covered	T2,T3,T11
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T27,T28,T29
Phase0St->Phase1St	198	Covered	T1,T3,T12
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T30,T31,T32
Phase1St->Phase2St	215	Covered	T1,T3,T12
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T20,T33,T28
Phase2St->Phase3St	233	Covered	T1,T3,T12
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T23,T25,T34
Phase3St->TerminalSt	249	Covered	T1,T3,T12
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T14,T30,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T3,T11
TimeoutSt->Phase0St	172	Covered	T4,T18,T23

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T18,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T28,T29
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T31,T32
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T20,T33,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T25,T34
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T30,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1085	0	0
CheckAccumTrig0_A	2147483647	2281	0	0
CheckAccumTrig1_A	2147483647	104	0	0
CheckClr_A	2147483647	1076	0	0
CheckEn_A	2147483647	1108525698	0	0
CheckPhase0_A	2147483647	2602	0	0
CheckPhase1_A	2147483647	2551	0	0
CheckPhase2_A	2147483647	2496	0	0
CheckPhase3_A	2147483647	2446	0	0
CheckTimeout0_A	2147483647	3786	0	0
CheckTimeoutSt1_A	2147483647	420419	0	0
CheckTimeoutSt2_A	2147483647	3420	0	0
CheckTimeoutStTrig_A	2147483647	256	0	0
ErrorStAllEscAsserted_A	2147483647	5653	0	0
ErrorStIsTerminal_A	2147483647	4573	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1085	0	0
T8	64100	131	0	0
T9	0	249	0	0
T10	0	236	0	0
T35	0	220	0	0
T36	0	249	0	0
T37	159952	0	0	0
T38	427304	0	0	0
T39	163648	0	0	0
T40	683572	0	0	0
T41	3739360	0	0	0
T42	93764	0	0	0
T43	734880	0	0	0
T44	25256	0	0	0
T45	57724	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2281	0	0
T1	421432	1	0	0
T2	14430	0	0	0
T3	1074368	4	0	0
T4	2232402	25	0	0
T5	0	15	0	0
T6	0	1	0	0
T7	1935960	2	0	0
T11	1490452	3	0	0
T12	1717660	2	0	0
T13	620940	5	0	0
T14	3188480	4	0	0
T15	404392	3	0	0
T17	0	1	0	0
T18	0	3	0	0
T19	0	1	0	0
T20	87608	2	0	0
T26	0	2	0	0
T30	106782	4	0	0
T46	0	2	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	104	0	0
T6	341728	0	0	0
T16	496527	0	0	0
T18	324706	1	0	0
T19	227002	0	0	0
T23	1204508	3	0	0
T25	16104	2	0	0
T28	4701	0	0	0
T29	0	1	0	0
T32	0	2	0	0
T33	690022	0	0	0
T34	0	1	0	0
T39	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	4	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	11173	0	0	0
T63	242152	0	0	0
T64	428423	0	0	0
T65	983340	0	0	0
T66	438313	0	0	0
T67	106859	0	0	0
T68	413577	0	0	0
T69	238997	0	0	0
T70	312145	0	0	0
T71	13406	0	0	0
T72	170233	0	0	0
T73	18963	0	0	0
T74	71064	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1076	0	0
T4	2976536	12	0	0
T5	667844	3	0	0
T6	341728	0	0	0
T11	372613	0	0	0
T13	465705	0	0	0
T14	797120	3	0	0
T15	101098	0	0	0
T17	695385	1	0	0
T18	649412	1	0	0
T19	227002	0	0	0
T20	43804	1	0	0
T23	0	7	0	0
T24	0	1	0	0
T25	0	3	0	0
T26	984232	0	0	0
T29	0	2	0	0
T30	106782	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T46	182912	1	0	0
T47	225387	1	0	0
T66	0	2	0	0
T72	0	3	0	0
T75	17052	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1108525698	0	0
T1	1685728	1278305	0	0
T2	57720	29850	0	0
T3	1074368	39793	0	0
T7	1935960	980448	0	0
T11	1490452	389646	0	0
T12	1717660	883353	0	0
T13	620940	20312	0	0
T14	3188480	1635100	0	0
T15	404392	115777	0	0
T20	87608	67485	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2602	0	0
T1	421432	1	0	0
T2	14430	0	0	0
T3	1074368	4	0	0
T4	2232402	27	0	0
T5	0	16	0	0
T6	0	1	0	0
T7	1935960	2	0	0
T11	1490452	3	0	0
T12	1717660	2	0	0
T13	620940	5	0	0
T14	3188480	4	0	0
T15	404392	3	0	0
T17	0	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	87608	2	0	0
T26	0	2	0	0
T30	106782	4	0	0
T46	0	2	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2551	0	0
T1	421432	1	0	0
T2	14430	0	0	0
T3	1074368	4	0	0
T4	2232402	27	0	0
T5	0	16	0	0
T6	0	1	0	0
T7	1935960	2	0	0
T11	1490452	3	0	0
T12	1717660	2	0	0
T13	620940	4	0	0
T14	3188480	4	0	0
T15	404392	3	0	0
T17	0	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	87608	2	0	0
T26	0	2	0	0
T30	106782	3	0	0
T46	0	2	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2496	0	0
T1	421432	1	0	0
T2	14430	0	0	0
T3	1074368	4	0	0
T4	2232402	27	0	0
T5	0	16	0	0
T6	0	1	0	0
T7	1935960	2	0	0
T11	1490452	3	0	0
T12	1717660	2	0	0
T13	620940	4	0	0
T14	3188480	4	0	0
T15	404392	3	0	0
T17	0	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	87608	1	0	0
T26	0	2	0	0
T30	106782	3	0	0
T46	0	2	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2446	0	0
T1	421432	1	0	0
T2	14430	0	0	0
T3	1074368	4	0	0
T4	2232402	26	0	0
T5	0	16	0	0
T6	0	1	0	0
T7	1935960	2	0	0
T11	1490452	3	0	0
T12	1717660	2	0	0
T13	620940	4	0	0
T14	3188480	4	0	0
T15	404392	3	0	0
T17	0	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	87608	1	0	0
T26	0	2	0	0
T30	106782	3	0	0
T46	0	2	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3786	0	0
T2	43290	7	0	0
T3	805776	2	0	0
T4	744134	8	0	0
T5	166961	49	0	0
T7	1451970	0	0	0
T11	1117839	1	0	0
T12	1288245	0	0	0
T13	465705	0	0	0
T14	2391360	0	0	0
T15	303294	0	0	0
T17	231795	1	0	0
T18	324706	4	0	0
T19	227002	3	0	0
T20	65706	0	0	0
T23	0	12	0	0
T24	0	3	0	0
T25	0	3	0	0
T26	246058	0	0	0
T30	142376	3	0	0
T33	0	1	0	0
T46	45728	1	0	0
T47	75129	0	0	0
T66	0	16	0	0
T72	0	56	0	0
T73	0	2	0	0
T75	5684	0	0	0
T76	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	420419	0	0
T2	43290	359	0	0
T3	805776	438	0	0
T4	744134	877	0	0
T5	166961	2042	0	0
T7	1451970	0	0	0
T11	1117839	33	0	0
T12	1288245	0	0	0
T13	465705	0	0	0
T14	2391360	0	0	0
T15	303294	0	0	0
T17	231795	160	0	0
T18	324706	352	0	0
T19	227002	403	0	0
T20	65706	0	0	0
T23	0	1416	0	0
T24	0	490	0	0
T25	0	159	0	0
T26	246058	0	0	0
T30	142376	255	0	0
T33	0	26	0	0
T46	45728	270	0	0
T47	75129	0	0	0
T66	0	2405	0	0
T72	0	4781	0	0
T73	0	131	0	0
T75	5684	0	0	0
T76	0	434	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3420	0	0
T2	43290	7	0	0
T3	805776	2	0	0
T4	744134	6	0	0
T5	166961	48	0	0
T7	1451970	0	0	0
T11	1117839	1	0	0
T12	1288245	0	0	0
T13	465705	0	0	0
T14	2391360	0	0	0
T15	303294	0	0	0
T17	231795	1	0	0
T18	324706	3	0	0
T19	227002	3	0	0
T20	65706	0	0	0
T21	0	1	0	0
T23	0	7	0	0
T24	0	2	0	0
T25	0	1	0	0
T26	246058	0	0	0
T30	142376	3	0	0
T33	0	1	0	0
T46	45728	1	0	0
T47	75129	0	0	0
T66	0	15	0	0
T72	0	55	0	0
T73	0	2	0	0
T75	5684	0	0	0
T76	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	256	0	0
T4	744134	1	0	0
T5	166961	0	0	0
T6	341728	0	0	0
T17	231795	0	0	0
T18	324706	0	0	0
T19	227002	0	0	0
T23	602254	1	0	0
T24	17280	1	0	0
T26	246058	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T33	345011	0	0	0
T34	0	6	0	0
T46	45728	0	0	0
T47	75129	0	0	0
T66	438313	0	0	0
T67	106859	0	0	0
T68	413577	0	0	0
T69	238997	0	0	0
T70	312145	0	0	0
T71	13406	0	0	0
T72	170233	0	0	0
T73	18963	0	0	0
T75	5684	0	0	0
T76	0	1	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	3	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5653	0	0
T8	64100	659	0	0
T9	0	1274	0	0
T10	0	1262	0	0
T35	0	1215	0	0
T36	0	1243	0	0
T37	159952	0	0	0
T38	427304	0	0	0
T39	163648	0	0	0
T40	683572	0	0	0
T41	3739360	0	0	0
T42	93764	0	0	0
T43	734880	0	0	0
T44	25256	0	0	0
T45	57724	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4573	0	0
T8	64100	539	0	0
T9	0	1034	0	0
T10	0	1022	0	0
T35	0	975	0	0
T36	0	1003	0	0
T37	159952	0	0	0
T38	427304	0	0	0
T39	163648	0	0	0
T40	683572	0	0	0
T41	3739360	0	0	0
T42	93764	0	0	0
T43	734880	0	0	0
T44	25256	0	0	0
T45	57724	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1685728	1685708	0	0
T2	57720	57336	0	0
T3	1074368	1074336	0	0
T7	1935960	1935940	0	0
T11	1490452	1490416	0	0
T12	1717660	1717352	0	0
T13	620940	620920	0	0
T14	3188480	3188176	0	0
T15	404392	404356	0	0
T20	87608	87336	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1685728	1685708	0	0
T2	57720	57336	0	0
T3	1074368	1074336	0	0
T7	1935960	1935940	0	0
T11	1490452	1490416	0	0
T12	1717660	1717352	0	0
T13	620940	620920	0	0
T14	3188480	3188176	0	0
T15	404392	404356	0	0
T20	87608	87336	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T12,T14

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T11
1	0	1	Covered	T12,T14,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T11

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T23,T76,T81
1	0	Covered	T18,T25,T29

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T25,T29

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Not Covered
1	1	Covered	T23,T76,T81

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T14
1	Covered	T13,T4,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T13,T4
1	Covered	T3,T12,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T14
1	Covered	T11,T4,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T14
1	Covered	T26,T18,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T12,T11,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T14,T15,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T12,T15,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T15,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T12,T14
Phase1St	198	Covered	T3,T12,T14
Phase2St	215	Covered	T3,T12,T14
Phase3St	233	Covered	T3,T12,T14
TerminalSt	249	Covered	T3,T12,T14
TimeoutSt	159	Covered	T2,T3,T11

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T3,T12,T14
IdleSt->TimeoutSt	159	Covered	T2,T3,T11
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T83,T93,T94
Phase0St->Phase1St	198	Covered	T3,T12,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T55,T95
Phase1St->Phase2St	215	Covered	T3,T12,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T96,T97,T55
Phase2St->Phase3St	233	Covered	T3,T12,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T25,T80,T98
Phase3St->TerminalSt	249	Covered	T3,T12,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T14,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T3,T11
TimeoutSt->Phase0St	172	Covered	T18,T23,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T23,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T94,T40,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T12,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T12,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T55,T95
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T12,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T12,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T96,T97,T55
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T12,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T12,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T80,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T12,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T12,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T12,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	670495040	272	0	0
CheckAccumTrig0_A	670495040	479	0	0
CheckAccumTrig1_A	670495040	23	0	0
CheckClr_A	670495040	210	0	0
CheckEn_A	670206486	294646705	0	0
CheckPhase0_A	670495040	552	0	0
CheckPhase1_A	670495040	541	0	0
CheckPhase2_A	670495040	529	0	0
CheckPhase3_A	670495040	522	0	0
CheckTimeout0_A	670495040	801	0	0
CheckTimeoutSt1_A	670495040	98940	0	0
CheckTimeoutSt2_A	670495040	716	0	0
CheckTimeoutStTrig_A	670495040	60	0	0
ErrorStAllEscAsserted_A	670495040	1376	0	0
ErrorStIsTerminal_A	670495040	1106	0	0
EscStateOut_A	670205061	670136863	0	0
u_state_regs_A	670495040	670311745	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	272	0	0
T8	16025	33	0	0
T9	0	53	0	0
T10	0	71	0	0
T35	0	63	0	0
T36	0	52	0	0
T37	39988	0	0	0
T38	106826	0	0	0
T39	40912	0	0	0
T40	170893	0	0	0
T41	934840	0	0	0
T42	23441	0	0	0
T43	183720	0	0	0
T44	6314	0	0	0
T45	14431	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	479	0	0
T3	268592	1	0	0
T4	744134	4	0	0
T5	0	3	0	0
T7	483990	0	0	0
T11	372613	1	0	0
T12	429415	1	0	0
T13	155235	1	0	0
T14	797120	4	0	0
T15	101098	1	0	0
T18	0	1	0	0
T20	21902	0	0	0
T26	0	1	0	0
T30	35594	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	23	0	0
T6	341728	0	0	0
T16	496527	0	0	0
T18	324706	1	0	0
T19	227002	0	0	0
T23	602254	0	0	0
T25	0	1	0	0
T29	0	1	0	0
T33	345011	0	0	0
T39	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T56	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	11173	0	0	0
T63	242152	0	0	0
T64	428423	0	0	0
T65	983340	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	210	0	0
T4	744134	2	0	0
T5	166961	1	0	0
T11	372613	0	0	0
T13	155235	0	0	0
T14	797120	3	0	0
T15	101098	0	0	0
T18	0	1	0	0
T20	21902	0	0	0
T25	0	1	0	0
T26	246058	0	0	0
T29	0	1	0	0
T30	35594	0	0	0
T34	0	4	0	0
T46	45728	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670206486	294646705	0	0
T1	421432	421426	0	0
T2	14430	13262	0	0
T3	268592	10100	0	0
T7	483990	483985	0	0
T11	372613	11710	0	0
T12	429415	15708	0	0
T13	155235	2032	0	0
T14	797120	38907	0	0
T15	101098	13304	0	0
T20	21902	21833	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	552	0	0
T3	268592	1	0	0
T4	744134	4	0	0
T5	0	3	0	0
T7	483990	0	0	0
T11	372613	1	0	0
T12	429415	1	0	0
T13	155235	1	0	0
T14	797120	4	0	0
T15	101098	1	0	0
T18	0	2	0	0
T20	21902	0	0	0
T26	0	1	0	0
T30	35594	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	541	0	0
T3	268592	1	0	0
T4	744134	4	0	0
T5	0	3	0	0
T7	483990	0	0	0
T11	372613	1	0	0
T12	429415	1	0	0
T13	155235	1	0	0
T14	797120	4	0	0
T15	101098	1	0	0
T18	0	2	0	0
T20	21902	0	0	0
T26	0	1	0	0
T30	35594	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	529	0	0
T3	268592	1	0	0
T4	744134	4	0	0
T5	0	3	0	0
T7	483990	0	0	0
T11	372613	1	0	0
T12	429415	1	0	0
T13	155235	1	0	0
T14	797120	4	0	0
T15	101098	1	0	0
T18	0	2	0	0
T20	21902	0	0	0
T26	0	1	0	0
T30	35594	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	522	0	0
T3	268592	1	0	0
T4	744134	4	0	0
T5	0	3	0	0
T7	483990	0	0	0
T11	372613	1	0	0
T12	429415	1	0	0
T13	155235	1	0	0
T14	797120	4	0	0
T15	101098	1	0	0
T18	0	2	0	0
T20	21902	0	0	0
T26	0	1	0	0
T30	35594	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	801	0	0
T2	14430	1	0	0
T3	268592	1	0	0
T5	0	43	0	0
T7	483990	0	0	0
T11	372613	1	0	0
T12	429415	0	0	0
T13	155235	0	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T18	0	3	0	0
T20	21902	0	0	0
T23	0	3	0	0
T25	0	2	0	0
T30	35594	0	0	0
T66	0	7	0	0
T72	0	15	0	0
T73	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	98940	0	0
T2	14430	56	0	0
T3	268592	221	0	0
T5	0	1720	0	0
T7	483990	0	0	0
T11	372613	33	0	0
T12	429415	0	0	0
T13	155235	0	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T18	0	240	0	0
T20	21902	0	0	0
T23	0	422	0	0
T25	0	158	0	0
T30	35594	0	0	0
T66	0	1089	0	0
T72	0	1289	0	0
T73	0	68	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	716	0	0
T2	14430	1	0	0
T3	268592	1	0	0
T5	0	43	0	0
T7	483990	0	0	0
T11	372613	1	0	0
T12	429415	0	0	0
T13	155235	0	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T18	0	2	0	0
T20	21902	0	0	0
T23	0	2	0	0
T25	0	1	0	0
T30	35594	0	0	0
T66	0	7	0	0
T72	0	15	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	60	0	0
T23	602254	1	0	0
T33	345011	0	0	0
T66	438313	0	0	0
T67	106859	0	0	0
T68	413577	0	0	0
T69	238997	0	0	0
T70	312145	0	0	0
T71	13406	0	0	0
T72	170233	0	0	0
T73	18963	0	0	0
T76	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T85	0	2	0	0
T86	0	1	0	0
T87	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	1376	0	0
T8	16025	152	0	0
T9	0	293	0	0
T10	0	326	0	0
T35	0	292	0	0
T36	0	313	0	0
T37	39988	0	0	0
T38	106826	0	0	0
T39	40912	0	0	0
T40	170893	0	0	0
T41	934840	0	0	0
T42	23441	0	0	0
T43	183720	0	0	0
T44	6314	0	0	0
T45	14431	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	1106	0	0
T8	16025	122	0	0
T9	0	233	0	0
T10	0	266	0	0
T35	0	232	0	0
T36	0	253	0	0
T37	39988	0	0	0
T38	106826	0	0	0
T39	40912	0	0	0
T40	170893	0	0	0
T41	934840	0	0	0
T42	23441	0	0	0
T43	183720	0	0	0
T44	6314	0	0	0
T45	14431	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670205061	670136863	0	0
T1	421432	421427	0	0
T2	14430	14334	0	0
T3	268592	268584	0	0
T7	483990	483985	0	0
T11	372613	372604	0	0
T12	429415	429338	0	0
T13	155235	155230	0	0
T14	797120	797044	0	0
T15	101098	101089	0	0
T20	21902	21834	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	670311745	0	0
T1	421432	421427	0	0
T2	14430	14334	0	0
T3	268592	268584	0	0
T7	483990	483985	0	0
T11	372613	372604	0	0
T12	429415	429338	0	0
T13	155235	155230	0	0
T14	797120	797044	0	0
T15	101098	101089	0	0
T20	21902	21834	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T11
1	0	1	Covered	T1,T7,T13
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T2,T3,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T5,T23,T66
1	0	Covered	T4,T34,T80

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T34,T80

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T5,T23,T66

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T13
1	Covered	T3,T7,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T13,T72,T28

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T15
1	Covered	T1,T11,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T4,T18,T63

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T15,T11,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T7,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T7
Phase1St	198	Covered	T1,T3,T7
Phase2St	215	Covered	T1,T3,T7
Phase3St	233	Covered	T1,T3,T7
TerminalSt	249	Covered	T1,T3,T7
TimeoutSt	159	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T3,T7
IdleSt->TimeoutSt	159	Covered	T2,T3,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T83,T100
Phase0St->Phase1St	198	Covered	T1,T3,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T13,T70,T80
Phase1St->Phase2St	215	Covered	T1,T3,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T25,T21,T80
Phase2St->Phase3St	233	Covered	T1,T3,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T4,T80,T95
Phase3St->TerminalSt	249	Covered	T1,T3,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T65
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T3,T4
TimeoutSt->Phase0St	172	Covered	T4,T5,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T100,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T13,T70,T80
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T7,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T25,T21,T80
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T80,T95
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	670495040	295	0	0
CheckAccumTrig0_A	670495040	477	0	0
CheckAccumTrig1_A	670495040	25	0	0
CheckClr_A	670495040	227	0	0
CheckEn_A	670206486	297569024	0	0
CheckPhase0_A	670495040	562	0	0
CheckPhase1_A	670495040	551	0	0
CheckPhase2_A	670495040	541	0	0
CheckPhase3_A	670495040	528	0	0
CheckTimeout0_A	670495040	768	0	0
CheckTimeoutSt1_A	670495040	77791	0	0
CheckTimeoutSt2_A	670495040	673	0	0
CheckTimeoutStTrig_A	670495040	69	0	0
ErrorStAllEscAsserted_A	670495040	1449	0	0
ErrorStIsTerminal_A	670495040	1179	0	0
EscStateOut_A	670205061	670136863	0	0
u_state_regs_A	670495040	670311745	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	295	0	0
T8	16025	33	0	0
T9	0	71	0	0
T10	0	60	0	0
T35	0	57	0	0
T36	0	74	0	0
T37	39988	0	0	0
T38	106826	0	0	0
T39	40912	0	0	0
T40	170893	0	0	0
T41	934840	0	0	0
T42	23441	0	0	0
T43	183720	0	0	0
T44	6314	0	0	0
T45	14431	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	477	0	0
T1	421432	1	0	0
T2	14430	0	0	0
T3	268592	1	0	0
T4	0	6	0	0
T5	0	3	0	0
T7	483990	1	0	0
T11	372613	1	0	0
T12	429415	0	0	0
T13	155235	2	0	0
T14	797120	0	0	0
T15	101098	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	21902	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	25	0	0
T4	744134	1	0	0
T5	166961	0	0	0
T6	341728	0	0	0
T17	231795	0	0	0
T18	324706	0	0	0
T19	227002	0	0	0
T26	246058	0	0	0
T32	0	1	0	0
T34	0	6	0	0
T39	0	1	0	0
T46	45728	0	0	0
T47	75129	0	0	0
T54	0	1	0	0
T75	5684	0	0	0
T80	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	227	0	0
T4	744134	5	0	0
T5	166961	1	0	0
T13	155235	1	0	0
T17	231795	0	0	0
T18	324706	0	0	0
T23	0	1	0	0
T25	0	2	0	0
T26	246058	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T30	35594	0	0	0
T46	45728	0	0	0
T47	75129	0	0	0
T70	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T75	5684	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670206486	297569024	0	0
T1	421432	15789	0	0
T2	14430	594	0	0
T3	268592	6799	0	0
T7	483990	9344	0	0
T11	372613	2693	0	0
T12	429415	429337	0	0
T13	155235	2055	0	0
T14	797120	42320	0	0
T15	101098	694	0	0
T20	21902	21833	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	562	0	0
T1	421432	1	0	0
T2	14430	0	0	0
T3	268592	1	0	0
T4	0	7	0	0
T5	0	4	0	0
T7	483990	1	0	0
T11	372613	1	0	0
T12	429415	0	0	0
T13	155235	2	0	0
T14	797120	0	0	0
T15	101098	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	21902	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	551	0	0
T1	421432	1	0	0
T2	14430	0	0	0
T3	268592	1	0	0
T4	0	7	0	0
T5	0	4	0	0
T7	483990	1	0	0
T11	372613	1	0	0
T12	429415	0	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	21902	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	541	0	0
T1	421432	1	0	0
T2	14430	0	0	0
T3	268592	1	0	0
T4	0	7	0	0
T5	0	4	0	0
T7	483990	1	0	0
T11	372613	1	0	0
T12	429415	0	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	21902	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	528	0	0
T1	421432	1	0	0
T2	14430	0	0	0
T3	268592	1	0	0
T4	0	6	0	0
T5	0	4	0	0
T7	483990	1	0	0
T11	372613	1	0	0
T12	429415	0	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	21902	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	768	0	0
T2	14430	4	0	0
T3	268592	1	0	0
T4	0	3	0	0
T5	0	4	0	0
T7	483990	0	0	0
T11	372613	0	0	0
T12	429415	0	0	0
T13	155235	0	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T20	21902	0	0	0
T23	0	3	0	0
T24	0	1	0	0
T30	35594	0	0	0
T66	0	3	0	0
T72	0	14	0	0
T73	0	1	0	0
T76	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	77791	0	0
T2	14430	197	0	0
T3	268592	217	0	0
T4	0	281	0	0
T5	0	221	0	0
T7	483990	0	0	0
T11	372613	0	0	0
T12	429415	0	0	0
T13	155235	0	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T20	21902	0	0	0
T23	0	504	0	0
T24	0	309	0	0
T30	35594	0	0	0
T66	0	475	0	0
T72	0	1040	0	0
T73	0	63	0	0
T76	0	434	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	673	0	0
T2	14430	4	0	0
T3	268592	1	0	0
T4	0	2	0	0
T5	0	3	0	0
T7	483990	0	0	0
T11	372613	0	0	0
T12	429415	0	0	0
T13	155235	0	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T20	21902	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T30	35594	0	0	0
T66	0	2	0	0
T72	0	13	0	0
T73	0	1	0	0
T76	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	69	0	0
T5	166961	1	0	0
T6	341728	0	0	0
T16	496527	0	0	0
T17	231795	0	0	0
T18	324706	0	0	0
T19	227002	0	0	0
T23	0	1	0	0
T34	0	2	0	0
T46	45728	0	0	0
T47	75129	0	0	0
T62	11173	0	0	0
T66	0	1	0	0
T72	0	1	0	0
T75	5684	0	0	0
T79	0	1	0	0
T80	0	5	0	0
T83	0	3	0	0
T106	0	1	0	0
T107	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	1449	0	0
T8	16025	191	0	0
T9	0	323	0	0
T10	0	298	0	0
T35	0	315	0	0
T36	0	322	0	0
T37	39988	0	0	0
T38	106826	0	0	0
T39	40912	0	0	0
T40	170893	0	0	0
T41	934840	0	0	0
T42	23441	0	0	0
T43	183720	0	0	0
T44	6314	0	0	0
T45	14431	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	1179	0	0
T8	16025	161	0	0
T9	0	263	0	0
T10	0	238	0	0
T35	0	255	0	0
T36	0	262	0	0
T37	39988	0	0	0
T38	106826	0	0	0
T39	40912	0	0	0
T40	170893	0	0	0
T41	934840	0	0	0
T42	23441	0	0	0
T43	183720	0	0	0
T44	6314	0	0	0
T45	14431	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670205061	670136863	0	0
T1	421432	421427	0	0
T2	14430	14334	0	0
T3	268592	268584	0	0
T7	483990	483985	0	0
T11	372613	372604	0	0
T12	429415	429338	0	0
T13	155235	155230	0	0
T14	797120	797044	0	0
T15	101098	101089	0	0
T20	21902	21834	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	670311745	0	0
T1	421432	421427	0	0
T2	14430	14334	0	0
T3	268592	268584	0	0
T7	483990	483985	0	0
T11	372613	372604	0	0
T12	429415	429338	0	0
T13	155235	155230	0	0
T14	797120	797044	0	0
T15	101098	101089	0	0
T20	21902	21834	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T7,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T7,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T22
1	1	1	Covered	T3,T7,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T11,T20
1	0	1	Covered	T13,T4,T26
1	1	0	Covered	T2,T5,T17
1	1	1	Covered	T30,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T4,T5
0	1	Covered	T4,T34,T80
1	0	Covered	T23,T34,T48

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T30,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T34,T48

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T30,T4,T5
1	0	Not Covered
1	1	Covered	T4,T34,T80

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T11
1	Covered	T4,T5,T75

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T20,T13
1	Covered	T3,T7,T30

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T30
1	Covered	T11,T20,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T11
1	Covered	T4,T46,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T7,T20,T30

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T7,T11,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T20,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T7,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T7,T11
Phase1St	198	Covered	T3,T7,T11
Phase2St	215	Covered	T3,T7,T11
Phase3St	233	Covered	T3,T7,T11
TerminalSt	249	Covered	T3,T7,T11
TimeoutSt	159	Covered	T30,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T3,T7,T11
IdleSt->TimeoutSt	159	Covered	T30,T4,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T29,T83
Phase0St->Phase1St	198	Covered	T3,T7,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T32,T108
Phase1St->Phase2St	215	Covered	T3,T7,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T20,T33,T28
Phase2St->Phase3St	233	Covered	T3,T7,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T23,T34,T50
Phase3St->TerminalSt	249	Covered	T3,T7,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T30,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T30,T4,T5
TimeoutSt->Phase0St	172	Covered	T4,T23,T34

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T30,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T23,T34
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T30,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T30,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T29,T87
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T7,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T7,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T32,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T7,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T7,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T20,T33,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T7,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T7,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T34,T50
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T7,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T7,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T30,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T7,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	670495040	290	0	0
CheckAccumTrig0_A	670495040	843	0	0
CheckAccumTrig1_A	670495040	38	0	0
CheckClr_A	670495040	408	0	0
CheckEn_A	670206486	206659571	0	0
CheckPhase0_A	670495040	933	0	0
CheckPhase1_A	670495040	912	0	0
CheckPhase2_A	670495040	895	0	0
CheckPhase3_A	670495040	876	0	0
CheckTimeout0_A	670495040	918	0	0
CheckTimeoutSt1_A	670495040	102527	0	0
CheckTimeoutSt2_A	670495040	815	0	0
CheckTimeoutStTrig_A	670495040	65	0	0
ErrorStAllEscAsserted_A	670495040	1398	0	0
ErrorStIsTerminal_A	670495040	1128	0	0
EscStateOut_A	670205061	670136863	0	0
u_state_regs_A	670495040	670311745	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	290	0	0
T8	16025	36	0	0
T9	0	80	0	0
T10	0	63	0	0
T35	0	52	0	0
T36	0	59	0	0
T37	39988	0	0	0
T38	106826	0	0	0
T39	40912	0	0	0
T40	170893	0	0	0
T41	934840	0	0	0
T42	23441	0	0	0
T43	183720	0	0	0
T44	6314	0	0	0
T45	14431	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	843	0	0
T3	268592	1	0	0
T4	744134	12	0	0
T5	0	6	0	0
T7	483990	1	0	0
T11	372613	1	0	0
T12	429415	0	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T20	21902	2	0	0
T26	0	1	0	0
T30	35594	4	0	0
T46	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	38	0	0
T23	602254	3	0	0
T32	0	1	0	0
T33	345011	0	0	0
T34	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T66	438313	0	0	0
T67	106859	0	0	0
T68	413577	0	0	0
T69	238997	0	0	0
T70	312145	0	0	0
T71	13406	0	0	0
T72	170233	0	0	0
T73	18963	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	408	0	0
T4	744134	8	0	0
T5	166961	2	0	0
T13	155235	0	0	0
T17	231795	1	0	0
T20	21902	1	0	0
T23	0	7	0	0
T26	246058	0	0	0
T30	35594	3	0	0
T33	0	1	0	0
T46	45728	1	0	0
T47	75129	0	0	0
T66	0	2	0	0
T75	5684	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670206486	206659571	0	0
T1	421432	421426	0	0
T2	14430	14333	0	0
T3	268592	13767	0	0
T7	483990	3134	0	0
T11	372613	2639	0	0
T12	429415	429337	0	0
T13	155235	6379	0	0
T14	797120	756830	0	0
T15	101098	101089	0	0
T20	21902	1986	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	933	0	0
T3	268592	1	0	0
T4	744134	13	0	0
T5	0	6	0	0
T7	483990	1	0	0
T11	372613	1	0	0
T12	429415	0	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T20	21902	2	0	0
T26	0	1	0	0
T30	35594	4	0	0
T46	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	912	0	0
T3	268592	1	0	0
T4	744134	13	0	0
T5	0	6	0	0
T7	483990	1	0	0
T11	372613	1	0	0
T12	429415	0	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T20	21902	2	0	0
T26	0	1	0	0
T30	35594	3	0	0
T46	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	895	0	0
T3	268592	1	0	0
T4	744134	13	0	0
T5	0	6	0	0
T7	483990	1	0	0
T11	372613	1	0	0
T12	429415	0	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T20	21902	1	0	0
T26	0	1	0	0
T30	35594	3	0	0
T46	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	876	0	0
T3	268592	1	0	0
T4	744134	13	0	0
T5	0	6	0	0
T7	483990	1	0	0
T11	372613	1	0	0
T12	429415	0	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T20	21902	1	0	0
T26	0	1	0	0
T30	35594	3	0	0
T46	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	918	0	0
T4	744134	4	0	0
T5	166961	1	0	0
T17	231795	0	0	0
T18	324706	0	0	0
T19	227002	3	0	0
T23	0	4	0	0
T24	0	1	0	0
T26	246058	0	0	0
T30	35594	3	0	0
T33	0	1	0	0
T46	45728	1	0	0
T47	75129	0	0	0
T66	0	1	0	0
T72	0	19	0	0
T75	5684	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	102527	0	0
T4	744134	446	0	0
T5	166961	57	0	0
T17	231795	0	0	0
T18	324706	0	0	0
T19	227002	403	0	0
T23	0	264	0	0
T24	0	120	0	0
T26	246058	0	0	0
T30	35594	255	0	0
T33	0	26	0	0
T46	45728	270	0	0
T47	75129	0	0	0
T66	0	33	0	0
T72	0	1802	0	0
T75	5684	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	815	0	0
T4	744134	3	0	0
T5	166961	1	0	0
T17	231795	0	0	0
T18	324706	0	0	0
T19	227002	3	0	0
T23	0	1	0	0
T24	0	1	0	0
T26	246058	0	0	0
T30	35594	3	0	0
T33	0	1	0	0
T46	45728	1	0	0
T47	75129	0	0	0
T66	0	1	0	0
T72	0	19	0	0
T75	5684	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	65	0	0
T4	744134	1	0	0
T5	166961	0	0	0
T6	341728	0	0	0
T17	231795	0	0	0
T18	324706	0	0	0
T19	227002	0	0	0
T26	246058	0	0	0
T34	0	4	0	0
T46	45728	0	0	0
T47	75129	0	0	0
T75	5684	0	0	0
T80	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T89	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	1398	0	0
T8	16025	169	0	0
T9	0	330	0	0
T10	0	307	0	0
T35	0	296	0	0
T36	0	296	0	0
T37	39988	0	0	0
T38	106826	0	0	0
T39	40912	0	0	0
T40	170893	0	0	0
T41	934840	0	0	0
T42	23441	0	0	0
T43	183720	0	0	0
T44	6314	0	0	0
T45	14431	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	1128	0	0
T8	16025	139	0	0
T9	0	270	0	0
T10	0	247	0	0
T35	0	236	0	0
T36	0	236	0	0
T37	39988	0	0	0
T38	106826	0	0	0
T39	40912	0	0	0
T40	170893	0	0	0
T41	934840	0	0	0
T42	23441	0	0	0
T43	183720	0	0	0
T44	6314	0	0	0
T45	14431	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670205061	670136863	0	0
T1	421432	421427	0	0
T2	14430	14334	0	0
T3	268592	268584	0	0
T7	483990	483985	0	0
T11	372613	372604	0	0
T12	429415	429338	0	0
T13	155235	155230	0	0
T14	797120	797044	0	0
T15	101098	101089	0	0
T20	21902	21834	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	670311745	0	0
T1	421432	421427	0	0
T2	14430	14334	0	0
T3	268592	268584	0	0
T7	483990	483985	0	0
T11	372613	372604	0	0
T12	429415	429338	0	0
T13	155235	155230	0	0
T14	797120	797044	0	0
T15	101098	101089	0	0
T20	21902	21834	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T21
1	1	1	Covered	T3,T12,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T30
1	0	1	Covered	T1,T12,T26
1	1	0	Covered	T3,T11,T4
1	1	1	Covered	T2,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T24,T29,T34
1	0	Covered	T25,T21,T32

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T21,T32

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T24,T29,T34

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T15,T13
1	Covered	T3,T4,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T4
1	Covered	T12,T13,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T15
1	Covered	T4,T16,T63

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T13
1	Covered	T15,T5,T47

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T15,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T15,T13,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T12,T15
Phase1St	198	Covered	T3,T12,T15
Phase2St	215	Covered	T3,T12,T15
Phase3St	233	Covered	T3,T12,T15
TerminalSt	249	Covered	T3,T12,T15
TimeoutSt	159	Covered	T2,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T3,T12,T15
IdleSt->TimeoutSt	159	Covered	T2,T4,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T93,T109,T104
Phase0St->Phase1St	198	Covered	T3,T12,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T39,T110,T111
Phase1St->Phase2St	215	Covered	T3,T12,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T112,T113,T54
Phase2St->Phase3St	233	Covered	T3,T12,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T25,T54,T114
Phase3St->TerminalSt	249	Covered	T3,T12,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T47
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T5
TimeoutSt->Phase0St	172	Covered	T24,T25,T29

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T109,T104,T22
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T12,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T12,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T39,T110,T111
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T12,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T12,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T112,T113,T54
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T12,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T12,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T54,T114
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T12,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T12,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T47,T72
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T12,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	670495040	228	0	0
CheckAccumTrig0_A	670495040	482	0	0
CheckAccumTrig1_A	670495040	18	0	0
CheckClr_A	670495040	231	0	0
CheckEn_A	670206486	309650398	0	0
CheckPhase0_A	670495040	555	0	0
CheckPhase1_A	670495040	547	0	0
CheckPhase2_A	670495040	531	0	0
CheckPhase3_A	670495040	520	0	0
CheckTimeout0_A	670495040	1299	0	0
CheckTimeoutSt1_A	670495040	141161	0	0
CheckTimeoutSt2_A	670495040	1216	0	0
CheckTimeoutStTrig_A	670495040	62	0	0
ErrorStAllEscAsserted_A	670495040	1430	0	0
ErrorStIsTerminal_A	670495040	1160	0	0
EscStateOut_A	670205061	670136863	0	0
u_state_regs_A	670495040	670311745	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	228	0	0
T8	16025	29	0	0
T9	0	45	0	0
T10	0	42	0	0
T35	0	48	0	0
T36	0	64	0	0
T37	39988	0	0	0
T38	106826	0	0	0
T39	40912	0	0	0
T40	170893	0	0	0
T41	934840	0	0	0
T42	23441	0	0	0
T43	183720	0	0	0
T44	6314	0	0	0
T45	14431	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	482	0	0
T3	268592	1	0	0
T4	744134	3	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	483990	0	0	0
T11	372613	0	0	0
T12	429415	1	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	21902	0	0	0
T30	35594	0	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	18	0	0
T21	13376	0	0	0
T25	16104	1	0	0
T28	4701	0	0	0
T32	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T58	0	1	0	0
T74	71064	0	0	0
T76	31501	0	0	0
T105	0	1	0	0
T112	795015	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	438617	0	0	0
T119	25284	0	0	0
T120	232770	0	0	0
T121	124319	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	231	0	0
T4	744134	2	0	0
T5	166961	0	0	0
T6	341728	0	0	0
T17	231795	0	0	0
T18	324706	0	0	0
T19	227002	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T26	246058	0	0	0
T29	0	1	0	0
T34	0	1	0	0
T46	45728	0	0	0
T47	75129	1	0	0
T72	0	3	0	0
T75	5684	0	0	0
T77	0	1	0	0
T112	0	7	0	0
T122	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670206486	309650398	0	0
T1	421432	419664	0	0
T2	14430	1661	0	0
T3	268592	9127	0	0
T7	483990	483985	0	0
T11	372613	372604	0	0
T12	429415	8971	0	0
T13	155235	9846	0	0
T14	797120	797043	0	0
T15	101098	690	0	0
T20	21902	21833	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	555	0	0
T3	268592	1	0	0
T4	744134	3	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	483990	0	0	0
T11	372613	0	0	0
T12	429415	1	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	21902	0	0	0
T30	35594	0	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	547	0	0
T3	268592	1	0	0
T4	744134	3	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	483990	0	0	0
T11	372613	0	0	0
T12	429415	1	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	21902	0	0	0
T30	35594	0	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	531	0	0
T3	268592	1	0	0
T4	744134	3	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	483990	0	0	0
T11	372613	0	0	0
T12	429415	1	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	21902	0	0	0
T30	35594	0	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	520	0	0
T3	268592	1	0	0
T4	744134	3	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	483990	0	0	0
T11	372613	0	0	0
T12	429415	1	0	0
T13	155235	1	0	0
T14	797120	0	0	0
T15	101098	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	21902	0	0	0
T30	35594	0	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	1299	0	0
T2	14430	2	0	0
T3	268592	0	0	0
T4	0	1	0	0
T5	0	1	0	0
T7	483990	0	0	0
T11	372613	0	0	0
T12	429415	0	0	0
T13	155235	0	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	21902	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T25	0	1	0	0
T30	35594	0	0	0
T66	0	5	0	0
T72	0	8	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	141161	0	0
T2	14430	106	0	0
T3	268592	0	0	0
T4	0	150	0	0
T5	0	44	0	0
T7	483990	0	0	0
T11	372613	0	0	0
T12	429415	0	0	0
T13	155235	0	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T17	0	160	0	0
T18	0	112	0	0
T20	21902	0	0	0
T23	0	226	0	0
T24	0	61	0	0
T25	0	1	0	0
T30	35594	0	0	0
T66	0	808	0	0
T72	0	650	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	1216	0	0
T2	14430	2	0	0
T3	268592	0	0	0
T4	0	1	0	0
T5	0	1	0	0
T7	483990	0	0	0
T11	372613	0	0	0
T12	429415	0	0	0
T13	155235	0	0	0
T14	797120	0	0	0
T15	101098	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	21902	0	0	0
T21	0	1	0	0
T23	0	2	0	0
T30	35594	0	0	0
T66	0	5	0	0
T72	0	8	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	62	0	0
T21	13376	0	0	0
T24	17280	1	0	0
T25	16104	0	0	0
T28	4701	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T52	0	1	0	0
T74	71064	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T82	0	1	0	0
T88	0	1	0	0
T92	0	1	0	0
T123	131187	0	0	0
T124	115629	0	0	0
T125	122735	0	0	0
T126	3524	0	0	0
T127	10185	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	1430	0	0
T8	16025	147	0	0
T9	0	328	0	0
T10	0	331	0	0
T35	0	312	0	0
T36	0	312	0	0
T37	39988	0	0	0
T38	106826	0	0	0
T39	40912	0	0	0
T40	170893	0	0	0
T41	934840	0	0	0
T42	23441	0	0	0
T43	183720	0	0	0
T44	6314	0	0	0
T45	14431	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	1160	0	0
T8	16025	117	0	0
T9	0	268	0	0
T10	0	271	0	0
T35	0	252	0	0
T36	0	252	0	0
T37	39988	0	0	0
T38	106826	0	0	0
T39	40912	0	0	0
T40	170893	0	0	0
T41	934840	0	0	0
T42	23441	0	0	0
T43	183720	0	0	0
T44	6314	0	0	0
T45	14431	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670205061	670136863	0	0
T1	421432	421427	0	0
T2	14430	14334	0	0
T3	268592	268584	0	0
T7	483990	483985	0	0
T11	372613	372604	0	0
T12	429415	429338	0	0
T13	155235	155230	0	0
T14	797120	797044	0	0
T15	101098	101089	0	0
T20	21902	21834	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670495040	670311745	0	0
T1	421432	421427	0	0
T2	14430	14334	0	0
T3	268592	268584	0	0
T7	483990	483985	0	0
T11	372613	372604	0	0
T12	429415	429338	0	0
T13	155235	155230	0	0
T14	797120	797044	0	0
T15	101098	101089	0	0
T20	21902	21834	0	0