Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65035652	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31454689

1

T1

103201

T2

106062

T3

80237

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14525393	1			T1	40639		T2	41173		T3	31124
values[0x0]	40002391	1			T1	143204		T2	146098		T3	110853
values[0x1]	41962557	1			T1	144024		T2	146398		T3	110891

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55588745	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40901596

1

T1

130727

T2

134024

T3

101044

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	317320	1			T1	1295		T2	1306		T3	878
valid_sources[0x01]	330864	1			T1	1280		T2	1289		T3	1191
valid_sources[0x02]	318891	1			T1	1261		T2	1359		T3	1012
valid_sources[0x03]	323079	1			T1	1301		T2	1284		T3	809
valid_sources[0x04]	314400	1			T1	1259		T2	1309		T3	763
valid_sources[0x05]	332247	1			T1	1307		T2	1241		T3	1019
valid_sources[0x06]	328853	1			T1	1277		T2	1387		T3	1032
valid_sources[0x07]	324677	1			T1	1245		T2	1444		T3	917
valid_sources[0x08]	326344	1			T1	1292		T2	1304		T3	666
valid_sources[0x09]	329477	1			T1	1246		T2	1258		T3	964
valid_sources[0x0a]	319590	1			T1	1244		T2	1223		T3	877
valid_sources[0x0b]	325917	1			T1	1327		T2	1194		T3	972
valid_sources[0x0c]	321828	1			T1	1242		T2	1311		T3	798
valid_sources[0x0d]	327585	1			T1	1266		T2	1290		T3	1222
valid_sources[0x0e]	332676	1			T1	1263		T2	1410		T3	1024
valid_sources[0x0f]	314916	1			T1	1227		T2	1327		T3	921
valid_sources[0x10]	324972	1			T1	1268		T2	1355		T3	1162
valid_sources[0x11]	319522	1			T1	1341		T2	1322		T3	876
valid_sources[0x12]	313806	1			T1	1301		T2	1473		T3	1115
valid_sources[0x13]	326453	1			T1	1309		T2	1319		T3	1060
valid_sources[0x14]	320337	1			T1	1323		T2	1278		T3	958
valid_sources[0x15]	325219	1			T1	1296		T2	1298		T3	969
valid_sources[0x16]	325877	1			T1	1271		T2	1340		T3	1008
valid_sources[0x17]	313623	1			T1	1264		T2	1390		T3	1159
valid_sources[0x18]	328053	1			T1	1290		T2	1306		T3	1171
valid_sources[0x19]	332018	1			T1	1265		T2	1335		T3	1118
valid_sources[0x1a]	324681	1			T1	1276		T2	1327		T3	1103
valid_sources[0x1b]	322315	1			T1	1267		T2	1336		T3	1032
valid_sources[0x1c]	327537	1			T1	1299		T2	1293		T3	789
valid_sources[0x1d]	314915	1			T1	1363		T2	1263		T3	1085
valid_sources[0x1e]	324424	1			T1	1336		T2	1262		T3	924
valid_sources[0x1f]	315760	1			T1	1312		T2	1340		T3	984
valid_sources[0x20]	317376	1			T1	1330		T2	1368		T3	1041
valid_sources[0x21]	311580	1			T1	1272		T2	1255		T3	874
valid_sources[0x22]	319616	1			T1	1327		T2	1286		T3	880
valid_sources[0x23]	319667	1			T1	1341		T2	1313		T3	1050
valid_sources[0x24]	328708	1			T1	1250		T2	1292		T3	998
valid_sources[0x25]	320211	1			T1	1233		T2	1351		T3	978
valid_sources[0x26]	314276	1			T1	1278		T2	1306		T3	1056
valid_sources[0x27]	321950	1			T1	1213		T2	1252		T3	917
valid_sources[0x28]	314688	1			T1	1356		T2	1442		T3	1119
valid_sources[0x29]	322490	1			T1	1281		T2	1351		T3	1085
valid_sources[0x2a]	322371	1			T1	1307		T2	1330		T3	917
valid_sources[0x2b]	588549	1			T1	1152		T2	1332		T3	1109
valid_sources[0x2c]	333605	1			T1	1250		T2	1383		T3	1187
valid_sources[0x2d]	705986	1			T1	1270		T2	1242		T3	853
valid_sources[0x2e]	320732	1			T1	1333		T2	1364		T3	760
valid_sources[0x2f]	314382	1			T1	1286		T2	1348		T3	1175
valid_sources[0x30]	354325	1			T1	1302		T2	1204		T3	1106
valid_sources[0x31]	324022	1			T1	1238		T2	1292		T3	1010
valid_sources[0x32]	327104	1			T1	1289		T2	1273		T3	1070
valid_sources[0x33]	319414	1			T1	1231		T2	1277		T3	1202
valid_sources[0x34]	319333	1			T1	1209		T2	1353		T3	1076
valid_sources[0x35]	349559	1			T1	1323		T2	1392		T3	942
valid_sources[0x36]	325834	1			T1	1265		T2	1302		T3	893
valid_sources[0x37]	328187	1			T1	1319		T2	1344		T3	973
valid_sources[0x38]	597900	1			T1	1272		T2	1331		T3	850
valid_sources[0x39]	315332	1			T1	1369		T2	1258		T3	1293
valid_sources[0x3a]	331332	1			T1	1299		T2	1354		T3	880
valid_sources[0x3b]	323980	1			T1	1303		T2	1221		T3	957
valid_sources[0x3c]	319772	1			T1	1328		T2	1316		T3	1137
valid_sources[0x3d]	359500	1			T1	1374		T2	1226		T3	1012
valid_sources[0x3e]	326910	1			T1	1384		T2	1256		T3	793
valid_sources[0x3f]	320663	1			T1	1292		T2	1369		T3	1000
valid_sources[0x40]	624758	1			T1	1333		T2	1306		T3	987
valid_sources[0x41]	332789	1			T1	1202		T2	1338		T3	1097
valid_sources[0x42]	898356	1			T1	1351		T2	1401		T3	798
valid_sources[0x43]	330988	1			T1	1274		T2	1265		T3	1311
valid_sources[0x44]	329036	1			T1	1368		T2	1314		T3	807
valid_sources[0x45]	319473	1			T1	1210		T2	1351		T3	923
valid_sources[0x46]	318274	1			T1	1295		T2	1337		T3	1050
valid_sources[0x47]	322481	1			T1	1296		T2	1268		T3	914
valid_sources[0x48]	317968	1			T1	1265		T2	1225		T3	1184
valid_sources[0x49]	321853	1			T1	1260		T2	1258		T3	1010
valid_sources[0x4a]	322380	1			T1	1273		T2	1313		T3	859
valid_sources[0x4b]	319145	1			T1	1299		T2	1237		T3	775
valid_sources[0x4c]	322080	1			T1	1326		T2	1296		T3	920
valid_sources[0x4d]	308986	1			T1	1238		T2	1158		T3	1048
valid_sources[0x4e]	322685	1			T1	1451		T2	1338		T3	948
valid_sources[0x4f]	312887	1			T1	1243		T2	1331		T3	951
valid_sources[0x50]	313109	1			T1	1309		T2	1177		T3	825
valid_sources[0x51]	322346	1			T1	1375		T2	1302		T3	979
valid_sources[0x52]	560204	1			T1	1242		T2	1239		T3	937
valid_sources[0x53]	321560	1			T1	1301		T2	1266		T3	1178
valid_sources[0x54]	312912	1			T1	1281		T2	1329		T3	1075
valid_sources[0x55]	319698	1			T1	1268		T2	1289		T3	1209
valid_sources[0x56]	318847	1			T1	1252		T2	1254		T3	922
valid_sources[0x57]	316646	1			T1	1287		T2	1251		T3	1092
valid_sources[0x58]	749896	1			T1	1239		T2	1337		T3	826
valid_sources[0x59]	319502	1			T1	1302		T2	1331		T3	885
valid_sources[0x5a]	317508	1			T1	1269		T2	1403		T3	853
valid_sources[0x5b]	312382	1			T1	1250		T2	1188		T3	687
valid_sources[0x5c]	323149	1			T1	1303		T2	1285		T3	1000
valid_sources[0x5d]	322447	1			T1	1370		T2	1357		T3	783
valid_sources[0x5e]	317358	1			T1	1287		T2	1300		T3	729
valid_sources[0x5f]	331444	1			T1	1225		T2	1319		T3	813
valid_sources[0x60]	648623	1			T1	1260		T2	1453		T3	1045
valid_sources[0x61]	331146	1			T1	1225		T2	1236		T3	749
valid_sources[0x62]	335515	1			T1	1265		T2	1302		T3	1281
valid_sources[0x63]	324022	1			T1	1219		T2	1347		T3	1090
valid_sources[0x64]	332502	1			T1	1331		T2	1285		T3	1014
valid_sources[0x65]	326439	1			T1	1178		T2	1268		T3	625
valid_sources[0x66]	333226	1			T1	1287		T2	1329		T3	1113
valid_sources[0x67]	313568	1			T1	1255		T2	1444		T3	1011
valid_sources[0x68]	325302	1			T1	1302		T2	1215		T3	1094
valid_sources[0x69]	321354	1			T1	1244		T2	1257		T3	964
valid_sources[0x6a]	349479	1			T1	1273		T2	1342		T3	1137
valid_sources[0x6b]	330034	1			T1	1339		T2	1173		T3	1018
valid_sources[0x6c]	315273	1			T1	1310		T2	1293		T3	794
valid_sources[0x6d]	339405	1			T1	1193		T2	1284		T3	818
valid_sources[0x6e]	325880	1			T1	1225		T2	1308		T3	843
valid_sources[0x6f]	327511	1			T1	1236		T2	1236		T3	742
valid_sources[0x70]	330189	1			T1	1349		T2	1229		T3	970
valid_sources[0x71]	316135	1			T1	1181		T2	1318		T3	860
valid_sources[0x72]	314284	1			T1	1382		T2	1286		T3	956
valid_sources[0x73]	320233	1			T1	1290		T2	1294		T3	879
valid_sources[0x74]	322604	1			T1	1313		T2	1316		T3	986
valid_sources[0x75]	325951	1			T1	1253		T2	1444		T3	914
valid_sources[0x76]	323824	1			T1	1317		T2	1389		T3	1005
valid_sources[0x77]	333675	1			T1	1352		T2	1361		T3	1108
valid_sources[0x78]	320519	1			T1	1255		T2	1284		T3	933
valid_sources[0x79]	323569	1			T1	1305		T2	1314		T3	1055
valid_sources[0x7a]	336347	1			T1	1247		T2	1272		T3	1017
valid_sources[0x7b]	327382	1			T1	1259		T2	1221		T3	818
valid_sources[0x7c]	325913	1			T1	1255		T2	1370		T3	955
valid_sources[0x7d]	329194	1			T1	1251		T2	1389		T3	811
valid_sources[0x7e]	330927	1			T1	1247		T2	1290		T3	1074
valid_sources[0x7f]	318581	1			T1	1241		T2	1259		T3	884
valid_sources[0x80]	320957	1			T1	1291		T2	1309		T3	888

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7210193

1

T1

20321

T2

20715

T3

15610

values[0x0]

all_enables

biggest_size

15306285

1

T1

52819

T2

54469

T3

41202

values[0x1]

all_enables

biggest_size

8938211

1

T1

30061

T2

30878

T3

23425