Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T68,T225
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13253	0	0
DisabledNoTrigBkwd_A	2147483647	837272	0	0
DisabledNoTrigFwd_A	2147483647	1533867010	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13253	0	0
T19	3144	932	0	0
T32	328065	0	0	0
T53	9415	0	0	0
T54	56664	0	0	0
T68	0	591	0	0
T99	432688	0	0	0
T100	457645	0	0	0
T102	681573	0	0	0
T103	43108	0	0	0
T117	828657	0	0	0
T215	0	331	0	0
T225	0	779	0	0
T226	4234	841	0	0
T227	4615	1100	0	0
T228	1178	470	0	0
T229	0	331	0	0
T230	0	438	0	0
T231	0	668	0	0
T232	0	463	0	0
T233	0	609	0	0
T234	0	642	0	0
T235	0	917	0	0
T236	0	606	0	0
T237	0	301	0	0
T238	0	1259	0	0
T239	0	850	0	0
T240	0	493	0	0
T241	0	632	0	0
T242	45769	0	0	0
T243	5632	0	0	0
T244	191501	0	0	0
T245	14533	0	0	0
T246	72028	0	0	0
T247	20185	0	0	0
T248	41614	0	0	0
T249	216546	0	0	0
T250	371352	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	837272	0	0
T1	1191844	3882	0	0
T2	1055960	5644	0	0
T3	1132104	22	0	0
T4	0	8	0	0
T5	0	9084	0	0
T6	0	9749	0	0
T10	1637852	2736	0	0
T11	785792	4	0	0
T12	1018104	1	0	0
T13	0	2	0	0
T16	430076	264	0	0
T17	0	15811	0	0
T18	20056	0	0	0
T19	12576	18	0	0
T20	246456	55	0	0
T24	0	341	0	0
T26	0	5	0	0
T27	0	2	0	0
T28	0	454	0	0
T48	0	73	0	0
T49	0	1391	0	0
T50	0	95	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1533867010	0	0
T1	1191844	599005	0	0
T2	1055960	300646	0	0
T3	1132104	1126638	0	0
T10	1637852	1240160	0	0
T11	785792	595467	0	0
T12	1018104	399566	0	0
T16	430076	227185	0	0
T18	20056	15429	0	0
T19	12576	8058	0	0
T20	246456	197338	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T226,T233,T240
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	704141077	1943	0	0
DisabledNoTrigBkwd_A	704141077	224684	0	0
DisabledNoTrigFwd_A	704141077	348640924	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	1943	0	0
T53	9415	0	0	0
T54	56664	0	0	0
T99	432688	0	0	0
T100	457645	0	0	0
T117	828657	0	0	0
T226	4234	841	0	0
T227	4615	0	0	0
T233	0	609	0	0
T240	0	493	0	0
T242	45769	0	0	0
T243	5632	0	0	0
T244	191501	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	224684	0	0
T1	297961	1	0	0
T2	263990	1887	0	0
T3	283026	4	0	0
T4	0	8	0	0
T5	0	4793	0	0
T10	409463	0	0	0
T11	196448	0	0	0
T12	254526	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	55	0	0
T24	0	332	0	0
T27	0	2	0	0
T48	0	73	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	348640924	0	0
T1	297961	297400	0	0
T2	263990	9455	0	0
T3	283026	282460	0	0
T10	409463	409455	0	0
T11	196448	195306	0	0
T12	254526	39571	0	0
T16	107519	107514	0	0
T18	5014	582	0	0
T19	3144	1999	0	0
T20	61614	20674	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T228,T229,T237
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T10

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	704141077	1952	0	0
DisabledNoTrigBkwd_A	704141077	195087	0	0
DisabledNoTrigFwd_A	704141077	363171647	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	1952	0	0
T32	328065	0	0	0
T102	681573	0	0	0
T103	43108	0	0	0
T228	1178	470	0	0
T229	0	331	0	0
T237	0	301	0	0
T239	0	850	0	0
T245	14533	0	0	0
T246	72028	0	0	0
T247	20185	0	0	0
T248	41614	0	0	0
T249	216546	0	0	0
T250	371352	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	195087	0	0
T1	297961	1801	0	0
T2	263990	2055	0	0
T3	283026	0	0	0
T5	0	1639	0	0
T6	0	3586	0	0
T10	409463	5	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T24	0	1	0	0
T26	0	5	0	0
T28	0	174	0	0
T50	0	95	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	363171647	0	0
T1	297961	2160	0	0
T2	263990	18057	0	0
T3	283026	282460	0	0
T10	409463	408903	0	0
T11	196448	196440	0	0
T12	254526	199197	0	0
T16	107519	107514	0	0
T18	5014	4949	0	0
T19	3144	2010	0	0
T20	61614	57575	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T225,T227
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T10

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	704141077	6164	0	0
DisabledNoTrigBkwd_A	704141077	193853	0	0
DisabledNoTrigFwd_A	704141077	399891682	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	6164	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T16	107519	0	0	0
T17	196944	0	0	0
T19	3144	932	0	0
T20	61614	0	0	0
T21	70673	0	0	0
T22	8542	0	0	0
T23	11177	0	0	0
T48	45616	0	0	0
T215	0	331	0	0
T225	0	779	0	0
T227	0	1100	0	0
T231	0	668	0	0
T232	0	463	0	0
T238	0	1259	0	0
T241	0	632	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	193853	0	0
T1	297961	2079	0	0
T2	263990	0	0	0
T3	283026	18	0	0
T5	0	1532	0	0
T6	0	6163	0	0
T10	409463	1	0	0
T11	196448	4	0	0
T12	254526	0	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	18	0	0
T20	61614	0	0	0
T24	0	4	0	0
T28	0	206	0	0
T49	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	399891682	0	0
T1	297961	2170	0	0
T2	263990	263630	0	0
T3	283026	279258	0	0
T10	409463	407725	0	0
T11	196448	7281	0	0
T12	254526	590	0	0
T16	107519	11468	0	0
T18	5014	4949	0	0
T19	3144	2019	0	0
T20	61614	57572	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T230,T234
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T10

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	704141077	3194	0	0
DisabledNoTrigBkwd_A	704141077	223648	0	0
DisabledNoTrigFwd_A	704141077	422162757	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	3194	0	0
T6	199534	0	0	0
T15	162757	0	0	0
T26	93277	0	0	0
T50	90083	0	0	0
T68	2851	591	0	0
T69	25687	0	0	0
T70	41918	0	0	0
T71	28587	0	0	0
T72	35386	0	0	0
T73	10095	0	0	0
T230	0	438	0	0
T234	0	642	0	0
T235	0	917	0	0
T236	0	606	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	223648	0	0
T1	297961	1	0	0
T2	263990	1702	0	0
T3	283026	0	0	0
T5	0	1120	0	0
T10	409463	2730	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	264	0	0
T17	0	15811	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T24	0	4	0	0
T28	0	74	0	0
T49	0	1384	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	422162757	0	0
T1	297961	297275	0	0
T2	263990	9504	0	0
T3	283026	282460	0	0
T10	409463	14077	0	0
T11	196448	196440	0	0
T12	254526	160208	0	0
T16	107519	689	0	0
T18	5014	4949	0	0
T19	3144	2030	0	0
T20	61614	61517	0	0