Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T10,T21
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T10,T21
1	1	1	Covered	T21,T22,T23

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T24,T25,T5
1	0	Covered	T5,T6,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T21,T22,T23
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Not Covered
1	1	Covered	T24,T25,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T27,T24

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T19

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T21,T22,T23

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T21,T22,T23
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T10,T28,T29
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T30,T31,T32
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T1,T25,T33
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T33,T34,T35
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T10,T16
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T21,T22,T23
TimeoutSt->Phase0St	172	Covered	T24,T25,T5

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T10,T28,T36
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T17,T30,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T25,T33
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T34,T35
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T10,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	635	0	0
CheckAccumTrig0_A	2147483647	2353	0	0
CheckAccumTrig1_A	2147483647	118	0	0
CheckClr_A	2147483647	1129	0	0
CheckEn_A	2147483647	1158134079	0	0
CheckPhase0_A	2147483647	2642	0	0
CheckPhase1_A	2147483647	2603	0	0
CheckPhase2_A	2147483647	2558	0	0
CheckPhase3_A	2147483647	2506	0	0
CheckTimeout0_A	2147483647	7036	0	0
CheckTimeoutSt1_A	2147483647	684073	0	0
CheckTimeoutSt2_A	2147483647	6685	0	0
CheckTimeoutStTrig_A	2147483647	221	0	0
ErrorStAllEscAsserted_A	2147483647	3320	0	0
ErrorStIsTerminal_A	2147483647	2720	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	635	0	0
T7	68788	153	0	0
T8	0	123	0	0
T9	0	117	0	0
T37	0	120	0	0
T38	0	122	0	0
T39	381808	0	0	0
T40	491172	0	0	0
T41	375704	0	0	0
T42	255268	0	0	0
T43	896760	0	0	0
T44	372204	0	0	0
T45	805256	0	0	0
T46	19076	0	0	0
T47	71736	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2353	0	0
T1	1191844	4	0	0
T2	1055960	3	0	0
T3	1132104	3	0	0
T4	0	1	0	0
T5	0	19	0	0
T6	0	5	0	0
T10	1637852	4	0	0
T11	785792	1	0	0
T12	1018104	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T16	430076	2	0	0
T18	20056	0	0	0
T19	12576	1	0	0
T20	246456	1	0	0
T24	0	3	0	0
T26	0	1	0	0
T27	0	2	0	0
T28	0	5	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118	0	0
T5	318173	1	0	0
T6	399068	1	0	0
T14	906857	0	0	0
T15	325514	0	0	0
T26	0	1	0	0
T29	0	1	0	0
T50	90083	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	7848	1	0	0
T56	165097	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	2851	0	0	0
T69	25687	0	0	0
T70	41918	0	0	0
T71	57174	0	0	0
T72	70772	0	0	0
T73	20190	0	0	0
T74	246016	0	0	0
T75	142604	0	0	0
T76	16702	0	0	0
T77	60278	0	0	0
T78	36296	0	0	0
T79	67855	0	0	0
T80	393422	0	0	0
T81	338126	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1129	0	0
T1	297961	1	0	0
T2	263990	0	0	0
T3	566052	1	0	0
T5	0	10	0	0
T10	1637852	3	0	0
T11	785792	0	0	0
T12	1018104	0	0	0
T16	430076	1	0	0
T17	393888	0	0	0
T18	20056	0	0	0
T19	12576	0	0	0
T20	246456	0	0	0
T21	212019	0	0	0
T22	25626	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T28	0	2	0	0
T29	0	1	0	0
T33	0	2	0	0
T36	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T82	0	4	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	4	0	0
T87	0	1	0	0
T88	0	2	0	0
T89	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1158134079	0	0
T1	1191844	313189	0	0
T2	1055960	300646	0	0
T3	1132104	579866	0	0
T10	1637852	1240160	0	0
T11	785792	595465	0	0
T12	1018104	399564	0	0
T16	430076	227185	0	0
T18	20056	15426	0	0
T19	12576	8058	0	0
T20	246456	178735	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2642	0	0
T1	1191844	4	0	0
T2	1055960	3	0	0
T3	1132104	3	0	0
T4	0	1	0	0
T5	0	7	0	0
T6	0	6	0	0
T10	1637852	3	0	0
T11	785792	1	0	0
T12	1018104	1	0	0
T13	0	2	0	0
T15	0	1	0	0
T16	430076	2	0	0
T18	20056	0	0	0
T19	12576	1	0	0
T20	246456	1	0	0
T24	0	5	0	0
T25	0	3	0	0
T27	0	2	0	0
T28	0	4	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2603	0	0
T1	1191844	4	0	0
T2	1055960	3	0	0
T3	1132104	3	0	0
T4	0	1	0	0
T5	0	7	0	0
T6	0	6	0	0
T10	1637852	3	0	0
T11	785792	1	0	0
T12	1018104	1	0	0
T13	0	2	0	0
T15	0	1	0	0
T16	430076	2	0	0
T18	20056	0	0	0
T19	12576	1	0	0
T20	246456	1	0	0
T24	0	5	0	0
T25	0	3	0	0
T27	0	2	0	0
T28	0	4	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2558	0	0
T1	893883	2	0	0
T2	1055960	2	0	0
T3	1132104	3	0	0
T4	0	1	0	0
T5	0	18	0	0
T6	0	6	0	0
T10	1637852	1	0	0
T11	785792	1	0	0
T12	1018104	1	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	430076	0	0	0
T18	20056	0	0	0
T19	12576	1	0	0
T20	246456	1	0	0
T21	70673	0	0	0
T24	0	3	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	2	0	0
T28	0	3	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2506	0	0
T1	893883	2	0	0
T2	1055960	2	0	0
T3	1132104	3	0	0
T4	0	1	0	0
T5	0	18	0	0
T6	0	6	0	0
T10	1637852	1	0	0
T11	785792	1	0	0
T12	1018104	1	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	430076	0	0	0
T18	20056	0	0	0
T19	12576	1	0	0
T20	246456	1	0	0
T21	70673	0	0	0
T24	0	3	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	2	0	0
T28	0	3	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7036	0	0
T4	762516	0	0	0
T5	0	6	0	0
T6	0	4	0	0
T13	1329940	0	0	0
T17	787776	0	0	0
T21	212019	11	0	0
T22	34168	6	0	0
T23	44708	2	0	0
T24	63024	2	0	0
T25	0	13	0	0
T26	0	6	0	0
T27	229916	0	0	0
T28	2236788	0	0	0
T34	0	8	0	0
T48	182464	0	0	0
T49	831661	9	0	0
T50	0	3	0	0
T70	0	2	0	0
T72	0	1	0	0
T73	0	13	0	0
T86	0	1	0	0
T90	0	3	0	0
T91	0	15	0	0
T92	0	2	0	0
T93	0	7	0	0
T94	0	7	0	0
T95	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	684073	0	0
T4	762516	0	0	0
T5	0	295	0	0
T6	0	460	0	0
T13	1329940	0	0	0
T17	787776	0	0	0
T21	212019	1756	0	0
T22	34168	385	0	0
T23	44708	239	0	0
T24	63024	175	0	0
T25	0	2378	0	0
T26	0	971	0	0
T27	229916	0	0	0
T28	2236788	0	0	0
T34	0	1153	0	0
T48	182464	0	0	0
T49	831661	1023	0	0
T50	0	855	0	0
T70	0	269	0	0
T72	0	27	0	0
T73	0	775	0	0
T86	0	418	0	0
T90	0	293	0	0
T91	0	1393	0	0
T92	0	314	0	0
T93	0	869	0	0
T94	0	1376	0	0
T95	0	731	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6685	0	0
T4	762516	0	0	0
T5	0	3	0	0
T13	1329940	0	0	0
T17	787776	0	0	0
T21	212019	11	0	0
T22	34168	2	0	0
T23	44708	1	0	0
T24	63024	0	0	0
T25	0	9	0	0
T27	229916	0	0	0
T28	2236788	0	0	0
T29	0	363	0	0
T34	0	8	0	0
T48	182464	0	0	0
T49	831661	0	0	0
T51	0	1	0	0
T56	0	3	0	0
T70	0	2	0	0
T72	0	1	0	0
T73	0	8	0	0
T76	0	3	0	0
T82	0	1	0	0
T90	0	3	0	0
T91	0	14	0	0
T93	0	10	0	0
T94	0	7	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	221	0	0
T5	636346	2	0	0
T6	399068	1	0	0
T14	1813714	0	0	0
T15	162757	0	0	0
T24	15756	1	0	0
T25	167630	2	0	0
T26	93277	0	0	0
T29	559282	0	0	0
T34	0	1	0	0
T49	831661	0	0	0
T50	90083	2	0	0
T51	376277	0	0	0
T56	0	2	0	0
T68	5702	0	0	0
T69	51374	0	0	0
T70	83836	0	0	0
T71	28587	0	0	0
T72	35386	0	0	0
T75	0	2	0	0
T80	0	2	0	0
T82	352921	0	0	0
T83	12307	0	0	0
T86	0	2	0	0
T89	0	3	0	0
T90	9327	0	0	0
T91	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T98	0	1	0	0
T99	0	3	0	0
T100	0	2	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	6502	0	0	0
T106	928435	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3320	0	0
T7	68788	690	0	0
T8	0	684	0	0
T9	0	618	0	0
T37	0	680	0	0
T38	0	648	0	0
T39	381808	0	0	0
T40	491172	0	0	0
T41	375704	0	0	0
T42	255268	0	0	0
T43	896760	0	0	0
T44	372204	0	0	0
T45	805256	0	0	0
T46	19076	0	0	0
T47	71736	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2720	0	0
T7	68788	570	0	0
T8	0	564	0	0
T9	0	498	0	0
T37	0	560	0	0
T38	0	528	0	0
T39	381808	0	0	0
T40	491172	0	0	0
T41	375704	0	0	0
T42	255268	0	0	0
T43	896760	0	0	0
T44	372204	0	0	0
T45	805256	0	0	0
T46	19076	0	0	0
T47	71736	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1191844	1191808	0	0
T2	1055960	1055932	0	0
T3	1132104	1132076	0	0
T10	1637852	1637820	0	0
T11	785792	785760	0	0
T12	1018104	1017732	0	0
T16	430076	430056	0	0
T18	20056	19796	0	0
T19	12576	12340	0	0
T20	246456	246068	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1191844	1191808	0	0
T2	1055960	1055932	0	0
T3	1132104	1132076	0	0
T10	1637852	1637820	0	0
T11	785792	785760	0	0
T12	1018104	1017732	0	0
T16	430076	430056	0	0
T18	20056	19796	0	0
T19	12576	12340	0	0
T20	246456	246068	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T21,T22,T23
1	0	1	Covered	T2,T11,T20
1	1	0	Covered	T10,T21,T17
1	1	1	Covered	T21,T22,T24

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T24
0	1	Covered	T24,T25,T6
1	0	Covered	T5,T26,T29

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T21,T22,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T26,T29

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T24
1	0	Not Covered
1	1	Covered	T24,T25,T6

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T20,T12,T27
1	Covered	T1,T2,T3

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T25,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T12,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T27,T24,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T48,T27

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T2,T3,T20
TerminalSt	249	Covered	T2,T3,T20
TimeoutSt	159	Covered	T21,T22,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T21,T22,T24
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T36,T107
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T32,T108
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T1,T33,T34
Phase2St->Phase3St	233	Covered	T2,T3,T20
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T34,T35,T56
Phase3St->TerminalSt	249	Covered	T2,T3,T20
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T27,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T21,T22,T25
TimeoutSt->Phase0St	172	Covered	T24,T25,T5

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T36,T107,T109
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T32,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T33,T34
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T35,T56
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T27,T5,T50
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	704141077	133	0	0
CheckAccumTrig0_A	704141077	833	0	0
CheckAccumTrig1_A	704141077	52	0	0
CheckClr_A	704141077	443	0	0
CheckEn_A	703954084	256297391	0	0
CheckPhase0_A	704141077	935	0	0
CheckPhase1_A	704141077	922	0	0
CheckPhase2_A	704141077	899	0	0
CheckPhase3_A	704141077	871	0	0
CheckTimeout0_A	704141077	2340	0	0
CheckTimeoutSt1_A	704141077	219815	0	0
CheckTimeoutSt2_A	704141077	2215	0	0
CheckTimeoutStTrig_A	704141077	70	0	0
ErrorStAllEscAsserted_A	704141077	834	0	0
ErrorStIsTerminal_A	704141077	684	0	0
EscStateOut_A	703951978	703885357	0	0
u_state_regs_A	704141077	704010667	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	133	0	0
T7	17197	38	0	0
T8	0	23	0	0
T9	0	24	0	0
T37	0	26	0	0
T38	0	22	0	0
T39	95452	0	0	0
T40	122793	0	0	0
T41	93926	0	0	0
T42	63817	0	0	0
T43	224190	0	0	0
T44	93051	0	0	0
T45	201314	0	0	0
T46	4769	0	0	0
T47	17934	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	833	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	1	0	0
T4	0	1	0	0
T5	0	10	0	0
T10	409463	0	0	0
T11	196448	0	0	0
T12	254526	1	0	0
T14	0	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	1	0	0
T27	0	2	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	52	0	0
T5	318173	1	0	0
T6	199534	0	0	0
T14	906857	0	0	0
T15	162757	0	0	0
T26	0	1	0	0
T29	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T68	2851	0	0	0
T69	25687	0	0	0
T70	41918	0	0	0
T71	28587	0	0	0
T72	35386	0	0	0
T73	10095	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	443	0	0
T1	297961	1	0	0
T2	263990	0	0	0
T3	283026	0	0	0
T5	0	6	0	0
T10	409463	0	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T33	0	2	0	0
T36	0	1	0	0
T50	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703954084	256297391	0	0
T1	297961	297400	0	0
T2	263990	9455	0	0
T3	283026	3078	0	0
T10	409463	409455	0	0
T11	196448	195306	0	0
T12	254526	39571	0	0
T16	107519	107514	0	0
T18	5014	582	0	0
T19	3144	1999	0	0
T20	61614	2074	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	935	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	1	0	0
T4	0	1	0	0
T10	409463	0	0	0
T11	196448	0	0	0
T12	254526	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T27	0	2	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	922	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	1	0	0
T4	0	1	0	0
T10	409463	0	0	0
T11	196448	0	0	0
T12	254526	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T27	0	2	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	899	0	0
T2	263990	1	0	0
T3	283026	1	0	0
T4	0	1	0	0
T5	0	11	0	0
T10	409463	0	0	0
T11	196448	0	0	0
T12	254526	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	1	0	0
T21	70673	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T27	0	2	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	871	0	0
T2	263990	1	0	0
T3	283026	1	0	0
T4	0	1	0	0
T5	0	11	0	0
T10	409463	0	0	0
T11	196448	0	0	0
T12	254526	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	1	0	0
T21	70673	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T27	0	2	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	2340	0	0
T4	190629	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T13	332485	0	0	0
T17	196944	0	0	0
T21	70673	3	0	0
T22	8542	2	0	0
T23	11177	0	0	0
T24	15756	1	0	0
T25	0	4	0	0
T27	57479	0	0	0
T28	559197	0	0	0
T48	45616	0	0	0
T50	0	1	0	0
T70	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	219815	0	0
T4	190629	0	0	0
T5	0	4	0	0
T6	0	90	0	0
T13	332485	0	0	0
T17	196944	0	0	0
T21	70673	486	0	0
T22	8542	165	0	0
T23	11177	0	0	0
T24	15756	22	0	0
T25	0	788	0	0
T27	57479	0	0	0
T28	559197	0	0	0
T48	45616	0	0	0
T50	0	656	0	0
T70	0	269	0	0
T72	0	27	0	0
T73	0	74	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	2215	0	0
T4	190629	0	0	0
T13	332485	0	0	0
T17	196944	0	0	0
T21	70673	3	0	0
T22	8542	2	0	0
T23	11177	0	0	0
T24	15756	0	0	0
T25	0	3	0	0
T27	57479	0	0	0
T28	559197	0	0	0
T29	0	363	0	0
T48	45616	0	0	0
T51	0	1	0	0
T70	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T82	0	1	0	0
T96	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	70	0	0
T5	318173	0	0	0
T6	199534	1	0	0
T14	906857	0	0	0
T24	15756	1	0	0
T25	83815	1	0	0
T34	0	1	0	0
T49	831661	0	0	0
T50	0	1	0	0
T68	2851	0	0	0
T69	25687	0	0	0
T70	41918	0	0	0
T86	0	1	0	0
T89	0	2	0	0
T90	9327	0	0	0
T94	0	1	0	0
T98	0	1	0	0
T100	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	834	0	0
T7	17197	163	0	0
T8	0	169	0	0
T9	0	147	0	0
T37	0	185	0	0
T38	0	170	0	0
T39	95452	0	0	0
T40	122793	0	0	0
T41	93926	0	0	0
T42	63817	0	0	0
T43	224190	0	0	0
T44	93051	0	0	0
T45	201314	0	0	0
T46	4769	0	0	0
T47	17934	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	684	0	0
T7	17197	133	0	0
T8	0	139	0	0
T9	0	117	0	0
T37	0	155	0	0
T38	0	140	0	0
T39	95452	0	0	0
T40	122793	0	0	0
T41	93926	0	0	0
T42	63817	0	0	0
T43	224190	0	0	0
T44	93051	0	0	0
T45	201314	0	0	0
T46	4769	0	0	0
T47	17934	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703951978	703885357	0	0
T1	297961	297952	0	0
T2	263990	263983	0	0
T3	283026	283019	0	0
T10	409463	409455	0	0
T11	196448	196440	0	0
T12	254526	254433	0	0
T16	107519	107514	0	0
T18	5014	4949	0	0
T19	3144	3085	0	0
T20	61614	61517	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	704010667	0	0
T1	297961	297952	0	0
T2	263990	263983	0	0
T3	283026	283019	0	0
T10	409463	409455	0	0
T11	196448	196440	0	0
T12	254526	254433	0	0
T16	107519	107514	0	0
T18	5014	4949	0	0
T19	3144	3085	0	0
T20	61614	61517	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T21,T22
1	0	1	Covered	T2,T3,T12
1	1	0	Covered	T3,T10,T21
1	1	1	Covered	T21,T25,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T25,T5
0	1	Covered	T25,T5,T91
1	0	Covered	T55,T57,T60

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T21,T25,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T55,T57,T60

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T25,T5
1	0	Not Covered
1	1	Covered	T25,T5,T91

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T10,T13
1	Covered	T2,T25,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T28
1	Covered	T10,T13,T24

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T13
1	Covered	T1,T28,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T86,T110,T87

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T24,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T28,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T10
Phase1St	198	Covered	T1,T2,T10
Phase2St	215	Covered	T1,T2,T10
Phase3St	233	Covered	T1,T2,T10
TerminalSt	249	Covered	T1,T2,T10
TimeoutSt	159	Covered	T21,T25,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T10
IdleSt->TimeoutSt	159	Covered	T21,T25,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T75,T111
Phase0St->Phase1St	198	Covered	T1,T2,T10
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T112,T113
Phase1St->Phase2St	215	Covered	T1,T2,T10
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T25,T30,T114
Phase2St->Phase3St	233	Covered	T1,T2,T10
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T33,T30,T59
Phase3St->TerminalSt	249	Covered	T1,T2,T10
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T28,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T21,T73,T91
TimeoutSt->Phase0St	172	Covered	T25,T5,T91

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T25,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T5,T91
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T25,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T73,T91
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T111,T115
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T112,T113
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T25,T30,T114
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T10
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T30,T59
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T28,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T10
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	704141077	162	0	0
CheckAccumTrig0_A	704141077	495	0	0
CheckAccumTrig1_A	704141077	21	0	0
CheckClr_A	704141077	227	0	0
CheckEn_A	703954084	291933276	0	0
CheckPhase0_A	704141077	577	0	0
CheckPhase1_A	704141077	574	0	0
CheckPhase2_A	704141077	566	0	0
CheckPhase3_A	704141077	557	0	0
CheckTimeout0_A	704141077	963	0	0
CheckTimeoutSt1_A	704141077	110107	0	0
CheckTimeoutSt2_A	704141077	868	0	0
CheckTimeoutStTrig_A	704141077	69	0	0
ErrorStAllEscAsserted_A	704141077	825	0	0
ErrorStIsTerminal_A	704141077	675	0	0
EscStateOut_A	703951978	703885357	0	0
u_state_regs_A	704141077	704010667	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	162	0	0
T7	17197	41	0	0
T8	0	26	0	0
T9	0	37	0	0
T37	0	29	0	0
T38	0	29	0	0
T39	95452	0	0	0
T40	122793	0	0	0
T41	93926	0	0	0
T42	63817	0	0	0
T43	224190	0	0	0
T44	93051	0	0	0
T45	201314	0	0	0
T46	4769	0	0	0
T47	17934	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	495	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	0	0	0
T5	0	2	0	0
T6	0	3	0	0
T10	409463	1	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T24	0	1	0	0
T26	0	1	0	0
T28	0	3	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	21	0	0
T55	7848	1	0	0
T56	165097	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T74	246016	0	0	0
T75	142604	0	0	0
T76	16702	0	0	0
T77	60278	0	0	0
T78	36296	0	0	0
T79	67855	0	0	0
T80	393422	0	0	0
T81	338126	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	227	0	0
T5	0	2	0	0
T10	409463	1	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T16	107519	0	0	0
T17	196944	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T21	70673	0	0	0
T22	8542	0	0	0
T25	0	1	0	0
T28	0	2	0	0
T36	0	1	0	0
T82	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T88	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703954084	291933276	0	0
T1	297961	2160	0	0
T2	263990	18057	0	0
T3	283026	282460	0	0
T10	409463	408903	0	0
T11	196448	196439	0	0
T12	254526	199196	0	0
T16	107519	107514	0	0
T18	5014	4948	0	0
T19	3144	2010	0	0
T20	61614	57574	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	577	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	0	0	0
T5	0	4	0	0
T6	0	3	0	0
T10	409463	1	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	0	2	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	574	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	0	0	0
T5	0	4	0	0
T6	0	3	0	0
T10	409463	1	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	0	2	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	566	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	0	0	0
T5	0	4	0	0
T6	0	3	0	0
T10	409463	1	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T24	0	1	0	0
T26	0	1	0	0
T28	0	2	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	557	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	0	0	0
T5	0	4	0	0
T6	0	3	0	0
T10	409463	1	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T24	0	1	0	0
T26	0	1	0	0
T28	0	2	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	963	0	0
T4	190629	0	0	0
T5	0	2	0	0
T13	332485	0	0	0
T17	196944	0	0	0
T21	70673	1	0	0
T22	8542	0	0	0
T23	11177	0	0	0
T24	15756	0	0	0
T25	0	1	0	0
T27	57479	0	0	0
T28	559197	0	0	0
T34	0	8	0	0
T48	45616	0	0	0
T73	0	6	0	0
T86	0	1	0	0
T91	0	2	0	0
T93	0	7	0	0
T94	0	7	0	0
T95	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	110107	0	0
T4	190629	0	0	0
T5	0	32	0	0
T13	332485	0	0	0
T17	196944	0	0	0
T21	70673	208	0	0
T22	8542	0	0	0
T23	11177	0	0	0
T24	15756	0	0	0
T25	0	196	0	0
T27	57479	0	0	0
T28	559197	0	0	0
T34	0	1153	0	0
T48	45616	0	0	0
T73	0	340	0	0
T86	0	418	0	0
T91	0	192	0	0
T93	0	869	0	0
T94	0	1376	0	0
T95	0	731	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	868	0	0
T4	190629	0	0	0
T13	332485	0	0	0
T17	196944	0	0	0
T21	70673	1	0	0
T22	8542	0	0	0
T23	11177	0	0	0
T24	15756	0	0	0
T27	57479	0	0	0
T28	559197	0	0	0
T34	0	8	0	0
T48	45616	0	0	0
T56	0	3	0	0
T73	0	6	0	0
T76	0	3	0	0
T91	0	1	0	0
T93	0	7	0	0
T94	0	7	0	0
T95	0	1	0	0
T97	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	69	0	0
T5	318173	2	0	0
T6	199534	0	0	0
T14	906857	0	0	0
T15	162757	0	0	0
T25	83815	1	0	0
T56	0	1	0	0
T68	2851	0	0	0
T69	25687	0	0	0
T70	41918	0	0	0
T71	28587	0	0	0
T72	35386	0	0	0
T80	0	1	0	0
T86	0	1	0	0
T91	0	1	0	0
T95	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T103	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	825	0	0
T7	17197	195	0	0
T8	0	145	0	0
T9	0	170	0	0
T37	0	172	0	0
T38	0	143	0	0
T39	95452	0	0	0
T40	122793	0	0	0
T41	93926	0	0	0
T42	63817	0	0	0
T43	224190	0	0	0
T44	93051	0	0	0
T45	201314	0	0	0
T46	4769	0	0	0
T47	17934	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	675	0	0
T7	17197	165	0	0
T8	0	115	0	0
T9	0	140	0	0
T37	0	142	0	0
T38	0	113	0	0
T39	95452	0	0	0
T40	122793	0	0	0
T41	93926	0	0	0
T42	63817	0	0	0
T43	224190	0	0	0
T44	93051	0	0	0
T45	201314	0	0	0
T46	4769	0	0	0
T47	17934	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703951978	703885357	0	0
T1	297961	297952	0	0
T2	263990	263983	0	0
T3	283026	283019	0	0
T10	409463	409455	0	0
T11	196448	196440	0	0
T12	254526	254433	0	0
T16	107519	107514	0	0
T18	5014	4949	0	0
T19	3144	3085	0	0
T20	61614	61517	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	704010667	0	0
T1	297961	297952	0	0
T2	263990	263983	0	0
T3	283026	283019	0	0
T10	409463	409455	0	0
T11	196448	196440	0	0
T12	254526	254433	0	0
T16	107519	107514	0	0
T18	5014	4949	0	0
T19	3144	3085	0	0
T20	61614	61517	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T10,T21
1	0	1	Covered	T1,T2,T19
1	1	0	Covered	T10,T22,T17
1	1	1	Covered	T21,T23,T90

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T23,T90
0	1	Covered	T50,T89,T99
1	0	Covered	T6,T59,T116

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T21,T23,T90
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T59,T116

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T23,T90
1	0	Not Covered
1	1	Covered	T50,T89,T99

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T3,T10,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T19,T11
1	Covered	T1,T24,T49

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T19
1	Covered	T11,T5,T51

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T19
1	Covered	T3,T28,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T19,T28,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T19,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T19,T11

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T10
Phase1St	198	Covered	T1,T3,T19
Phase2St	215	Covered	T1,T3,T19
Phase3St	233	Covered	T1,T3,T19
TerminalSt	249	Covered	T1,T3,T19
TimeoutSt	159	Covered	T21,T23,T90

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T3,T10
IdleSt->TimeoutSt	159	Covered	T21,T23,T90
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T10,T29,T117
Phase0St->Phase1St	198	Covered	T1,T3,T19
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T118,T119
Phase1St->Phase2St	215	Covered	T1,T3,T19
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T117,T111,T120
Phase2St->Phase3St	233	Covered	T1,T3,T19
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T121,T122,T123
Phase3St->TerminalSt	249	Covered	T1,T3,T19
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T21,T23,T90
TimeoutSt->Phase0St	172	Covered	T6,T50,T89

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T90
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T50,T89
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T90
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T90
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T10,T117,T119
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T119,T124
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T117,T111,T120
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T121,T122,T123
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T5,T82
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	704141077	188	0	0
CheckAccumTrig0_A	704141077	481	0	0
CheckAccumTrig1_A	704141077	18	0	0
CheckClr_A	704141077	197	0	0
CheckEn_A	703954084	291122884	0	0
CheckPhase0_A	704141077	540	0	0
CheckPhase1_A	704141077	530	0	0
CheckPhase2_A	704141077	523	0	0
CheckPhase3_A	704141077	516	0	0
CheckTimeout0_A	704141077	1531	0	0
CheckTimeoutSt1_A	704141077	147991	0	0
CheckTimeoutSt2_A	704141077	1462	0	0
CheckTimeoutStTrig_A	704141077	50	0	0
ErrorStAllEscAsserted_A	704141077	835	0	0
ErrorStIsTerminal_A	704141077	685	0	0
EscStateOut_A	703951978	703885357	0	0
u_state_regs_A	704141077	704010667	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	188	0	0
T7	17197	46	0	0
T8	0	45	0	0
T9	0	38	0	0
T37	0	30	0	0
T38	0	29	0	0
T39	95452	0	0	0
T40	122793	0	0	0
T41	93926	0	0	0
T42	63817	0	0	0
T43	224190	0	0	0
T44	93051	0	0	0
T45	201314	0	0	0
T46	4769	0	0	0
T47	17934	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	481	0	0
T1	297961	1	0	0
T2	263990	0	0	0
T3	283026	2	0	0
T5	0	3	0	0
T6	0	2	0	0
T10	409463	1	0	0
T11	196448	1	0	0
T12	254526	0	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	1	0	0
T20	61614	0	0	0
T24	0	1	0	0
T28	0	1	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	18	0	0
T6	199534	1	0	0
T15	162757	0	0	0
T26	93277	0	0	0
T29	559282	0	0	0
T50	90083	0	0	0
T59	0	1	0	0
T67	0	1	0	0
T71	28587	0	0	0
T72	35386	0	0	0
T73	10095	0	0	0
T82	352921	0	0	0
T105	6502	0	0	0
T116	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	197	0	0
T3	283026	1	0	0
T5	0	1	0	0
T10	409463	1	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T21	70673	0	0	0
T22	8542	0	0	0
T51	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T89	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703954084	291122884	0	0
T1	297961	2170	0	0
T2	263990	263630	0	0
T3	283026	11869	0	0
T10	409463	407725	0	0
T11	196448	7281	0	0
T12	254526	590	0	0
T16	107519	11468	0	0
T18	5014	4948	0	0
T19	3144	2019	0	0
T20	61614	57571	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	540	0	0
T1	297961	1	0	0
T2	263990	0	0	0
T3	283026	2	0	0
T5	0	3	0	0
T6	0	3	0	0
T10	409463	0	0	0
T11	196448	1	0	0
T12	254526	0	0	0
T15	0	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	1	0	0
T20	61614	0	0	0
T24	0	1	0	0
T28	0	1	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	530	0	0
T1	297961	1	0	0
T2	263990	0	0	0
T3	283026	2	0	0
T5	0	3	0	0
T6	0	3	0	0
T10	409463	0	0	0
T11	196448	1	0	0
T12	254526	0	0	0
T15	0	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	1	0	0
T20	61614	0	0	0
T24	0	1	0	0
T28	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	523	0	0
T1	297961	1	0	0
T2	263990	0	0	0
T3	283026	2	0	0
T5	0	3	0	0
T6	0	3	0	0
T10	409463	0	0	0
T11	196448	1	0	0
T12	254526	0	0	0
T15	0	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	1	0	0
T20	61614	0	0	0
T24	0	1	0	0
T28	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	516	0	0
T1	297961	1	0	0
T2	263990	0	0	0
T3	283026	2	0	0
T5	0	3	0	0
T6	0	3	0	0
T10	409463	0	0	0
T11	196448	1	0	0
T12	254526	0	0	0
T15	0	1	0	0
T16	107519	0	0	0
T18	5014	0	0	0
T19	3144	1	0	0
T20	61614	0	0	0
T24	0	1	0	0
T28	0	1	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	1531	0	0
T4	190629	0	0	0
T5	0	3	0	0
T6	0	2	0	0
T13	332485	0	0	0
T17	196944	0	0	0
T21	70673	7	0	0
T22	8542	0	0	0
T23	11177	1	0	0
T24	15756	0	0	0
T25	0	6	0	0
T27	57479	0	0	0
T28	559197	0	0	0
T48	45616	0	0	0
T50	0	1	0	0
T73	0	1	0	0
T90	0	3	0	0
T91	0	13	0	0
T92	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	147991	0	0
T4	190629	0	0	0
T5	0	259	0	0
T6	0	46	0	0
T13	332485	0	0	0
T17	196944	0	0	0
T21	70673	1062	0	0
T22	8542	0	0	0
T23	11177	106	0	0
T24	15756	0	0	0
T25	0	1128	0	0
T27	57479	0	0	0
T28	559197	0	0	0
T48	45616	0	0	0
T50	0	196	0	0
T73	0	54	0	0
T90	0	293	0	0
T91	0	1201	0	0
T92	0	314	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	1462	0	0
T4	190629	0	0	0
T5	0	3	0	0
T6	0	1	0	0
T13	332485	0	0	0
T17	196944	0	0	0
T21	70673	7	0	0
T22	8542	0	0	0
T23	11177	1	0	0
T24	15756	0	0	0
T25	0	6	0	0
T27	57479	0	0	0
T28	559197	0	0	0
T48	45616	0	0	0
T73	0	1	0	0
T90	0	3	0	0
T91	0	13	0	0
T92	0	2	0	0
T93	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	50	0	0
T26	93277	0	0	0
T29	559282	0	0	0
T50	90083	1	0	0
T51	376277	0	0	0
T56	0	1	0	0
T75	0	2	0	0
T80	0	1	0	0
T82	352921	0	0	0
T83	12307	0	0	0
T84	343297	0	0	0
T89	0	1	0	0
T96	43345	0	0	0
T99	0	2	0	0
T101	0	1	0	0
T102	0	1	0	0
T104	0	1	0	0
T105	6502	0	0	0
T106	928435	0	0	0
T131	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	835	0	0
T7	17197	166	0	0
T8	0	192	0	0
T9	0	158	0	0
T37	0	158	0	0
T38	0	161	0	0
T39	95452	0	0	0
T40	122793	0	0	0
T41	93926	0	0	0
T42	63817	0	0	0
T43	224190	0	0	0
T44	93051	0	0	0
T45	201314	0	0	0
T46	4769	0	0	0
T47	17934	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	685	0	0
T7	17197	136	0	0
T8	0	162	0	0
T9	0	128	0	0
T37	0	128	0	0
T38	0	131	0	0
T39	95452	0	0	0
T40	122793	0	0	0
T41	93926	0	0	0
T42	63817	0	0	0
T43	224190	0	0	0
T44	93051	0	0	0
T45	201314	0	0	0
T46	4769	0	0	0
T47	17934	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703951978	703885357	0	0
T1	297961	297952	0	0
T2	263990	263983	0	0
T3	283026	283019	0	0
T10	409463	409455	0	0
T11	196448	196440	0	0
T12	254526	254433	0	0
T16	107519	107514	0	0
T18	5014	4949	0	0
T19	3144	3085	0	0
T20	61614	61517	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	704010667	0	0
T1	297961	297952	0	0
T2	263990	263983	0	0
T3	283026	283019	0	0
T10	409463	409455	0	0
T11	196448	196440	0	0
T12	254526	254433	0	0
T16	107519	107514	0	0
T18	5014	4949	0	0
T19	3144	3085	0	0
T20	61614	61517	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T22,T17
1	0	1	Covered	T1,T3,T28
1	1	0	Covered	T3,T10,T21
1	1	1	Covered	T22,T23,T24

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T24,T25,T6
1	0	Covered	T50,T78,T58

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T22,T23,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T50,T78,T58

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Not Covered
1	1	Covered	T24,T25,T6

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T17,T24,T49

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T17
1	Covered	T2,T10,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T16
1	Covered	T1,T16,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T16,T28,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T16,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T10,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T10,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T10,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T10
Phase1St	198	Covered	T1,T2,T10
Phase2St	215	Covered	T1,T2,T10
Phase3St	233	Covered	T1,T2,T10
TerminalSt	249	Covered	T1,T2,T10
TimeoutSt	159	Covered	T22,T23,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T10
IdleSt->TimeoutSt	159	Covered	T22,T23,T24
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T17,T31,T112
Phase0St->Phase1St	198	Covered	T1,T2,T10
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T17,T132,T133
Phase1St->Phase2St	215	Covered	T1,T2,T10
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T17,T31,T111
Phase2St->Phase3St	233	Covered	T1,T2,T10
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T30,T59,T134
Phase3St->TerminalSt	249	Covered	T1,T2,T10
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T16,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T22,T23,T49
TimeoutSt->Phase0St	172	Covered	T24,T25,T6

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T49
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T31,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T17,T132,T133
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T17,T31,T111
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T10
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T59,T134
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T16,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T10
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	704141077	152	0	0
CheckAccumTrig0_A	704141077	544	0	0
CheckAccumTrig1_A	704141077	27	0	0
CheckClr_A	704141077	262	0	0
CheckEn_A	703954084	318780528	0	0
CheckPhase0_A	704141077	590	0	0
CheckPhase1_A	704141077	577	0	0
CheckPhase2_A	704141077	570	0	0
CheckPhase3_A	704141077	562	0	0
CheckTimeout0_A	704141077	2202	0	0
CheckTimeoutSt1_A	704141077	206160	0	0
CheckTimeoutSt2_A	704141077	2140	0	0
CheckTimeoutStTrig_A	704141077	32	0	0
ErrorStAllEscAsserted_A	704141077	826	0	0
ErrorStIsTerminal_A	704141077	676	0	0
EscStateOut_A	703951978	703885357	0	0
u_state_regs_A	704141077	704010667	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	152	0	0
T7	17197	28	0	0
T8	0	29	0	0
T9	0	18	0	0
T37	0	35	0	0
T38	0	42	0	0
T39	95452	0	0	0
T40	122793	0	0	0
T41	93926	0	0	0
T42	63817	0	0	0
T43	224190	0	0	0
T44	93051	0	0	0
T45	201314	0	0	0
T46	4769	0	0	0
T47	17934	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	544	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	0	0	0
T5	0	4	0	0
T10	409463	2	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	2	0	0
T17	0	15	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T24	0	1	0	0
T28	0	1	0	0
T49	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	27	0	0
T26	93277	0	0	0
T29	559282	0	0	0
T50	90083	1	0	0
T51	376277	0	0	0
T58	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T82	352921	0	0	0
T83	12307	0	0	0
T84	343297	0	0	0
T96	43345	0	0	0
T105	6502	0	0	0
T106	928435	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	3	0	0
T140	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	262	0	0
T5	0	1	0	0
T10	409463	1	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	1	0	0
T17	196944	14	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T21	70673	0	0	0
T22	8542	0	0	0
T24	0	1	0	0
T49	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T105	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703954084	318780528	0	0
T1	297961	11459	0	0
T2	263990	9504	0	0
T3	283026	282459	0	0
T10	409463	14077	0	0
T11	196448	196439	0	0
T12	254526	160207	0	0
T16	107519	689	0	0
T18	5014	4948	0	0
T19	3144	2030	0	0
T20	61614	61516	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	590	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	0	0	0
T10	409463	2	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	2	0	0
T17	0	10	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T24	0	2	0	0
T25	0	1	0	0
T28	0	1	0	0
T49	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	577	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	0	0	0
T10	409463	2	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	2	0	0
T17	0	7	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T24	0	2	0	0
T25	0	1	0	0
T28	0	1	0	0
T49	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	570	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	0	0	0
T10	409463	2	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	2	0	0
T17	0	6	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T24	0	2	0	0
T25	0	1	0	0
T28	0	1	0	0
T49	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	562	0	0
T1	297961	1	0	0
T2	263990	1	0	0
T3	283026	0	0	0
T10	409463	2	0	0
T11	196448	0	0	0
T12	254526	0	0	0
T13	0	1	0	0
T16	107519	2	0	0
T17	0	6	0	0
T18	5014	0	0	0
T19	3144	0	0	0
T20	61614	0	0	0
T24	0	2	0	0
T25	0	1	0	0
T28	0	1	0	0
T49	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	2202	0	0
T4	190629	0	0	0
T6	0	1	0	0
T13	332485	0	0	0
T17	196944	0	0	0
T22	8542	4	0	0
T23	11177	1	0	0
T24	15756	1	0	0
T25	0	2	0	0
T26	0	6	0	0
T27	57479	0	0	0
T28	559197	0	0	0
T29	0	337	0	0
T48	45616	0	0	0
T49	831661	9	0	0
T50	0	1	0	0
T73	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	206160	0	0
T4	190629	0	0	0
T6	0	324	0	0
T13	332485	0	0	0
T17	196944	0	0	0
T22	8542	220	0	0
T23	11177	133	0	0
T24	15756	153	0	0
T25	0	266	0	0
T26	0	971	0	0
T27	57479	0	0	0
T28	559197	0	0	0
T29	0	42911	0	0
T48	45616	0	0	0
T49	831661	1023	0	0
T50	0	3	0	0
T73	0	307	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	2140	0	0
T4	190629	0	0	0
T13	332485	0	0	0
T17	196944	0	0	0
T22	8542	4	0	0
T23	11177	1	0	0
T24	15756	0	0	0
T25	0	1	0	0
T26	0	6	0	0
T27	57479	0	0	0
T28	559197	0	0	0
T29	0	336	0	0
T48	45616	0	0	0
T49	831661	9	0	0
T73	0	5	0	0
T91	0	8	0	0
T92	0	8	0	0
T110	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	32	0	0
T5	318173	0	0	0
T6	199534	1	0	0
T14	906857	0	0	0
T24	15756	1	0	0
T25	83815	1	0	0
T49	831661	0	0	0
T56	0	2	0	0
T68	2851	0	0	0
T69	25687	0	0	0
T70	41918	0	0	0
T90	9327	0	0	0
T94	0	1	0	0
T103	0	1	0	0
T118	0	1	0	0
T141	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	826	0	0
T7	17197	166	0	0
T8	0	178	0	0
T9	0	143	0	0
T37	0	165	0	0
T38	0	174	0	0
T39	95452	0	0	0
T40	122793	0	0	0
T41	93926	0	0	0
T42	63817	0	0	0
T43	224190	0	0	0
T44	93051	0	0	0
T45	201314	0	0	0
T46	4769	0	0	0
T47	17934	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	676	0	0
T7	17197	136	0	0
T8	0	148	0	0
T9	0	113	0	0
T37	0	135	0	0
T38	0	144	0	0
T39	95452	0	0	0
T40	122793	0	0	0
T41	93926	0	0	0
T42	63817	0	0	0
T43	224190	0	0	0
T44	93051	0	0	0
T45	201314	0	0	0
T46	4769	0	0	0
T47	17934	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703951978	703885357	0	0
T1	297961	297952	0	0
T2	263990	263983	0	0
T3	283026	283019	0	0
T10	409463	409455	0	0
T11	196448	196440	0	0
T12	254526	254433	0	0
T16	107519	107514	0	0
T18	5014	4949	0	0
T19	3144	3085	0	0
T20	61614	61517	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704141077	704010667	0	0
T1	297961	297952	0	0
T2	263990	263983	0	0
T3	283026	283019	0	0
T10	409463	409455	0	0
T11	196448	196440	0	0
T12	254526	254433	0	0
T16	107519	107514	0	0
T18	5014	4949	0	0
T19	3144	3085	0	0
T20	61614	61517	0	0